From 0183c56c11b4a6c3a66b5b1db44aa3582fe7f15b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 27 Jul 2018 09:15:03 +0000 Subject: [PATCH] AMDGPU: Fix code size for return_to_epilog pseudo llvm-svn: 338113 --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 +++--- llvm/lib/Target/AMDGPU/SIInstructions.td | 1 + llvm/test/CodeGen/AMDGPU/ret.ll | 6 ++++++ 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 41c029c9c785..6c85c92454c3 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -4753,12 +4753,12 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { if (DescSize != 0 && DescSize != 4) return DescSize; + if (isFixedSize(MI)) + return DescSize; + // 4-byte instructions may have a 32-bit literal encoded after them. Check // operands that coud ever be literals. if (isVALU(MI) || isSALU(MI)) { - if (isFixedSize(MI)) - return DescSize; - int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); if (Src0Idx == -1) return 4; // No operands. diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 2f9cdec61ed7..c3f8bfb53ef4 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -374,6 +374,7 @@ def SI_RETURN_TO_EPILOG : SPseudoInstSI < let isReturn = 1; let hasNoSchedulingInfo = 1; let DisableWQM = 1; + let FixedSize = 1; } // Return for returning function calls. diff --git a/llvm/test/CodeGen/AMDGPU/ret.ll b/llvm/test/CodeGen/AMDGPU/ret.ll index deedf365d2cd..265d37e8d641 100644 --- a/llvm/test/CodeGen/AMDGPU/ret.ll +++ b/llvm/test/CodeGen/AMDGPU/ret.ll @@ -241,6 +241,12 @@ bb: ret { { float, i32 }, { i32, <2 x float> } } { { float, i32 } { float 1.000000e+00, i32 2 }, { i32, <2 x float> } { i32 3, <2 x float> } } } +; GCN-LABEL: {{^}}ret_return_to_epilog_pseudo_size: +; GCN: codeLenInByte = 0{{$}} +define amdgpu_ps float @ret_return_to_epilog_pseudo_size() #0 { + ret float undef +} + declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 attributes #0 = { nounwind }