forked from OSchip/llvm-project
[AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP.
No need to be different here for the vast majority of rules.
This commit is contained in:
Amara Emerson
parent
e28c5899a2
commit
017b871502
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@ -326,8 +326,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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.legalFor({s32, s64})
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.clampScalar(0, s32, s64);
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getActionDefinitionsBuilder(G_ICMP)
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getActionDefinitionsBuilder({G_ICMP, G_FCMP})
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.legalFor({{s32, s32},
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{s32, s64},
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{s32, p0},
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@ -358,12 +358,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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.widenScalarOrEltToNextPow2(1)
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.clampNumElements(0, v2s32, v4s32);
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getActionDefinitionsBuilder(G_FCMP)
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.legalFor({{s32, s32}, {s32, s64}})
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.clampScalar(0, s32, s32)
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.clampScalar(1, s32, s64)
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.widenScalarToNextPow2(1);
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// Extensions
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auto ExtLegalFunc = [=](const LegalityQuery &Query) {
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unsigned DstSize = Query.Types[0].getSizeInBits();
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@ -1996,3 +1996,109 @@ body: |
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$d0 = COPY %7(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: fcmp_8xs1
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0' }
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- { reg: '$q1' }
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- { reg: '$q2' }
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- { reg: '$q3' }
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body: |
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bb.1:
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liveins: $q0, $q1, $q2, $q3
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; CHECK-LABEL: name: fcmp_8xs1
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; CHECK: liveins: $q0, $q1, $q2, $q3
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
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; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3
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; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY]](<4 x s32>), [[COPY2]]
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; CHECK: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY1]](<4 x s32>), [[COPY3]]
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; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>)
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
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; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
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; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>)
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; CHECK: RET_ReallyLR implicit $d0
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%2:_(<4 x s32>) = COPY $q0
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%3:_(<4 x s32>) = COPY $q1
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%0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)
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%4:_(<4 x s32>) = COPY $q2
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%5:_(<4 x s32>) = COPY $q3
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%1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)
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%6:_(<8 x s1>) = G_FCMP floatpred(one), %0(<8 x s32>), %1
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%7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>)
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$d0 = COPY %7(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: fcmp_8xs32
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0' }
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- { reg: '$q1' }
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- { reg: '$q2' }
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- { reg: '$q3' }
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body: |
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bb.1:
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liveins: $q0, $q1, $q2, $q3
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; CHECK-LABEL: name: fcmp_8xs32
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; CHECK: liveins: $q0, $q1, $q2, $q3
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
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; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3
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; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY]](<4 x s32>), [[COPY2]]
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; CHECK: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY1]](<4 x s32>), [[COPY3]]
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; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>)
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
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; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
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; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>)
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; CHECK: RET_ReallyLR implicit $d0
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%2:_(<4 x s32>) = COPY $q0
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%3:_(<4 x s32>) = COPY $q1
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%0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)
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%4:_(<4 x s32>) = COPY $q2
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%5:_(<4 x s32>) = COPY $q3
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%1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)
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%6:_(<8 x s32>) = G_FCMP floatpred(oeq), %0(<8 x s32>), %1
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%7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>)
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$d0 = COPY %7(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: fcmp_v4s32
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: fcmp_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(olt), [[COPY]](<4 x s32>), [[COPY1]]
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; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
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; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%2:_(<4 x s1>) = G_FCMP floatpred(olt), %0(<4 x s32>), %1
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%3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
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$d0 = COPY %3(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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@ -286,8 +286,9 @@
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_FCMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_SELECT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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