forked from OSchip/llvm-project
[DAG] make binops with undef operands consistent with IR
This started by noticing that scalar and vector types were producing different results with div ops in PR36305: https://bugs.llvm.org/show_bug.cgi?id=36305 ...but the problem is bigger. I couldn't keep it straight without a table, so I'm attaching that as a PDF to the review. The x86 tests in undef-ops.ll correspond to that table. Green means that instsimplify and the DAG agree on the result for all types. Red means the DAG was returning undef when IR was not. Yellow means the DAG was returning a non-undef result when IR returned undef. This patch assumes that we're currently doing the right thing in IR. Note: I couldn't find any problems with lowering vector constants as the code comments were warning, but those comments were written long ago in rL36413 . Differential Revision: https://reviews.llvm.org/D43141 llvm-svn: 324941
This commit is contained in:
Sanjay Patel
parent
e7ed880761
commit
014c000f6a
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@ -4667,19 +4667,15 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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case ISD::FSUB:
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case ISD::FDIV:
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case ISD::FREM:
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case ISD::SRA:
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return N1; // fold op(undef, arg2) -> undef
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case ISD::UDIV:
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case ISD::SDIV:
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case ISD::UREM:
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case ISD::SREM:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::SHL:
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if (!VT.isVector())
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return getConstant(0, DL, VT); // fold op(undef, arg2) -> 0
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// For vectors, we can't easily build an all zero vector, just return
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// the LHS.
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return N2;
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}
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}
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}
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@ -4701,6 +4697,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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case ISD::SDIV:
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case ISD::UREM:
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case ISD::SREM:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::SHL:
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return N2; // fold op(arg1, undef) -> undef
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case ISD::FADD:
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case ISD::FSUB:
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@ -4712,21 +4711,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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break;
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case ISD::MUL:
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case ISD::AND:
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case ISD::SRL:
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case ISD::SHL:
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if (!VT.isVector())
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return getConstant(0, DL, VT); // fold op(arg1, undef) -> 0
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// For vectors, we can't easily build an all zero vector, just return
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// the LHS.
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return N1;
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case ISD::OR:
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if (!VT.isVector())
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return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
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// For vectors, we can't easily build an all one vector, just return
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// the LHS.
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return N1;
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case ISD::SRA:
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return N1;
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return getAllOnesConstant(DL, VT);
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}
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}
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@ -5,7 +5,7 @@
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; subregisters were dropped by the tail duplicator, resulting in invalid
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; COPY instructions being generated.
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; CHECK: = extractu(r{{[0-9]+}},#15,#17)
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; CHECK: = asl(r{{[0-9]+}}:{{[0-9]+}},#15)
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target triple = "hexagon"
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@ -36,20 +36,20 @@ if.then5.i: ; preds = %if.then.i
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br label %if.end.i
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if.else.i: ; preds = %if.then.i
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%shl12.i = shl i64 %0, undef
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%shl12.i = shl i64 %0, 7
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br label %if.end.i
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if.end.i: ; preds = %if.else.i, %if.then5.i
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%aSig0.0 = phi i64 [ undef, %if.then5.i ], [ %shl12.i, %if.else.i ]
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%storemerge43.i = phi i64 [ %shl.i21, %if.then5.i ], [ 0, %if.else.i ]
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%sub15.i = sub nsw i32 -63, undef
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%sub15.i = sub nsw i32 -63, 8
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br label %if.end13
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if.else16.i: ; preds = %if.then7
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br label %if.end13
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if.else: ; preds = %entry
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%or12 = or i64 undef, 281474976710656
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%or12 = or i64 9, 281474976710656
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br label %if.end13
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if.end13: ; preds = %if.else, %if.else16.i, %if.end.i
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@ -31,7 +31,6 @@ define float @pr26070() {
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; CHECK-NEXT: orps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%c = call float @copysignf(float 1.0, float undef) readnone
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ret float %c
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@ -7,12 +7,12 @@
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define void @PR33960() {
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; X86-LABEL: PR33960:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl $0, b
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; X86-NEXT: movl $-1, b
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; X86-NEXT: retl
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;
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; X64-LABEL: PR33960:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movl $0, {{.*}}(%rip)
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; X64-NEXT: movl $-1, {{.*}}(%rip)
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; X64-NEXT: retq
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entry:
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%tmp = insertelement <4 x i32> <i32 undef, i32 -7, i32 -3, i32 undef>, i32 -2, i32 3
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@ -77,6 +77,7 @@ define i32 @mul_undef_rhs(i32 %x) {
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define <4 x i32> @mul_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: mul_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = mul <4 x i32> %x, undef
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ret <4 x i32> %r
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@ -94,6 +95,7 @@ define i32 @mul_undef_lhs(i32 %x) {
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define <4 x i32> @mul_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: mul_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = mul <4 x i32> undef, %x
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ret <4 x i32> %r
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@ -127,6 +129,7 @@ define i32 @sdiv_undef_lhs(i32 %x) {
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define <4 x i32> @sdiv_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: sdiv_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = sdiv <4 x i32> undef, %x
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ret <4 x i32> %r
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@ -160,6 +163,7 @@ define i32 @udiv_undef_lhs(i32 %x) {
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define <4 x i32> @udiv_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: udiv_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = udiv <4 x i32> undef, %x
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ret <4 x i32> %r
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@ -193,6 +197,7 @@ define i32 @srem_undef_lhs(i32 %x) {
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define <4 x i32> @srem_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: srem_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = srem <4 x i32> undef, %x
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ret <4 x i32> %r
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@ -226,6 +231,7 @@ define i32 @urem_undef_lhs(i32 %x) {
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define <4 x i32> @urem_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: urem_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = urem <4 x i32> undef, %x
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ret <4 x i32> %r
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@ -234,7 +240,6 @@ define <4 x i32> @urem_undef_lhs_vec(<4 x i32> %x) {
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define i32 @ashr_undef_rhs(i32 %x) {
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; CHECK-LABEL: ashr_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%r = ashr i32 %x, undef
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ret i32 %r
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@ -251,6 +256,7 @@ define <4 x i32> @ashr_undef_rhs_vec(<4 x i32> %x) {
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define i32 @ashr_undef_lhs(i32 %x) {
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; CHECK-LABEL: ashr_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = ashr i32 undef, %x
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ret i32 %r
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@ -259,6 +265,7 @@ define i32 @ashr_undef_lhs(i32 %x) {
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define <4 x i32> @ashr_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: ashr_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = ashr <4 x i32> undef, %x
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ret <4 x i32> %r
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@ -267,7 +274,6 @@ define <4 x i32> @ashr_undef_lhs_vec(<4 x i32> %x) {
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define i32 @lshr_undef_rhs(i32 %x) {
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; CHECK-LABEL: lshr_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = lshr i32 %x, undef
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ret i32 %r
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@ -293,6 +299,7 @@ define i32 @lshr_undef_lhs(i32 %x) {
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define <4 x i32> @lshr_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: lshr_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = lshr <4 x i32> undef, %x
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ret <4 x i32> %r
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@ -301,7 +308,6 @@ define <4 x i32> @lshr_undef_lhs_vec(<4 x i32> %x) {
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define i32 @shl_undef_rhs(i32 %x) {
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; CHECK-LABEL: shl_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = shl i32 %x, undef
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ret i32 %r
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@ -327,6 +333,7 @@ define i32 @shl_undef_lhs(i32 %x) {
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define <4 x i32> @shl_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: shl_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = shl <4 x i32> undef, %x
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ret <4 x i32> %r
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@ -344,6 +351,7 @@ define i32 @and_undef_rhs(i32 %x) {
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define <4 x i32> @and_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: and_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = and <4 x i32> %x, undef
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ret <4 x i32> %r
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@ -361,6 +369,7 @@ define i32 @and_undef_lhs(i32 %x) {
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define <4 x i32> @and_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: and_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = and <4 x i32> undef, %x
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ret <4 x i32> %r
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@ -378,6 +387,7 @@ define i32 @or_undef_rhs(i32 %x) {
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define <4 x i32> @or_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: or_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = or <4 x i32> %x, undef
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ret <4 x i32> %r
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@ -395,6 +405,7 @@ define i32 @or_undef_lhs(i32 %x) {
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define <4 x i32> @or_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: or_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = or <4 x i32> undef, %x
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ret <4 x i32> %r
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