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[X86] Add tests showing failure to merge shuffles through avx2 shift binops

This commit is contained in:
Simon Pilgrim 2022-01-13 15:25:13 +00:00
parent ec5b63ba96
commit 01494c6a73
1 changed files with 49 additions and 0 deletions
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49
llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll
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@ -122,6 +122,55 @@ define <4 x i64> @demandedelts_vpsrlvq(<4 x i64> %a0, <4 x i64> %a1) {
ret <4 x i64> %result ret <4 x i64> %result
} }
;
; isBinOp Handling (TODO)
;
define <4 x i32> @binop_shuffle_vpsllvd(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: binop_shuffle_vpsllvd:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; CHECK-NEXT: retq
%shuffle0 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%shuffle1 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%shift = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %shuffle0, <4 x i32> %shuffle1)
%res = shufflevector <4 x i32> %shift, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i32> %res
}
define <8 x i32> @binop_shuffle_vpsravd(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-LABEL: binop_shuffle_vpsravd:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
; CHECK-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[3,2,1,0,7,6,5,4]
; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
; CHECK-NEXT: retq
%shuffle0 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
%shuffle1 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
%shift = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %shuffle0, <8 x i32> %shuffle1)
%res = shufflevector <8 x i32> %shift, <8 x i32> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
ret <8 x i32> %res
}
define <4 x i64> @binop_shuffle_vpsrlvq(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-LABEL: binop_shuffle_vpsrlvq:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; CHECK-NEXT: vpermq {{.*#+}} ymm1 = ymm1[3,2,1,0]
; CHECK-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; CHECK-NEXT: retq
%shuffle0 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%shuffle1 = shufflevector <4 x i64> %a1, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%shift = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %shuffle0, <4 x i64> %shuffle1)
%res = shufflevector <4 x i64> %shift, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i64> %res
}
declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i32) declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i32)
declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i32) declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i32)
declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i32) declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i32)