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Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This 

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243
This commit is contained in:
Stuart Hastings 2010-06-17 22:43:56 +00:00
parent 6fdb139cdd
commit 0125b6410a
34 changed files with 137 additions and 126 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/include/llvm/CodeGen/FastISel.h
View File

@ -286,7 +286,7 @@ protected:
/// FastEmitBranch - Emit an unconditional branch to the given block, /// FastEmitBranch - Emit an unconditional branch to the given block,
/// unless it is the immediate (fall-through) successor, and update /// unless it is the immediate (fall-through) successor, and update
/// the CFG. /// the CFG.
void FastEmitBranch(MachineBasicBlock *MBB); void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
unsigned UpdateValueMap(const Value* I, unsigned Reg); unsigned UpdateValueMap(const Value* I, unsigned Reg);

5
llvm/include/llvm/Target/TargetInstrInfo.h
View File

@ -315,8 +315,9 @@ public:
/// branch to analyze. At least this much must be implemented, else tail /// branch to analyze. At least this much must be implemented, else tail
/// merging needs to be disabled. /// merging needs to be disabled.
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const {
assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
return 0; return 0;
} }

31
llvm/lib/CodeGen/BranchFolding.cpp
View File

@ -373,7 +373,8 @@ void BranchFolder::ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
// If OldBB isn't immediately before OldBB, insert a branch to it. // If OldBB isn't immediately before OldBB, insert a branch to it.
if (++MachineFunction::iterator(OldBB) != MachineFunction::iterator(NewDest)) if (++MachineFunction::iterator(OldBB) != MachineFunction::iterator(NewDest))
TII->InsertBranch(*OldBB, NewDest, 0, SmallVector<MachineOperand, 0>()); TII->InsertBranch(*OldBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
OldInst->getDebugLoc());
OldBB->addSuccessor(NewDest); OldBB->addSuccessor(NewDest);
++NumTailMerge; ++NumTailMerge;
} }
@ -443,18 +444,20 @@ static void FixTail(MachineBasicBlock *CurMBB, MachineBasicBlock *SuccBB,
MachineFunction::iterator I = llvm::next(MachineFunction::iterator(CurMBB)); MachineFunction::iterator I = llvm::next(MachineFunction::iterator(CurMBB));
MachineBasicBlock *TBB = 0, *FBB = 0; MachineBasicBlock *TBB = 0, *FBB = 0;
SmallVector<MachineOperand, 4> Cond; SmallVector<MachineOperand, 4> Cond;
DebugLoc dl; // FIXME: this is nowhere
if (I != MF->end() && if (I != MF->end() &&
!TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) {
MachineBasicBlock *NextBB = I; MachineBasicBlock *NextBB = I;
if (TBB == NextBB && !Cond.empty() && !FBB) { if (TBB == NextBB && !Cond.empty() && !FBB) {
if (!TII->ReverseBranchCondition(Cond)) { if (!TII->ReverseBranchCondition(Cond)) {
TII->RemoveBranch(*CurMBB); TII->RemoveBranch(*CurMBB);
TII->InsertBranch(*CurMBB, SuccBB, NULL, Cond); TII->InsertBranch(*CurMBB, SuccBB, NULL, Cond, dl);
return; return;
} }
} }
} }
TII->InsertBranch(*CurMBB, SuccBB, NULL, SmallVector<MachineOperand, 0>()); TII->InsertBranch(*CurMBB, SuccBB, NULL,
SmallVector<MachineOperand, 0>(), dl);
} }
bool bool
@ -874,10 +877,11 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
} }
// Remove the unconditional branch at the end, if any. // Remove the unconditional branch at the end, if any.
if (TBB && (Cond.empty() || FBB)) { if (TBB && (Cond.empty() || FBB)) {
DebugLoc dl; // FIXME: this is nowhere
TII->RemoveBranch(*PBB); TII->RemoveBranch(*PBB);
if (!Cond.empty()) if (!Cond.empty())
// reinsert conditional branch only, for now // reinsert conditional branch only, for now
TII->InsertBranch(*PBB, (TBB == IBB) ? FBB : TBB, 0, NewCond); TII->InsertBranch(*PBB, (TBB == IBB) ? FBB : TBB, 0, NewCond, dl);
} }
MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(PBB), *P)); MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(PBB), *P));
} }
@ -976,6 +980,7 @@ static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) { bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
bool MadeChange = false; bool MadeChange = false;
MachineFunction &MF = *MBB->getParent(); MachineFunction &MF = *MBB->getParent();
DebugLoc dl; // FIXME: this is nowhere
ReoptimizeBlock: ReoptimizeBlock:
MachineFunction::iterator FallThrough = MBB; MachineFunction::iterator FallThrough = MBB;
@ -1027,7 +1032,7 @@ ReoptimizeBlock:
TII->RemoveBranch(PrevBB); TII->RemoveBranch(PrevBB);
PriorCond.clear(); PriorCond.clear();
if (PriorTBB != MBB) if (PriorTBB != MBB)
TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond); TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond, dl);
MadeChange = true; MadeChange = true;
++NumBranchOpts; ++NumBranchOpts;
goto ReoptimizeBlock; goto ReoptimizeBlock;
@ -1066,7 +1071,7 @@ ReoptimizeBlock:
// the condition is false, remove the uncond second branch. // the condition is false, remove the uncond second branch.
if (PriorFBB == MBB) { if (PriorFBB == MBB) {
TII->RemoveBranch(PrevBB); TII->RemoveBranch(PrevBB);
TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond); TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond, dl);
MadeChange = true; MadeChange = true;
++NumBranchOpts; ++NumBranchOpts;
goto ReoptimizeBlock; goto ReoptimizeBlock;
@ -1079,7 +1084,7 @@ ReoptimizeBlock:
SmallVector<MachineOperand, 4> NewPriorCond(PriorCond); SmallVector<MachineOperand, 4> NewPriorCond(PriorCond);
if (!TII->ReverseBranchCondition(NewPriorCond)) { if (!TII->ReverseBranchCondition(NewPriorCond)) {
TII->RemoveBranch(PrevBB); TII->RemoveBranch(PrevBB);
TII->InsertBranch(PrevBB, PriorFBB, 0, NewPriorCond); TII->InsertBranch(PrevBB, PriorFBB, 0, NewPriorCond, dl);
MadeChange = true; MadeChange = true;
++NumBranchOpts; ++NumBranchOpts;
goto ReoptimizeBlock; goto ReoptimizeBlock;
@ -1116,7 +1121,7 @@ ReoptimizeBlock:
<< "To make fallthrough to: " << *PriorTBB << "\n"); << "To make fallthrough to: " << *PriorTBB << "\n");
TII->RemoveBranch(PrevBB); TII->RemoveBranch(PrevBB);
TII->InsertBranch(PrevBB, MBB, 0, NewPriorCond); TII->InsertBranch(PrevBB, MBB, 0, NewPriorCond, dl);
// Move this block to the end of the function. // Move this block to the end of the function.
MBB->moveAfter(--MF.end()); MBB->moveAfter(--MF.end());
@ -1145,7 +1150,7 @@ ReoptimizeBlock:
SmallVector<MachineOperand, 4> NewCond(CurCond); SmallVector<MachineOperand, 4> NewCond(CurCond);
if (!TII->ReverseBranchCondition(NewCond)) { if (!TII->ReverseBranchCondition(NewCond)) {
TII->RemoveBranch(*MBB); TII->RemoveBranch(*MBB);
TII->InsertBranch(*MBB, CurFBB, CurTBB, NewCond); TII->InsertBranch(*MBB, CurFBB, CurTBB, NewCond, dl);
MadeChange = true; MadeChange = true;
++NumBranchOpts; ++NumBranchOpts;
goto ReoptimizeBlock; goto ReoptimizeBlock;
@ -1200,7 +1205,7 @@ ReoptimizeBlock:
PriorFBB = MBB; PriorFBB = MBB;
} }
TII->RemoveBranch(PrevBB); TII->RemoveBranch(PrevBB);
TII->InsertBranch(PrevBB, PriorTBB, PriorFBB, PriorCond); TII->InsertBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, dl);
} }
// Iterate through all the predecessors, revectoring each in-turn. // Iterate through all the predecessors, revectoring each in-turn.
@ -1226,7 +1231,7 @@ ReoptimizeBlock:
if (!NewCurUnAnalyzable && NewCurTBB && NewCurTBB == NewCurFBB) { if (!NewCurUnAnalyzable && NewCurTBB && NewCurTBB == NewCurFBB) {
TII->RemoveBranch(*PMBB); TII->RemoveBranch(*PMBB);
NewCurCond.clear(); NewCurCond.clear();
TII->InsertBranch(*PMBB, NewCurTBB, 0, NewCurCond); TII->InsertBranch(*PMBB, NewCurTBB, 0, NewCurCond, dl);
MadeChange = true; MadeChange = true;
++NumBranchOpts; ++NumBranchOpts;
PMBB->CorrectExtraCFGEdges(NewCurTBB, 0, false); PMBB->CorrectExtraCFGEdges(NewCurTBB, 0, false);
@ -1246,7 +1251,7 @@ ReoptimizeBlock:
} }
// Add the branch back if the block is more than just an uncond branch. // Add the branch back if the block is more than just an uncond branch.
TII->InsertBranch(*MBB, CurTBB, 0, CurCond); TII->InsertBranch(*MBB, CurTBB, 0, CurCond, dl);
} }
} }
@ -1286,7 +1291,7 @@ ReoptimizeBlock:
if (CurFallsThru) { if (CurFallsThru) {
MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB)); MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
CurCond.clear(); CurCond.clear();
TII->InsertBranch(*MBB, NextBB, 0, CurCond); TII->InsertBranch(*MBB, NextBB, 0, CurCond, dl);
} }
MBB->moveAfter(PredBB); MBB->moveAfter(PredBB);
MadeChange = true; MadeChange = true;

9
llvm/lib/CodeGen/IfConversion.cpp
View File

@ -395,9 +395,10 @@ static MachineBasicBlock *findFalseBlock(MachineBasicBlock *BB,
/// ReverseBranchCondition - Reverse the condition of the end of the block /// ReverseBranchCondition - Reverse the condition of the end of the block
/// branch. Swap block's 'true' and 'false' successors. /// branch. Swap block's 'true' and 'false' successors.
bool IfConverter::ReverseBranchCondition(BBInfo &BBI) { bool IfConverter::ReverseBranchCondition(BBInfo &BBI) {
DebugLoc dl; // FIXME: this is nowhere
if (!TII->ReverseBranchCondition(BBI.BrCond)) { if (!TII->ReverseBranchCondition(BBI.BrCond)) {
TII->RemoveBranch(*BBI.BB); TII->RemoveBranch(*BBI.BB);
TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond); TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
std::swap(BBI.TrueBB, BBI.FalseBB); std::swap(BBI.TrueBB, BBI.FalseBB);
return true; return true;
} }
@ -862,8 +863,9 @@ void IfConverter::InvalidatePreds(MachineBasicBlock *BB) {
/// ///
static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB, static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB,
const TargetInstrInfo *TII) { const TargetInstrInfo *TII) {
DebugLoc dl; // FIXME: this is nowhere
SmallVector<MachineOperand, 0> NoCond; SmallVector<MachineOperand, 0> NoCond;
TII->InsertBranch(*BB, ToBB, NULL, NoCond); TII->InsertBranch(*BB, ToBB, NULL, NoCond, dl);
} }
/// RemoveExtraEdges - Remove true / false edges if either / both are no longer /// RemoveExtraEdges - Remove true / false edges if either / both are no longer
@ -1014,6 +1016,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()]; BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
BBInfo *CvtBBI = &TrueBBI; BBInfo *CvtBBI = &TrueBBI;
BBInfo *NextBBI = &FalseBBI; BBInfo *NextBBI = &FalseBBI;
DebugLoc dl; // FIXME: this is nowhere
SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end()); SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
if (Kind == ICTriangleFalse || Kind == ICTriangleFRev) if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
@ -1078,7 +1081,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
CvtBBI->BrCond.end()); CvtBBI->BrCond.end());
if (TII->ReverseBranchCondition(RevCond)) if (TII->ReverseBranchCondition(RevCond))
assert(false && "Unable to reverse branch condition!"); assert(false && "Unable to reverse branch condition!");
TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond); TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond, dl);
BBI.BB->addSuccessor(CvtBBI->FalseBB); BBI.BB->addSuccessor(CvtBBI->FalseBB);
} }

13
llvm/lib/CodeGen/MachineBasicBlock.cpp
View File

@ -245,6 +245,7 @@ void MachineBasicBlock::updateTerminator() {
MachineBasicBlock *TBB = 0, *FBB = 0; MachineBasicBlock *TBB = 0, *FBB = 0;
SmallVector<MachineOperand, 4> Cond; SmallVector<MachineOperand, 4> Cond;
DebugLoc dl; // FIXME: this is nowhere
bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond); bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
(void) B; (void) B;
assert(!B && "UpdateTerminators requires analyzable predecessors!"); assert(!B && "UpdateTerminators requires analyzable predecessors!");
@ -259,7 +260,7 @@ void MachineBasicBlock::updateTerminator() {
// its layout successor, insert a branch. // its layout successor, insert a branch.
TBB = *succ_begin(); TBB = *succ_begin();
if (!isLayoutSuccessor(TBB)) if (!isLayoutSuccessor(TBB))
TII->InsertBranch(*this, TBB, 0, Cond); TII->InsertBranch(*this, TBB, 0, Cond, dl);
} }
} else { } else {
if (FBB) { if (FBB) {
@ -270,10 +271,10 @@ void MachineBasicBlock::updateTerminator() {
if (TII->ReverseBranchCondition(Cond)) if (TII->ReverseBranchCondition(Cond))
return; return;
TII->RemoveBranch(*this); TII->RemoveBranch(*this);
TII->InsertBranch(*this, FBB, 0, Cond); TII->InsertBranch(*this, FBB, 0, Cond, dl);
} else if (isLayoutSuccessor(FBB)) { } else if (isLayoutSuccessor(FBB)) {
TII->RemoveBranch(*this); TII->RemoveBranch(*this);
TII->InsertBranch(*this, TBB, 0, Cond); TII->InsertBranch(*this, TBB, 0, Cond, dl);
} }
} else { } else {
// The block has a fallthrough conditional branch. // The block has a fallthrough conditional branch.
@ -284,14 +285,14 @@ void MachineBasicBlock::updateTerminator() {
if (TII->ReverseBranchCondition(Cond)) { if (TII->ReverseBranchCondition(Cond)) {
// We can't reverse the condition, add an unconditional branch. // We can't reverse the condition, add an unconditional branch.
Cond.clear(); Cond.clear();
TII->InsertBranch(*this, MBBA, 0, Cond); TII->InsertBranch(*this, MBBA, 0, Cond, dl);
return; return;
} }
TII->RemoveBranch(*this); TII->RemoveBranch(*this);
TII->InsertBranch(*this, MBBA, 0, Cond); TII->InsertBranch(*this, MBBA, 0, Cond, dl);
} else if (!isLayoutSuccessor(MBBA)) { } else if (!isLayoutSuccessor(MBBA)) {
TII->RemoveBranch(*this); TII->RemoveBranch(*this);
TII->InsertBranch(*this, TBB, MBBA, Cond); TII->InsertBranch(*this, TBB, MBBA, Cond, dl);
} }
} }
} }

3
llvm/lib/CodeGen/PHIElimination.cpp
View File

@ -402,6 +402,7 @@ MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
assert(A && B && "Missing MBB end point"); assert(A && B && "Missing MBB end point");
MachineFunction *MF = A->getParent(); MachineFunction *MF = A->getParent();
DebugLoc dl; // FIXME: this is nowhere
// We may need to update A's terminator, but we can't do that if AnalyzeBranch // We may need to update A's terminator, but we can't do that if AnalyzeBranch
// fails. If A uses a jump table, we won't touch it. // fails. If A uses a jump table, we won't touch it.
@ -427,7 +428,7 @@ MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
NMBB->addSuccessor(B); NMBB->addSuccessor(B);
if (!NMBB->isLayoutSuccessor(B)) { if (!NMBB->isLayoutSuccessor(B)) {
Cond.clear(); Cond.clear();
MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond); MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond, dl);
} }
// Fix PHI nodes in B so they refer to NMBB instead of A // Fix PHI nodes in B so they refer to NMBB instead of A

6
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -655,12 +655,12 @@ FastISel::SelectInstruction(const Instruction *I) {
/// unless it is the immediate (fall-through) successor, and update /// unless it is the immediate (fall-through) successor, and update
/// the CFG. /// the CFG.
void void
FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
if (MBB->isLayoutSuccessor(MSucc)) { if (MBB->isLayoutSuccessor(MSucc)) {
// The unconditional fall-through case, which needs no instructions. // The unconditional fall-through case, which needs no instructions.
} else { } else {
// The unconditional branch case. // The unconditional branch case.
TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>(), DL);
} }
MBB->addSuccessor(MSucc); MBB->addSuccessor(MSucc);
} }
@ -763,7 +763,7 @@ FastISel::SelectOperator(const User *I, unsigned Opcode) {
if (BI->isUnconditional()) { if (BI->isUnconditional()) {
const BasicBlock *LLVMSucc = BI->getSuccessor(0); const BasicBlock *LLVMSucc = BI->getSuccessor(0);
MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
FastEmitBranch(MSucc); FastEmitBranch(MSucc, BI->getDebugLoc());
return true; return true;
} }

16
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -347,11 +347,9 @@ unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned unsigned
ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
// FIXME this should probably have a DebugLoc argument DebugLoc DL) const {
DebugLoc dl;
ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
int BOpc = !AFI->isThumbFunction() int BOpc = !AFI->isThumbFunction()
? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
@ -365,17 +363,17 @@ ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
if (FBB == 0) { if (FBB == 0) {
if (Cond.empty()) // Unconditional branch? if (Cond.empty()) // Unconditional branch?
BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
else else
BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
return 1; return 1;
} }
// Two-way conditional branch. // Two-way conditional branch.
BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
return 2; return 2;
} }

3
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -225,7 +225,8 @@ public:
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;

17
llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -110,9 +110,8 @@ static bool isAlphaIntCondCode(unsigned Opcode) {
unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
// FIXME this should probably have a DebugLoc argument DebugLoc DL) const {
DebugLoc dl;
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) && assert((Cond.size() == 2 || Cond.size() == 0) &&
"Alpha branch conditions have two components!"); "Alpha branch conditions have two components!");
@ -120,25 +119,25 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
// One-way branch. // One-way branch.
if (FBB == 0) { if (FBB == 0) {
if (Cond.empty()) // Unconditional branch if (Cond.empty()) // Unconditional branch
BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB); BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(TBB);
else // Conditional branch else // Conditional branch
if (isAlphaIntCondCode(Cond[0].getImm())) if (isAlphaIntCondCode(Cond[0].getImm()))
BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else else
BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return 1; return 1;
} }
// Two-way Conditional Branch. // Two-way Conditional Branch.
if (isAlphaIntCondCode(Cond[0].getImm())) if (isAlphaIntCondCode(Cond[0].getImm()))
BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else else
BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB); BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(FBB);
return 2; return 2;
} }

5
llvm/lib/Target/Alpha/AlphaInstrInfo.h
View File

@ -42,8 +42,9 @@ public:
int &FrameIndex) const; int &FrameIndex) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB, virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,

6
llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp
View File

@ -104,10 +104,8 @@ unsigned BlackfinInstrInfo::
InsertBranch(MachineBasicBlock &MBB, InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
// FIXME this should probably have a DebugLoc operand DebugLoc DL) const {
DebugLoc DL;
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) && assert((Cond.size() == 1 || Cond.size() == 0) &&

3
llvm/lib/Target/Blackfin/BlackfinInstrInfo.h
View File

@ -44,7 +44,8 @@ namespace llvm {
InsertBranch(MachineBasicBlock &MBB, InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB, virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,

13
llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -554,9 +554,8 @@ SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned unsigned
SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
// FIXME this should probably have a DebugLoc argument DebugLoc DL) const {
DebugLoc dl;
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) && assert((Cond.size() == 2 || Cond.size() == 0) &&
@ -566,14 +565,14 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
if (FBB == 0) { if (FBB == 0) {
if (Cond.empty()) { if (Cond.empty()) {
// Unconditional branch // Unconditional branch
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR)); MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(SPU::BR));
MIB.addMBB(TBB); MIB.addMBB(TBB);
DEBUG(errs() << "Inserted one-way uncond branch: "); DEBUG(errs() << "Inserted one-way uncond branch: ");
DEBUG((*MIB).dump()); DEBUG((*MIB).dump());
} else { } else {
// Conditional branch // Conditional branch
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm())); MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
MIB.addReg(Cond[1].getReg()).addMBB(TBB); MIB.addReg(Cond[1].getReg()).addMBB(TBB);
DEBUG(errs() << "Inserted one-way cond branch: "); DEBUG(errs() << "Inserted one-way cond branch: ");
@ -581,8 +580,8 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
} }
return 1; return 1;
} else { } else {
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm())); MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR)); MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
// Two-way Conditional Branch. // Two-way Conditional Branch.
MIB.addReg(Cond[1].getReg()).addMBB(TBB); MIB.addReg(Cond[1].getReg()).addMBB(TBB);

5
llvm/lib/Target/CellSPU/SPUInstrInfo.h
View File

@ -94,8 +94,9 @@ namespace llvm {
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
}; };
} }

5
llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp
View File

@ -185,10 +185,11 @@ foldMemoryOperandImpl(MachineFunction &MF,
unsigned MBlazeInstrInfo:: unsigned MBlazeInstrInfo::
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const {
// Can only insert uncond branches so far. // Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
BuildMI(&MBB, DebugLoc(), get(MBlaze::BRI)).addMBB(TBB); BuildMI(&MBB, DL, get(MBlaze::BRI)).addMBB(TBB);
return 1; return 1;
} }

3
llvm/lib/Target/MBlaze/MBlazeInstrInfo.h
View File

@ -198,7 +198,8 @@ public:
/// Branch Analysis /// Branch Analysis
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB, virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,

6
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -330,10 +330,8 @@ bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
unsigned unsigned
MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
// FIXME this should probably have a DebugLoc operand DebugLoc DL) const {
DebugLoc DL;
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) && assert((Cond.size() == 1 || Cond.size() == 0) &&

3
llvm/lib/Target/MSP430/MSP430InstrInfo.h
View File

@ -93,7 +93,8 @@ public:
unsigned RemoveBranch(MachineBasicBlock &MBB) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
}; };

17
llvm/lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -520,9 +520,8 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
unsigned MipsInstrInfo:: unsigned MipsInstrInfo::
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
// FIXME this should probably have a DebugLoc argument DebugLoc DL) const {
DebugLoc dl;
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) && assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
@ -531,18 +530,18 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
if (FBB == 0) { // One way branch. if (FBB == 0) { // One way branch.
if (Cond.empty()) { if (Cond.empty()) {
// Unconditional branch? // Unconditional branch?
BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB); BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
} else { } else {
// Conditional branch. // Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
const TargetInstrDesc &TID = get(Opc); const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3) if (TID.getNumOperands() == 3)
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
.addReg(Cond[2].getReg()) .addReg(Cond[2].getReg())
.addMBB(TBB); .addMBB(TBB);
else else
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
.addMBB(TBB); .addMBB(TBB);
} }
@ -554,12 +553,12 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
const TargetInstrDesc &TID = get(Opc); const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3) if (TID.getNumOperands() == 3)
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg()) BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
.addMBB(TBB); .addMBB(TBB);
else else
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB); BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB); BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
return 2; return 2;
} }

3
llvm/lib/Target/Mips/MipsInstrInfo.h
View File

@ -204,7 +204,8 @@ public:
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB, virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,

6
llvm/lib/Target/PIC16/PIC16InstrInfo.cpp
View File

@ -196,15 +196,15 @@ bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned PIC16InstrInfo:: unsigned PIC16InstrInfo::
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
if (FBB == 0) { // One way branch. if (FBB == 0) { // One way branch.
if (Cond.empty()) { if (Cond.empty()) {
// Unconditional branch? // Unconditional branch?
DebugLoc dl; BuildMI(&MBB, DL, get(PIC16::br_uncond)).addMBB(TBB);
BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
} }
return 1; return 1;
} }

3
llvm/lib/Target/PIC16/PIC16InstrInfo.h
View File

@ -70,7 +70,8 @@ public:
virtual virtual
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond, SmallVectorImpl<MachineOperand> &Cond,

13
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -316,9 +316,8 @@ unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned unsigned
PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
// FIXME this should probably have a DebugLoc argument DebugLoc DL) const {
DebugLoc dl;
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) && assert((Cond.size() == 2 || Cond.size() == 0) &&
@ -327,17 +326,17 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
// One-way branch. // One-way branch.
if (FBB == 0) { if (FBB == 0) {
if (Cond.empty()) // Unconditional branch if (Cond.empty()) // Unconditional branch
BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB); BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
else // Conditional branch else // Conditional branch
BuildMI(&MBB, dl, get(PPC::BCC)) BuildMI(&MBB, DL, get(PPC::BCC))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return 1; return 1;
} }
// Two-way Conditional Branch. // Two-way Conditional Branch.
BuildMI(&MBB, dl, get(PPC::BCC)) BuildMI(&MBB, DL, get(PPC::BCC))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB); BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
return 2; return 2;
} }

3
llvm/lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -109,7 +109,8 @@ public:
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB, virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,

7
llvm/lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -109,12 +109,11 @@ unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
unsigned unsigned
SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond)const{ const SmallVectorImpl<MachineOperand> &Cond,
// FIXME this should probably take a DebugLoc argument DebugLoc DL)const{
DebugLoc dl;
// Can only insert uncond branches so far. // Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB); BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
return 1; return 1;
} }

3
llvm/lib/Target/Sparc/SparcInstrInfo.h
View File

@ -68,7 +68,8 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB, virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,

5
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -521,9 +521,8 @@ unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned unsigned
SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
// FIXME: this should probably have a DebugLoc operand DebugLoc DL) const {
DebugLoc DL;
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) && assert((Cond.size() == 1 || Cond.size() == 0) &&

3
llvm/lib/Target/SystemZ/SystemZInstrInfo.h
View File

@ -102,7 +102,8 @@ public:
bool AllowModify) const; bool AllowModify) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const; SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;

6
llvm/lib/Target/X86/X86FastISel.cpp
View File

@ -891,7 +891,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB); BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
} }
FastEmitBranch(FalseMBB); FastEmitBranch(FalseMBB, DL);
MBB->addSuccessor(TrueMBB); MBB->addSuccessor(TrueMBB);
return true; return true;
} }
@ -946,7 +946,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
X86::JO_4 : X86::JB_4)) X86::JO_4 : X86::JB_4))
.addMBB(TrueMBB); .addMBB(TrueMBB);
FastEmitBranch(FalseMBB); FastEmitBranch(FalseMBB, DL);
MBB->addSuccessor(TrueMBB); MBB->addSuccessor(TrueMBB);
return true; return true;
} }
@ -961,7 +961,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB); BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
FastEmitBranch(FalseMBB); FastEmitBranch(FalseMBB, DL);
MBB->addSuccessor(TrueMBB); MBB->addSuccessor(TrueMBB);
return true; return true;
} }

19
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -1839,9 +1839,8 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned unsigned
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond,
// FIXME this should probably have a DebugLoc operand DebugLoc DL) const {
DebugLoc dl;
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) && assert((Cond.size() == 1 || Cond.size() == 0) &&
@ -1850,7 +1849,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
if (Cond.empty()) { if (Cond.empty()) {
// Unconditional branch? // Unconditional branch?
assert(!FBB && "Unconditional branch with multiple successors!"); assert(!FBB && "Unconditional branch with multiple successors!");
BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB); BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
return 1; return 1;
} }
@ -1860,27 +1859,27 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
switch (CC) { switch (CC) {
case X86::COND_NP_OR_E: case X86::COND_NP_OR_E:
// Synthesize NP_OR_E with two branches. // Synthesize NP_OR_E with two branches.
BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB); BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
++Count; ++Count;
BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB); BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
++Count; ++Count;
break; break;
case X86::COND_NE_OR_P: case X86::COND_NE_OR_P:
// Synthesize NE_OR_P with two branches. // Synthesize NE_OR_P with two branches.
BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB); BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
++Count; ++Count;
BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB); BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
++Count; ++Count;
break; break;
default: { default: {
unsigned Opc = GetCondBranchFromCond(CC); unsigned Opc = GetCondBranchFromCond(CC);
BuildMI(&MBB, dl, get(Opc)).addMBB(TBB); BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
++Count; ++Count;
} }
} }
if (FBB) { if (FBB) {
// Two-way Conditional branch. Insert the second branch. // Two-way Conditional branch. Insert the second branch.
BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB); BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
++Count; ++Count;
} }
return Count; return Count;

3
llvm/lib/Target/X86/X86InstrInfo.h
View File

@ -612,7 +612,8 @@ public:
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB, virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,

13
llvm/lib/Target/XCore/XCoreInstrInfo.cpp
View File

@ -299,9 +299,8 @@ XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
unsigned unsigned
XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond)const{ const SmallVectorImpl<MachineOperand> &Cond,
// FIXME there should probably be a DebugLoc argument here DebugLoc DL)const{
DebugLoc dl;
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) && assert((Cond.size() == 2 || Cond.size() == 0) &&
@ -310,11 +309,11 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
if (FBB == 0) { // One way branch. if (FBB == 0) { // One way branch.
if (Cond.empty()) { if (Cond.empty()) {
// Unconditional branch // Unconditional branch
BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB); BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
} else { } else {
// Conditional branch. // Conditional branch.
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
.addMBB(TBB); .addMBB(TBB);
} }
return 1; return 1;
@ -323,9 +322,9 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
// Two-way Conditional branch. // Two-way Conditional branch.
assert(Cond.size() == 2 && "Unexpected number of components!"); assert(Cond.size() == 2 && "Unexpected number of components!");
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
.addMBB(TBB); .addMBB(TBB);
BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB); BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
return 2; return 2;
} }

5
llvm/lib/Target/XCore/XCoreInstrInfo.h
View File

@ -58,8 +58,9 @@ public:
bool AllowModify) const; bool AllowModify) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;