forked from OSchip/llvm-project
LoadStoreVectorizer: Don't increase alignment with no align set
If no alignment was set on the load/stores, it would vectorize to the new type even though this increases the default alignment. llvm-svn: 274323
This commit is contained in:
Matt Arsenault
parent
370e8226c7
commit
0101ecade0
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@ -71,6 +71,22 @@ private:
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unsigned getPointerAddressSpace(Value *I);
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unsigned getAlignment(LoadInst *LI) const {
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unsigned Align = LI->getAlignment();
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if (Align != 0)
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return Align;
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return DL.getABITypeAlignment(LI->getType());
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}
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unsigned getAlignment(StoreInst *SI) const {
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unsigned Align = SI->getAlignment();
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if (Align != 0)
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return Align;
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return DL.getABITypeAlignment(SI->getValueOperand()->getType());
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}
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bool isConsecutiveAccess(Value *A, Value *B);
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/// Reorders the users of I after vectorization to ensure that I dominates its
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@ -648,7 +664,7 @@ bool Vectorizer::vectorizeStoreChain(ArrayRef<Value *> Chain) {
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);
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// Check alignment restrictions.
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unsigned Alignment = S0->getAlignment();
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unsigned Alignment = getAlignment(S0);
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// If the store is going to be misaligned, don't vectorize it.
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// TODO: Check TLI.allowsMisalignedMemoryAccess
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@ -776,7 +792,7 @@ bool Vectorizer::vectorizeLoadChain(ArrayRef<Value *> Chain) {
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}
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// Check alignment restrictions.
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unsigned Alignment = L0->getAlignment();
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unsigned Alignment = getAlignment(L0);
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// If the load is going to be misaligned, don't vectorize it.
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// TODO: Check TLI.allowsMisalignedMemoryAccess and remove TargetBaseAlign.
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@ -2,6 +2,8 @@
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-8 -load-store-vectorizer -S -o - %s | FileCheck -check-prefix=ELT8 -check-prefix=ALL %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-16 -load-store-vectorizer -S -o - %s | FileCheck -check-prefix=ELT16 -check-prefix=ALL %s
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32
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; ELT4: store i32
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; ELT4: store i32
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@ -31,7 +33,7 @@ define void @merge_private_store_4_vector_elts_loads_v4i8(i8* %out) #0 {
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%out.gep.2 = getelementptr i8, i8* %out, i32 2
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%out.gep.3 = getelementptr i8, i8* %out, i32 3
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store i8 9, i8* %out
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store i8 9, i8* %out, align 4
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store i8 1, i8* %out.gep.1
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store i8 23, i8* %out.gep.2
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store i8 19, i8* %out.gep.3
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@ -43,7 +45,7 @@ define void @merge_private_store_4_vector_elts_loads_v4i8(i8* %out) #0 {
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define void @merge_private_store_4_vector_elts_loads_v2i16(i16* %out) #0 {
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%out.gep.1 = getelementptr i16, i16* %out, i32 1
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store i16 9, i16* %out
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store i16 9, i16* %out, align 4
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store i16 12, i16* %out.gep.1
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ret void
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}
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@ -1,6 +1,8 @@
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -load-store-vectorizer -S -o - %s | FileCheck %s
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; Copy of test/CodeGen/AMDGPU/merge-stores.ll with some additions
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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; TODO: Vector element tests
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; TODO: Non-zero base offset for load and store combinations
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; TODO: Same base addrspacecasted
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@ -17,7 +19,8 @@ define void @merge_global_store_2_constants_i8(i8 addrspace(1)* %out) #0 {
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}
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; CHECK-LABEL: @merge_global_store_2_constants_i8_natural_align
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; CHECK: store <2 x i8> <i8 -56, i8 123>, <2 x i8> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store i8
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; CHECK: store i8
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define void @merge_global_store_2_constants_i8_natural_align(i8 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
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@ -47,7 +50,8 @@ define void @merge_global_store_2_constants_0_i16(i16 addrspace(1)* %out) #0 {
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}
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; CHECK-LABEL: @merge_global_store_2_constants_i16_natural_align
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; CHECK: store <2 x i16> <i16 456, i16 123>, <2 x i16> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store i16
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; CHECK: store i16
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define void @merge_global_store_2_constants_i16_natural_align(i16 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
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@ -57,7 +61,8 @@ define void @merge_global_store_2_constants_i16_natural_align(i16 addrspace(1)*
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}
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; CHECK-LABEL: @merge_global_store_2_constants_half_natural_align
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; CHECK: store <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store half
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; CHECK: store half
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define void @merge_global_store_2_constants_half_natural_align(half addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr half, half addrspace(1)* %out, i32 1
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@ -67,7 +72,7 @@ define void @merge_global_store_2_constants_half_natural_align(half addrspace(1)
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}
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; CHECK-LABEL: @merge_global_store_2_constants_i32
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; CHECK: store <2 x i32> <i32 456, i32 123>, <2 x i32> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store <2 x i32> <i32 456, i32 123>, <2 x i32> addrspace(1)* %{{[0-9]+}}, align 4
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define void @merge_global_store_2_constants_i32(i32 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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@ -77,7 +82,7 @@ define void @merge_global_store_2_constants_i32(i32 addrspace(1)* %out) #0 {
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}
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; CHECK-LABEL: @merge_global_store_2_constants_i32_f32
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; CHECK: store <2 x i32> <i32 456, i32 1065353216>, <2 x i32> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store <2 x i32> <i32 456, i32 1065353216>, <2 x i32> addrspace(1)* %{{[0-9]+}}, align 4
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define void @merge_global_store_2_constants_i32_f32(i32 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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%out.gep.1.bc = bitcast i32 addrspace(1)* %out.gep.1 to float addrspace(1)*
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@ -97,7 +102,7 @@ define void @merge_global_store_2_constants_f32_i32(float addrspace(1)* %out) #0
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}
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; CHECK-LABEL: @merge_global_store_4_constants_i32
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; CHECK: store <4 x i32> <i32 1234, i32 123, i32 456, i32 333>, <4 x i32> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store <4 x i32> <i32 1234, i32 123, i32 456, i32 333>, <4 x i32> addrspace(1)* %{{[0-9]+}}, align 4
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define void @merge_global_store_4_constants_i32(i32 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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%out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
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@ -126,7 +131,7 @@ define void @merge_global_store_4_constants_f32_order(float addrspace(1)* %out)
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; First store is out of order.
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; CHECK-LABEL: @merge_global_store_4_constants_f32
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; CHECK: store <4 x float> <float 8.000000e+00, float 1.000000e+00, float 2.000000e+00, float 4.000000e+00>, <4 x float> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store <4 x float> <float 8.000000e+00, float 1.000000e+00, float 2.000000e+00, float 4.000000e+00>, <4 x float> addrspace(1)* %{{[0-9]+}}, align 4
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define void @merge_global_store_4_constants_f32(float addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
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%out.gep.2 = getelementptr float, float addrspace(1)* %out, i32 2
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@ -140,7 +145,7 @@ define void @merge_global_store_4_constants_f32(float addrspace(1)* %out) #0 {
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}
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; CHECK-LABEL: @merge_global_store_4_constants_mixed_i32_f32
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; CHECK: store <4 x i32> <i32 1090519040, i32 11, i32 1073741824, i32 17>, <4 x i32> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store <4 x i32> <i32 1090519040, i32 11, i32 1073741824, i32 17>, <4 x i32> addrspace(1)* %{{[0-9]+}}, align 4
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define void @merge_global_store_4_constants_mixed_i32_f32(float addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
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%out.gep.2 = getelementptr float, float addrspace(1)* %out, i32 2
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@ -157,7 +162,7 @@ define void @merge_global_store_4_constants_mixed_i32_f32(float addrspace(1)* %o
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}
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; CHECK-LABEL: @merge_global_store_3_constants_i32
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; CHECK: store <3 x i32> <i32 1234, i32 123, i32 456>, <3 x i32> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store <3 x i32> <i32 1234, i32 123, i32 456>, <3 x i32> addrspace(1)* %{{[0-9]+}}, align 4
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define void @merge_global_store_3_constants_i32(i32 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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%out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
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@ -169,7 +174,7 @@ define void @merge_global_store_3_constants_i32(i32 addrspace(1)* %out) #0 {
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}
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; CHECK-LABEL: @merge_global_store_2_constants_i64
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; CHECK: store <2 x i64> <i64 456, i64 123>, <2 x i64> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store <2 x i64> <i64 456, i64 123>, <2 x i64> addrspace(1)* %{{[0-9]+}}, align 8
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define void @merge_global_store_2_constants_i64(i64 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i64, i64 addrspace(1)* %out, i64 1
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@ -179,8 +184,8 @@ define void @merge_global_store_2_constants_i64(i64 addrspace(1)* %out) #0 {
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}
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; CHECK-LABEL: @merge_global_store_4_constants_i64
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; CHECK: store <2 x i64> <i64 456, i64 333>, <2 x i64> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store <2 x i64> <i64 1234, i64 123>, <2 x i64> addrspace(1)* %{{[0-9]+$}}
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; CHECK: store <2 x i64> <i64 456, i64 333>, <2 x i64> addrspace(1)* %{{[0-9]+}}, align 8
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; CHECK: store <2 x i64> <i64 1234, i64 123>, <2 x i64> addrspace(1)* %{{[0-9]+}}, align 8
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define void @merge_global_store_4_constants_i64(i64 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i64, i64 addrspace(1)* %out, i64 1
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%out.gep.2 = getelementptr i64, i64 addrspace(1)* %out, i64 2
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@ -427,8 +432,14 @@ define void @merge_global_store_4_adjacent_loads_i8(i8 addrspace(1)* %out, i8 ad
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}
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; CHECK-LABEL: @merge_global_store_4_adjacent_loads_i8_natural_align
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; CHECK: load <4 x i8>
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; CHECK: store <4 x i8>
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; CHECK: load i8
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; CHECK: load i8
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; CHECK: load i8
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; CHECK: load i8
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; CHECK: store i8
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; CHECK: store i8
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; CHECK: store i8
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; CHECK: store i8
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define void @merge_global_store_4_adjacent_loads_i8_natural_align(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #0 {
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%out.gep.1 = getelementptr i8, i8 addrspace(1)* %out, i8 1
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%out.gep.2 = getelementptr i8, i8 addrspace(1)* %out, i8 2
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@ -481,7 +492,7 @@ define void @merge_local_store_2_constants_i8(i8 addrspace(3)* %out) #0 {
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}
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; CHECK-LABEL: @merge_local_store_2_constants_i32
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; CHECK: store <2 x i32> <i32 456, i32 123>, <2 x i32> addrspace(3)* %{{[0-9]+$}}
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; CHECK: store <2 x i32> <i32 456, i32 123>, <2 x i32> addrspace(3)* %{{[0-9]+}}, align 4
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define void @merge_local_store_2_constants_i32(i32 addrspace(3)* %out) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(3)* %out, i32 1
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@ -0,0 +1,30 @@
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; RUN: opt -mtriple=amdgcn-- -load-store-vectorizer -S -o - %s | FileCheck %s
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@lds = internal addrspace(3) global [512 x float] undef, align 4
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; The original load has an implicit alignment of 4, and should not
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; increase to an align 8 load.
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; CHECK-LABEL: @load_keep_base_alignment_missing_align(
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; CHECK: load <2 x float>, <2 x float> addrspace(3)* %{{[0-9]+}}, align 4
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define void @load_keep_base_alignment_missing_align(float addrspace(1)* %out) {
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%ptr0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 11
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%val0 = load float, float addrspace(3)* %ptr0
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%ptr1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 12
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%val1 = load float, float addrspace(3)* %ptr1
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%add = fadd float %val0, %val1
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store float %add, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: @store_keep_base_alignment_missing_align(
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; CHECK: store <2 x float> zeroinitializer, <2 x float> addrspace(3)* %{{[0-9]+}}, align 4
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define void @store_keep_base_alignment_missing_align() {
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%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 1
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%arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 2
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store float 0.0, float addrspace(3)* %arrayidx0
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store float 0.0, float addrspace(3)* %arrayidx1
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ret void
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}
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