forked from OSchip/llvm-project
parent
feae3dfe9f
commit
00f25d0915
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@ -20,7 +20,7 @@ TEST(ScheduleOptimizer, getPartialTilePrefixes) {
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isl_ctx *ctx = isl_ctx_alloc();
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{
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// Verify that for loop with 3 iterations starting at 0 that is
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// Verify that for a loop with 3 iterations starting at 0 that is
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// pre-vectorized (strip-mined with a factor of 2), we correctly identify
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// that only the first two iterations are full vector iterations.
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isl::map Schedule(
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@ -32,7 +32,7 @@ TEST(ScheduleOptimizer, getPartialTilePrefixes) {
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}
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{
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// Verify that for loop with 3 iterations starting at 1 that is
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// Verify that for a loop with 3 iterations starting at 1 that is
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// pre-vectorized (strip-mined with a factor of 2), we correctly identify
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// that only the last two iterations are full vector iterations.
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isl::map Schedule(
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@ -44,7 +44,7 @@ TEST(ScheduleOptimizer, getPartialTilePrefixes) {
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}
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{
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// Verify that for loop with 6 iterations starting at 1 that is
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// Verify that for a loop with 6 iterations starting at 1 that is
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// pre-vectorized (strip-mined with a factor of 2), we correctly identify
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// that all but the first and the last iteration are full vector iterations.
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isl::map Schedule(
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