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[LegalizeDAG] Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

This commit is contained in:
Simon Pilgrim 2020-09-14 11:09:15 +01:00
parent 687e1d7121
commit 00e5676cf6
1 changed files with 1 additions and 1 deletions
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2
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -2800,7 +2800,7 @@ SDValue SelectionDAGLegalize::ExpandPARITY(SDValue Op, const SDLoc &dl) {
Result = Op; Result = Op;
for (unsigned i = Log2_32_Ceil(Sz); i != 0;) { for (unsigned i = Log2_32_Ceil(Sz); i != 0;) {
SDValue Shift = DAG.getNode(ISD::SRL, dl, VT, Result, SDValue Shift = DAG.getNode(ISD::SRL, dl, VT, Result,
DAG.getConstant(1 << (--i), dl, ShVT)); DAG.getConstant(1ULL << (--i), dl, ShVT));
Result = DAG.getNode(ISD::XOR, dl, VT, Result, Shift); Result = DAG.getNode(ISD::XOR, dl, VT, Result, Shift);
} }
} }