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[RISCV] Add more i32 srem/sdiv with power of 2 constant tests. NFC 

Add a small power 2 srem test to match existing sdiv test. Add
larger power of 2 test to both.

The larger constant test shows materialization of a constant
for an AND in the RV64 code. We should be using W shift instructions
to match the RV32 code.
This commit is contained in:
Craig Topper 2021-07-17 23:48:35 -07:00
parent dac582ad3a
commit 00c1cc867f
2 changed files with 134 additions and 0 deletions
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42
llvm/test/CodeGen/RISCV/div.ll
View File

@ -730,6 +730,48 @@ define i32 @sdiv_pow2(i32 %a) nounwind {
ret i32 %1
}
define i32 @sdiv_pow2_2(i32 %a) nounwind {
; RV32I-LABEL: sdiv_pow2_2:
; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: ret
;
; RV32IM-LABEL: sdiv_pow2_2:
; RV32IM: # %bb.0:
; RV32IM-NEXT: srai a1, a0, 31
; RV32IM-NEXT: srli a1, a1, 16
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: srai a0, a0, 16
; RV32IM-NEXT: ret
;
; RV64I-LABEL: sdiv_pow2_2:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: srli a1, a1, 47
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 16
; RV64I-NEXT: ret
;
; RV64IM-LABEL: sdiv_pow2_2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a0
; RV64IM-NEXT: srli a1, a1, 47
; RV64IM-NEXT: lui a2, 16
; RV64IM-NEXT: addiw a2, a2, -1
; RV64IM-NEXT: and a1, a1, a2
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: sraiw a0, a0, 16
; RV64IM-NEXT: ret
%1 = sdiv i32 %a, 65536
ret i32 %1
}
define i32 @sdiv_constant_lhs(i32 %a) nounwind {
; RV32I-LABEL: sdiv_constant_lhs:
; RV32I: # %bb.0:

92
llvm/test/CodeGen/RISCV/rem.ll
View File

@ -117,6 +117,98 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
ret i32 %1
}
define i32 @srem_pow2(i32 %a) nounwind {
; RV32I-LABEL: srem_pow2:
; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: add a1, a0, a1
; RV32I-NEXT: andi a1, a1, -8
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IM-LABEL: srem_pow2:
; RV32IM: # %bb.0:
; RV32IM-NEXT: srai a1, a0, 31
; RV32IM-NEXT: srli a1, a1, 29
; RV32IM-NEXT: add a1, a0, a1
; RV32IM-NEXT: andi a1, a1, -8
; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: srem_pow2:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: srli a1, a1, 60
; RV64I-NEXT: andi a1, a1, 7
; RV64I-NEXT: add a1, a0, a1
; RV64I-NEXT: andi a1, a1, -8
; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: srem_pow2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a0
; RV64IM-NEXT: srli a1, a1, 60
; RV64IM-NEXT: andi a1, a1, 7
; RV64IM-NEXT: add a1, a0, a1
; RV64IM-NEXT: andi a1, a1, -8
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = srem i32 %a, 8
ret i32 %1
}
define i32 @srem_pow2_2(i32 %a) nounwind {
; RV32I-LABEL: srem_pow2_2:
; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: add a1, a0, a1
; RV32I-NEXT: lui a2, 1048560
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IM-LABEL: srem_pow2_2:
; RV32IM: # %bb.0:
; RV32IM-NEXT: srai a1, a0, 31
; RV32IM-NEXT: srli a1, a1, 16
; RV32IM-NEXT: add a1, a0, a1
; RV32IM-NEXT: lui a2, 1048560
; RV32IM-NEXT: and a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: srem_pow2_2:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: srli a1, a1, 47
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: add a1, a0, a1
; RV64I-NEXT: lui a2, 1048560
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: srem_pow2_2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a0
; RV64IM-NEXT: srli a1, a1, 47
; RV64IM-NEXT: lui a2, 16
; RV64IM-NEXT: addiw a2, a2, -1
; RV64IM-NEXT: and a1, a1, a2
; RV64IM-NEXT: add a1, a0, a1
; RV64IM-NEXT: lui a2, 1048560
; RV64IM-NEXT: and a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = srem i32 %a, 65536
ret i32 %1
}
define i32 @srem_constant_lhs(i32 %a) nounwind {
; RV32I-LABEL: srem_constant_lhs:
; RV32I: # %bb.0: