maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[PowerPC] [MLICM] Enable hoisting of caller preserved registers on AIX 

On ppc64 linux , MachineLICM will hoist caller preserved registers, including TOC loads of the global variable address, out of loops. This is to enable this on AIX for both ppc64 and ppc32.

Differential Revision: https://reviews.llvm.org/D99076
This commit is contained in:
Shimin Cui 2021-03-31 12:36:49 -04:00
parent 50b8634a99
commit 00c0c8c87d
2 changed files with 36 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -403,22 +403,20 @@ bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg,
assert(Register::isPhysicalRegister(PhysReg)); assert(Register::isPhysicalRegister(PhysReg));
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
const MachineFrameInfo &MFI = MF.getFrameInfo(); const MachineFrameInfo &MFI = MF.getFrameInfo();
if (!TM.isPPC64())
return false;
if (!Subtarget.isSVR4ABI()) if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI())
return false; return false;
if (PhysReg == PPC::X2) if (PhysReg == Subtarget.getTOCPointerRegister())
// X2 is guaranteed to be preserved within a function if it is reserved. // X2/R2 is guaranteed to be preserved within a function if it is reserved.
// The reason it's reserved is that it's the TOC pointer (and the function // The reason it's reserved is that it's the TOC pointer (and the function
// uses the TOC). In functions where it isn't reserved (i.e. leaf functions // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
// with no TOC access), we can't claim that it is preserved. // with no TOC access), we can't claim that it is preserved.
return (getReservedRegs(MF).test(PPC::X2)); return (getReservedRegs(MF).test(PhysReg));
if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects() if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() &&
&& !MFI.hasOpaqueSPAdjustment()) !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
// The value of the stack pointer does not change within a function after // The value of the stack pointer does not change within a function after
// the prologue and before the epilogue if there are no dynamic allocations // the prologue and before the epilogue if there are no dynamic allocations
// and no inline asm which clobbers X1. // and no inline asm which clobbers X1/R1.
return true; return true;
return false; return false;
} }

46
llvm/test/CodeGen/PowerPC/licm-tocReg.ll
View File

@ -1,4 +1,6 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck -check-prefixes=CHECK,CHECKLX %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECK,CHECKAIX %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECK,CHECKAIX32 %s
; The instructions ADDIStocHA8/LDtocL are used to calculate the address of ; The instructions ADDIStocHA8/LDtocL are used to calculate the address of
; globals. The ones that are in bb.3.if.end could not be hoisted by Machine ; globals. The ones that are in bb.3.if.end could not be hoisted by Machine
@ -65,22 +67,32 @@ define signext i32 @test(i32 (i32)* nocapture %FP) local_unnamed_addr #0 {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK: addis 4, 2, .LC0@toc@ha ; CHECKLX: addis 4, 2, .LC0@toc@ha
; CHECK-NEXT: addis 5, 2, .LC1@toc@ha ; CHECKLX-NEXT: addis 5, 2, .LC1@toc@ha
; CHECK-NEXT: mr 12, 3 ; CHECKLX-NEXT: mr 12, 3
; CHECK-NEXT: ld 4, .LC0@toc@l(4) ; CHECKLX-NEXT: ld 4, .LC0@toc@l(4)
; CHECK-NEXT: ld 5, .LC1@toc@l(5) ; CHECKLX-NEXT: ld 5, .LC1@toc@l(5)
; CHECK-NEXT: lwz 6, 0(4) ; CHECKLX-NEXT: lwz 6, 0(4)
; CHECK-NEXT: lwz 7, 0(5) ; CHECKLX-NEXT: lwz 7, 0(5)
; CHECK-NEXT: cmpw 6, 7 ; CHECKLX-NEXT: cmpw 6, 7
; CHECK-NEXT: lwz 6, 0(4) ; CHECKLX-NEXT: lwz 6, 0(4)
; CHECK-NEXT: bgt 0, .LBB0_2 ; CHECKLX-NEXT: bgt 0, .LBB0_2
; CHECK-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha ; CHECKLX-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha
; CHECK-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha ; CHECKLX-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha
; CHECK-NEXT: .p2align 5 ; CHECKLX-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_1: # %if.end ; CHECKLX-NEXT: .LBB0_1: # %if.end
; CHECK-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha ; CHECKLX-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha
; CHECK-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha ; CHECKLX-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha
; CHECKAIX: ld 5, L..C0(2)
; CHECKAIX-NEXT: ld 6, L..C1(2)
; CHECKAIX-NEXT: L..BB0_1: # %if.end
; CHECKAIX-NOT: ld {{[0-9]+}}, L..C0(2)
; CHECKAIX-NOT: ld {{[0-9]+}}, L..C1(2)
; CHECKAIX32: lwz 5, L..C0(2)
; CHECKAIX32-NEXT: lwz 6, L..C1(2)
; CHECKAIX32-NEXT: L..BB0_1: # %if.end
; CHECKAIX32-NOT: lwz 5, L..C0(2)
; CHECKAIX32-NOT: lwz 6, L..C1(2)
; CHECK: blr ; CHECK: blr
entry: entry:
%0 = load volatile i32, i32* @ga, align 4 %0 = load volatile i32, i32* @ga, align 4