forked from OSchip/llvm-project
[PowerPC] Don't generate mfocrf on the e500mc
The e500mc does not actually support the mfocrf instruction; update the processor definitions to reflect that fact. Patch by Tom Rix (with some test-case cleanup by me). llvm-svn: 254064
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@ -312,7 +312,7 @@ def : ProcessorModel<"g5", G5Model,
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Feature64Bit /*, Feature64BitRegs */,
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Feature64Bit /*, Feature64BitRegs */,
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FeatureMFTB, DeprecatedDST]>;
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FeatureMFTB, DeprecatedDST]>;
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def : ProcessorModel<"e500mc", PPCE500mcModel,
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def : ProcessorModel<"e500mc", PPCE500mcModel,
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[DirectiveE500mc, FeatureMFOCRF,
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[DirectiveE500mc,
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FeatureSTFIWX, FeatureICBT, FeatureBookE,
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FeatureSTFIWX, FeatureICBT, FeatureBookE,
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FeatureISEL, FeatureMFTB]>;
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FeatureISEL, FeatureMFTB]>;
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def : ProcessorModel<"e5500", PPCE5500Model,
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def : ProcessorModel<"e5500", PPCE5500Model,
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@ -0,0 +1,30 @@
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; RUN: llc -O0 -mcpu=e500mc < %s | FileCheck %s
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; Check if e500 generates code with mfocrf insn.
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target datalayout = "E-m:e-p:32:32-i64:64-n32"
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target triple = "powerpc-unknown-linux-gnu"
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define internal i32 @func_49(i64 %p_50, i16 zeroext %p_51, i8* %p_52, i32 %p_53) {
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; CHECK-LABEL: @func_49
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; CHECK-NOT: mfocrf
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%1 = load i64, i64* undef, align 8
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%2 = load i64, i64* undef, align 8
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%3 = icmp sge i32 undef, undef
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%4 = zext i1 %3 to i32
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%5 = sext i32 %4 to i64
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%6 = icmp slt i64 %2, %5
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%7 = zext i1 %6 to i32
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%8 = call i64 @safe_sub_func_int64_t_s_s(i64 -6372137293439783564, i64 undef)
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%9 = icmp slt i32 %7, undef
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%10 = zext i1 %9 to i32
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%11 = sext i32 %10 to i64
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%12 = icmp sle i64 %1, %11
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%13 = zext i1 %12 to i32
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%14 = call i32 @safe_add_func_int32_t_s_s(i32 undef, i32 %13)
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ret i32 undef
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}
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declare i32 @safe_add_func_int32_t_s_s(i32, i32)
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declare i64 @safe_sub_func_int64_t_s_s(i64, i64)
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