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[PowerPC] Don't generate mfocrf on the e500mc 

The e500mc does not actually support the mfocrf instruction; update the
processor definitions to reflect that fact.

Patch by Tom Rix (with some test-case cleanup by me).

llvm-svn: 254064
This commit is contained in:
Hal Finkel 2015-11-25 10:14:31 +00:00
parent c99b04983b
commit 005f840959
2 changed files with 31 additions and 1 deletions
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2
llvm/lib/Target/PowerPC/PPC.td
View File

@ -312,7 +312,7 @@ def : ProcessorModel<"g5", G5Model,
Feature64Bit /*, Feature64BitRegs */,
FeatureMFTB, DeprecatedDST]>;
def : ProcessorModel<"e500mc", PPCE500mcModel,
[DirectiveE500mc, FeatureMFOCRF,
[DirectiveE500mc,
FeatureSTFIWX, FeatureICBT, FeatureBookE,
FeatureISEL, FeatureMFTB]>;
def : ProcessorModel<"e5500", PPCE5500Model,

30
llvm/test/CodeGen/PowerPC/e500-1.ll Normal file
View File

@ -0,0 +1,30 @@
; RUN: llc -O0 -mcpu=e500mc < %s | FileCheck %s
; Check if e500 generates code with mfocrf insn.
target datalayout = "E-m:e-p:32:32-i64:64-n32"
target triple = "powerpc-unknown-linux-gnu"
define internal i32 @func_49(i64 %p_50, i16 zeroext %p_51, i8* %p_52, i32 %p_53) {
; CHECK-LABEL: @func_49
; CHECK-NOT: mfocrf
%1 = load i64, i64* undef, align 8
%2 = load i64, i64* undef, align 8
%3 = icmp sge i32 undef, undef
%4 = zext i1 %3 to i32
%5 = sext i32 %4 to i64
%6 = icmp slt i64 %2, %5
%7 = zext i1 %6 to i32
%8 = call i64 @safe_sub_func_int64_t_s_s(i64 -6372137293439783564, i64 undef)
%9 = icmp slt i32 %7, undef
%10 = zext i1 %9 to i32
%11 = sext i32 %10 to i64
%12 = icmp sle i64 %1, %11
%13 = zext i1 %12 to i32
%14 = call i32 @safe_add_func_int32_t_s_s(i32 undef, i32 %13)
ret i32 undef
}
declare i32 @safe_add_func_int32_t_s_s(i32, i32)
declare i64 @safe_sub_func_int64_t_s_s(i64, i64)