forked from OSchip/llvm-project
[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6
Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 llvm-svn: 211019
This commit is contained in:
Daniel Sanders
parent
6a803f6162
commit
00463119a5
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@ -91,6 +91,10 @@ def OPCODE6_LL : OPCODE6<0b110110>;
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def OPCODE6_LLD : OPCODE6<0b110111>;
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def OPCODE6_SC : OPCODE6<0b100110>;
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def OPCODE6_SCD : OPCODE6<0b100111>;
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def OPCODE6_CLO : OPCODE6<0b010001>;
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def OPCODE6_CLZ : OPCODE6<0b010000>;
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def OPCODE6_DCLO : OPCODE6<0b010011>;
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def OPCODE6_DCLZ : OPCODE6<0b010010>;
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class FIELD_FMT<bits<5> Val> {
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bits<5> Value = Val;
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@ -293,6 +297,20 @@ class SPECIAL3_MEM_FM<OPCODE6 Operation> : MipsR6Inst {
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let Inst{5-0} = Operation.Value;
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}
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class SPECIAL_2R_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0b00000;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0b00001;
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let Inst{5-0} = Operation.Value;
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}
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class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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@ -15,7 +15,6 @@ include "Mips32r6InstrFormats.td"
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// Notes about removals/changes from MIPS32r6:
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// Unclear: ssnop
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// Reencoded: clo, clz
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// Reencoded: jr -> jalr
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// Reencoded: jr.hb -> jalr.hb
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// Reencoded: sdbbp
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@ -160,6 +159,9 @@ class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
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class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
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class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
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class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
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class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
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class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
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RegisterOperand FGROpnd,
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SDPatternOperator Op = null_frag> {
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@ -586,6 +588,25 @@ class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
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class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
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}
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class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
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CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
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list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
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}
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class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
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CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
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list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
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}
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class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>;
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class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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@ -628,6 +649,8 @@ def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
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def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
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def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
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def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
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def CLO_R6 : CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
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def CLZ_R6 : CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
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defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
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defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
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def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
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@ -225,8 +225,8 @@ def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
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}
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/// Count Leading
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def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64;
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def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64;
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def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
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def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
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/// Double Word Swap Bytes/HalfWords
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def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
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@ -25,6 +25,8 @@ class DAUI_ENC : DAUI_FM;
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class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
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class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
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class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
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class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
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class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
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class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
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class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
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class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
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@ -55,6 +57,8 @@ class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
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class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
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class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>;
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class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
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class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
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class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
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class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
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class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
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class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
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@ -80,6 +84,8 @@ def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
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def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
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def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
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def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
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def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
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def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
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def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
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def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
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// def DLSA; // See MSA
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@ -240,6 +240,9 @@ class ISA_MIPS32R2_NOT_32R6_64R6 {
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list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
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}
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class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
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class ISA_MIPS64_NOT_64R6 {
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list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
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}
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class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
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class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
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class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
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@ -1277,8 +1280,10 @@ def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
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SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
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/// Count Leading
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def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
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def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
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def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
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ISA_MIPS32_NOT_32R6_64R6;
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def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
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ISA_MIPS32_NOT_32R6_64R6;
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/// Word Swap Bytes Within Halfwords
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def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
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@ -158,7 +158,10 @@ public:
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bool hasMips3() const { return MipsArchVersion >= Mips3; }
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bool hasMips4_32() const { return HasMips4_32; }
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bool hasMips4_32r2() const { return HasMips4_32r2; }
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bool hasMips32() const { return MipsArchVersion >= Mips32; }
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bool hasMips32() const {
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return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
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MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
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}
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bool hasMips32r2() const {
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return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
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MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
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@ -0,0 +1,90 @@
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; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
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; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6 -check-prefix=MIPS32-GT-R1 %s
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; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
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; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
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; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
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; Prefixes:
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; ALL - All
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; MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
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; MIPS64-GT-R1 - MIPS64r1 and above
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define i32 @ctlz_i32(i32 %X) nounwind readnone {
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entry:
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; ALL-LABEL: ctlz_i32:
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; MIPS4-NOT: clz
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; MIPS32-GT-R1: clz $2, $4
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; MIPS64-GT-R1: clz $2, $4
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%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
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ret i32 %tmp1
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}
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declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
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define i32 @ctlo_i32(i32 %X) nounwind readnone {
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entry:
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; ALL-LABEL: ctlo_i32:
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; MIPS4-NOT: clo
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; MIPS32-GT-R1: clo $2, $4
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; MIPS64-GT-R1: clo $2, $4
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%neg = xor i32 %X, -1
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%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
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ret i32 %tmp1
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}
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define i64 @ctlz_i64(i64 %X) nounwind readnone {
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entry:
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; ALL-LABEL: ctlz_i64:
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; MIPS4-NOT: dclz
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; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4
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; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5
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; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
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; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5
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; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R2]], $5
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; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R1]], $5
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; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]]
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; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
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; MIPS64-GT-R1: dclz $2, $4
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
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ret i64 %tmp1
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}
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declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
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define i64 @ctlo_i64(i64 %X) nounwind readnone {
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entry:
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; ALL-LABEL: ctlo_i64:
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; MIPS4-NOT: dclo
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; MIPS32-GT-R1-DAG: clo $[[R0:[0-9]+]], $4
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; MIPS32-GT-R1-DAG: clo $[[R1:[0-9]+]], $5
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; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
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; MIPS32-GT-R1-DAG: addiu $[[R3:[0-9]+]], $zero, -1
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; MIPS32-GT-R1-DAG: xor $[[R4:[0-9]+]], $5, $[[R3]]
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; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $[[R4]]
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; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]]
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; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]]
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; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]]
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; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
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; MIPS64-GT-R1: dclo $2, $4
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%neg = xor i64 %X, -1
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
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ret i64 %tmp1
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}
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@ -1,24 +0,0 @@
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; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS4 %s
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS64 %s
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define i64 @t1(i64 %X) nounwind readnone {
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entry:
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; CHECK-LABEL: t1:
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; MIPS4-NOT: dclz
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; MIPS64: dclz
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
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ret i64 %tmp1
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}
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declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
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define i64 @t3(i64 %X) nounwind readnone {
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entry:
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; CHECK-LABEL: t3:
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; MIPS4-NOT: dclo
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; MIPS64: dclo
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%neg = xor i64 %X, -1
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
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ret i64 %tmp1
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}
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@ -1,5 +1,7 @@
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; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
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; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 %s
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; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 -check-prefix=ACCMULDIV %s
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; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
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; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
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; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=GPRMULDIV %s
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@gll0 = common global i64 0, align 8
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@gll1 = common global i64 0, align 8
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@ -87,7 +89,10 @@ entry:
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define i64 @f12(i64 %a, i64 %b) nounwind readnone {
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entry:
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; ALL-LABEL: f12:
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; ALL: mult ${{[45]}}, ${{[45]}}
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; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
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; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}
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%mul = mul nsw i64 %b, %a
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ret i64 %mul
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}
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@ -95,7 +100,10 @@ entry:
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define i64 @f13(i64 %a, i64 %b) nounwind readnone {
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entry:
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; ALL-LABEL: f13:
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; ALL: mult ${{[45]}}, ${{[45]}}
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; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
|
||||
; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}
|
||||
|
||||
%mul = mul i64 %b, %a
|
||||
ret i64 %mul
|
||||
}
|
||||
|
|
@ -107,9 +115,14 @@ entry:
|
|||
; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
|
||||
; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
|
||||
; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
|
||||
; ALL: ddiv $zero, $[[T0]], $[[T1]]
|
||||
; ALL: teq $[[T1]], $zero, 7
|
||||
; ALL: mflo $2
|
||||
|
||||
; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]]
|
||||
; ACCMULDIV: teq $[[T1]], $zero, 7
|
||||
; ACCMULDIV: mflo $2
|
||||
|
||||
; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]]
|
||||
; GPRMULDIV: teq $[[T1]], $zero, 7
|
||||
|
||||
%0 = load i64* @gll0, align 8
|
||||
%1 = load i64* @gll1, align 8
|
||||
%div = sdiv i64 %0, %1
|
||||
|
|
@ -123,9 +136,14 @@ entry:
|
|||
; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
|
||||
; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
|
||||
; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
|
||||
; ALL: ddivu $zero, $[[T0]], $[[T1]]
|
||||
; ALL: teq $[[T1]], $zero, 7
|
||||
; ALL: mflo $2
|
||||
|
||||
; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]
|
||||
; ACCMULDIV: teq $[[T1]], $zero, 7
|
||||
; ACCMULDIV: mflo $2
|
||||
|
||||
; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]
|
||||
; GPRMULDIV: teq $[[T1]], $zero, 7
|
||||
|
||||
%0 = load i64* @gll0, align 8
|
||||
%1 = load i64* @gll1, align 8
|
||||
%div = udiv i64 %0, %1
|
||||
|
|
@ -135,9 +153,14 @@ entry:
|
|||
define i64 @f16(i64 %a, i64 %b) nounwind readnone {
|
||||
entry:
|
||||
; ALL-LABEL: f16:
|
||||
; ALL: ddiv $zero, $4, $5
|
||||
; ALL: teq $5, $zero, 7
|
||||
; ALL: mfhi $2
|
||||
|
||||
; ACCMULDIV: ddiv $zero, $4, $5
|
||||
; ACCMULDIV: teq $5, $zero, 7
|
||||
; ACCMULDIV: mfhi $2
|
||||
|
||||
; GPRMULDIV: dmod $2, $4, $5
|
||||
; GPRMULDIV: teq $5, $zero, 7
|
||||
|
||||
%rem = srem i64 %a, %b
|
||||
ret i64 %rem
|
||||
}
|
||||
|
|
@ -145,9 +168,14 @@ entry:
|
|||
define i64 @f17(i64 %a, i64 %b) nounwind readnone {
|
||||
entry:
|
||||
; ALL-LABEL: f17:
|
||||
; ALL: ddivu $zero, $4, $5
|
||||
; ALL: teq $5, $zero, 7
|
||||
; ALL: mfhi $2
|
||||
|
||||
; ACCMULDIV: ddivu $zero, $4, $5
|
||||
; ACCMULDIV: teq $5, $zero, 7
|
||||
; ACCMULDIV: mfhi $2
|
||||
|
||||
; GPRMULDIV: dmodu $2, $4, $5
|
||||
; GPRMULDIV: teq $5, $zero, 7
|
||||
|
||||
%rem = urem i64 %a, %b
|
||||
ret i64 %rem
|
||||
}
|
||||
|
|
@ -161,7 +189,8 @@ entry:
|
|||
; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
|
||||
; MIPS4-NOT: dclz
|
||||
|
||||
; MIPS64: dclz $2, $4
|
||||
; HAS-DCLO: dclz $2, $4
|
||||
|
||||
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
|
||||
ret i64 %tmp1
|
||||
}
|
||||
|
|
@ -173,7 +202,8 @@ entry:
|
|||
; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
|
||||
; MIPS4-NOT: dclo
|
||||
|
||||
; MIPS64: dclo $2, $4
|
||||
; HAS-DCLO: dclo $2, $4
|
||||
|
||||
%neg = xor i64 %X, -1
|
||||
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
|
||||
ret i64 %tmp1
|
||||
|
|
|
|||
|
|
@ -121,3 +121,5 @@
|
|||
0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
|
||||
0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18)
|
||||
0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19)
|
||||
0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
|
||||
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
|
||||
|
|
|
|||
|
|
@ -137,3 +137,7 @@
|
|||
0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra)
|
||||
0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19)
|
||||
0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp)
|
||||
0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
|
||||
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
|
||||
0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6
|
||||
0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
|
||||
|
|
|
|||
|
|
@ -29,8 +29,8 @@
|
|||
ceil.w.d $f11,$f25
|
||||
ceil.w.s $f6,$f20
|
||||
cfc1 $s1,$21
|
||||
clo $11,$a1
|
||||
clz $sp,$gp
|
||||
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
|
||||
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
|
||||
ctc1 $a2,$26
|
||||
cvt.d.s $f22,$f28
|
||||
cvt.d.w $f26,$f11
|
||||
|
|
|
|||
|
|
@ -29,8 +29,8 @@
|
|||
ceil.w.d $f11,$f25
|
||||
ceil.w.s $f6,$f20
|
||||
cfc1 $s1,$21
|
||||
clo $11,$a1
|
||||
clz $sp,$gp
|
||||
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
|
||||
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
|
||||
ctc1 $a2,$26
|
||||
cvt.d.s $f22,$f28
|
||||
cvt.d.w $f26,$f11
|
||||
|
|
|
|||
|
|
@ -138,3 +138,5 @@
|
|||
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
|
||||
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
|
||||
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
|
||||
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
|
||||
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
|
||||
|
|
|
|||
|
|
@ -31,8 +31,8 @@
|
|||
ceil.w.d $f11,$f25
|
||||
ceil.w.s $f6,$f20
|
||||
cfc1 $s1,$21
|
||||
clo $11,$a1
|
||||
clz $sp,$gp
|
||||
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
|
||||
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
|
||||
ctc1 $a2,$26
|
||||
cvt.d.l $f4,$f16
|
||||
cvt.d.s $f22,$f28
|
||||
|
|
@ -52,8 +52,8 @@
|
|||
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
|
||||
daddiu $k0,$s6,-4586
|
||||
daddu $s3,$at,$ra
|
||||
dclo $s2,$a2
|
||||
dclz $s0,$25
|
||||
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
|
||||
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
||||
deret
|
||||
ddiv $zero,$k0,$s3
|
||||
ddivu $zero,$s0,$s1
|
||||
|
|
|
|||
|
|
@ -31,8 +31,8 @@
|
|||
ceil.w.d $f11,$f25
|
||||
ceil.w.s $f6,$f20
|
||||
cfc1 $s1,$21
|
||||
clo $11,$a1
|
||||
clz $sp,$gp
|
||||
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
|
||||
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
|
||||
ctc1 $a2,$26
|
||||
cvt.d.l $f4,$f16
|
||||
cvt.d.s $f22,$f28
|
||||
|
|
@ -52,8 +52,8 @@
|
|||
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
|
||||
daddiu $k0,$s6,-4586
|
||||
daddu $s3,$at,$ra
|
||||
dclo $s2,$a2
|
||||
dclz $s0,$25
|
||||
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
|
||||
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
||||
deret
|
||||
di $s8
|
||||
ddiv $zero,$k0,$s3
|
||||
|
|
|
|||
|
|
@ -154,3 +154,7 @@
|
|||
lld $zero,112($ra) # CHECK: lld $zero, 112($ra) # encoding: [0x7f,0xe0,0x38,0x37]
|
||||
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
|
||||
scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7]
|
||||
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
|
||||
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
|
||||
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53]
|
||||
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
|
||||
|
|
|
|||
Loading…
Reference in New Issue