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ARM NEON two-operand aliases for VSHL(immediate). 

llvm-svn: 146125
This commit is contained in:
Jim Grosbach 2011-12-08 01:30:04 +00:00
parent 14e024dff7
commit 00326406d4
4 changed files with 55 additions and 0 deletions
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8
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -584,6 +584,14 @@ def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
let ParserMatchClass = Imm0_32AsmOperand;
}
/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm < 64;
}]> {
let ParserMatchClass = Imm0_63AsmOperand;
}
/// imm0_255 predicate - Immediate in the range [0,255].
def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {

19
llvm/lib/Target/ARM/ARMInstrNEON.td
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@ -5402,6 +5402,25 @@ def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane",
(VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
VectorIndex32:$lane, pred:$p)>;
// VSHL (immediate) two-operand aliases.
def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
(VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>;
def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
(VSHLiv4i16 DPR:$Vdn, DPR:$Vdn, imm0_15:$imm, pred:$p)>;
def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
(VSHLiv2i32 DPR:$Vdn, DPR:$Vdn, imm0_31:$imm, pred:$p)>;
def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
(VSHLiv1i64 DPR:$Vdn, DPR:$Vdn, imm0_63:$imm, pred:$p)>;
def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
(VSHLiv16i8 QPR:$Vdn, QPR:$Vdn, imm0_7:$imm, pred:$p)>;
def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
(VSHLiv8i16 QPR:$Vdn, QPR:$Vdn, imm0_15:$imm, pred:$p)>;
def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
(VSHLiv4i32 QPR:$Vdn, QPR:$Vdn, imm0_31:$imm, pred:$p)>;
def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
(VSHLiv2i64 QPR:$Vdn, QPR:$Vdn, imm0_63:$imm, pred:$p)>;
// VSHL (register) two-operand aliases.
def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
(VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;

8
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -611,6 +611,14 @@ public:
int64_t Value = CE->getValue();
return Value >= 0 && Value < 32;
}
bool isImm0_63() const {
if (Kind != k_Immediate)
return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false;
int64_t Value = CE->getValue();
return Value >= 0 && Value < 64;
}
bool isImm8() const {
if (Kind != k_Immediate)
return false;

20
llvm/test/MC/ARM/neon-shift-encoding.s
View File

@ -276,3 +276,23 @@ _foo:
@ CHECK: vshl.u16 d4, d4, d5 @ encoding: [0x04,0x44,0x15,0xf3]
@ CHECK: vshl.u32 d4, d4, d5 @ encoding: [0x04,0x44,0x25,0xf3]
@ CHECK: vshl.u64 d4, d4, d5 @ encoding: [0x04,0x44,0x35,0xf3]
vshl.s8 q4, #2
vshl.s16 q4, #14
vshl.s32 q4, #27
vshl.s64 q4, #35
vshl.s8 d4, #6
vshl.u16 d4, #10
vshl.s32 d4, #17
vshl.u64 d4, #43
@ CHECK: vshl.i8 q4, q4, #2 @ encoding: [0x58,0x85,0x8a,0xf2]
@ CHECK: vshl.i16 q4, q4, #14 @ encoding: [0x58,0x85,0x9e,0xf2]
@ CHECK: vshl.i32 q4, q4, #27 @ encoding: [0x58,0x85,0xbb,0xf2]
@ CHECK: vshl.i64 q4, q4, #35 @ encoding: [0xd8,0x85,0xa3,0xf2]
@ CHECK: vshl.i8 d4, d4, #6 @ encoding: [0x14,0x45,0x8e,0xf2]
@ CHECK: vshl.i16 d4, d4, #10 @ encoding: [0x14,0x45,0x9a,0xf2]
@ CHECK: vshl.i32 d4, d4, #17 @ encoding: [0x14,0x45,0xb1,0xf2]
@ CHECK: vshl.i64 d4, d4, #43 @ encoding: [0x94,0x45,0xab,0xf2]