forked from OSchip/llvm-project
* Eliminate global base register, r2 is used for that on AIX/PowerPC
* Fix bug from 32-bit PowerPC days of 2-register long split llvm-svn: 15916
This commit is contained in:
Misha Brukman
parent
6c4a085286
commit
0010ea3042
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@ -93,11 +93,6 @@ namespace {
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// FrameIndex for the alloca.
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std::map<AllocaInst*, unsigned> AllocaMap;
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// A Reg to hold the base address used for global loads and stores, and a
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// flag to set whether or not we need to emit it for this function.
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unsigned GlobalBaseReg;
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bool GlobalBaseInitialized;
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ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC64TargetMachine&>(tm)),
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F(0), BB(0) {}
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@ -158,9 +153,6 @@ namespace {
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BB = &F->front();
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseInitialized = false;
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// Copy incoming arguments off of the stack...
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LoadArgumentsToVirtualRegs(Fn);
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@ -356,13 +348,6 @@ namespace {
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Value *Cond, Value *TrueVal, Value *FalseVal,
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unsigned DestReg);
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/// copyGlobalBaseToRegister - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned R);
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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@ -507,27 +492,6 @@ unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
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}
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/// copyGlobalBaseToRegister - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned R) {
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if (!GlobalBaseInitialized) {
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = F->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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GlobalBaseReg = makeAnotherReg(Type::IntTy);
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BuildMI(FirstMBB, MBBI, PPC::IMPLICIT_DEF, 0, PPC::LR);
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BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, GlobalBaseReg);
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GlobalBaseInitialized = true;
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}
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// Emit our copy of GlobalBaseReg to the destination register in the
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// current MBB
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BuildMI(*MBB, IP, PPC::OR, 2, R).addReg(GlobalBaseReg)
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.addReg(GlobalBaseReg);
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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@ -561,6 +525,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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unsigned CPI = CP->getConstantPoolIndex(C);
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BuildMI(*MBB, IP, PPC::LD, 1, R)
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.addReg(PPC::R2).addConstantPoolIndex(CPI);
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return;
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}
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assert(Class <= cInt && "Type not handled yet!");
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@ -907,7 +872,7 @@ static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
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/// emitUCOM - emits an unordered FP compare.
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void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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unsigned LHS, unsigned RHS) {
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unsigned LHS, unsigned RHS) {
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BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
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}
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@ -1406,7 +1371,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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// pass the float in an int. Otherwise, put it on the stack.
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if (isVarArg) {
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BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
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.addReg(PPC::R1);
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.addReg(PPC::R1);
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if (GPR_remaining > 0) {
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BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx])
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.addSImm(ArgOffset).addReg(ArgReg);
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@ -1794,10 +1759,8 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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// registers and emit the appropriate opcode.
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unsigned Op0r = getReg(Op0, MBB, IP);
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unsigned Op1r = getReg(Op1, MBB, IP);
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unsigned Opcode = OpcodeTab[OperatorClass];
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
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return;
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}
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// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
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@ -2114,7 +2077,7 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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}
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}
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} else { // The shift amount is non-constant.
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unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
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unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
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if (isLeftShift) {
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BuildMI(*MBB, IP, PPC::SLW, 2, DestReg).addReg(SrcReg)
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@ -2522,7 +2485,7 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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// PhiMBB:
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// DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
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BB = PhiMBB;
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BuildMI(BB, PPC::PHI, 2, DestReg).addReg(IntTmp).addMBB(OldMBB)
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BuildMI(BB, PPC::PHI, 4, DestReg).addReg(IntTmp).addMBB(OldMBB)
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.addReg(XorReg).addMBB(XorMBB);
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}
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}
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@ -2674,10 +2637,8 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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// sbyte -1 -> ubyte 0xFFFFFFFF
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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break;
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case cLong:
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++SrcReg;
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// Fall through
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case cInt:
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case cLong:
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if (DestClass == cInt)
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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else
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