maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/clang/test/Preprocessor/predefined-arch-macros.c

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

3729 lines
154 KiB
C
Raw Normal View History

Fix lit test failure due to 0b81d9 These lit tests now requires amdgpu-registered-target since they use clang driver and clang driver passes an LLVM option which is available only if amdgpu target is registered. Change-Id: I2df31967409f1627fc6d342d1ab5cc8aa17c9c0c
2020-12-08 08:48:59 +08:00
// REQUIRES: amdgpu-registered-target
Add a little banner to this test. This lets my scripts more easily automate the process of updating and generating these tests. If anyone is really interested, I can check my scripts for generating this test in, but its a horrible pile of shell... Not sure its really worth it. llvm-svn: 140691
2011-09-28 18:17:41 +08:00
// Begin X86/GCC/Linux tests ----------------
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=i386 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I386_M32
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_I386_M32: #define __LAHF_SAHF__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_I386_M32: #define __i386 1
// CHECK_I386_M32: #define __i386__ 1
// CHECK_I386_M32: #define __tune_i386__ 1
// CHECK_I386_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=i386 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I386_M64
// CHECK_I386_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=i486 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I486_M32
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_I486_M32: #define __i386 1
// CHECK_I486_M32: #define __i386__ 1
// CHECK_I486_M32: #define __i486 1
// CHECK_I486_M32: #define __i486__ 1
// CHECK_I486_M32: #define __tune_i486__ 1
// CHECK_I486_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=i486 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I486_M64
// CHECK_I486_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=i586 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I586_M32
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_I586_M32: #define __i386 1
// CHECK_I586_M32: #define __i386__ 1
// CHECK_I586_M32: #define __i586 1
// CHECK_I586_M32: #define __i586__ 1
// CHECK_I586_M32: #define __pentium 1
// CHECK_I586_M32: #define __pentium__ 1
// CHECK_I586_M32: #define __tune_i586__ 1
// CHECK_I586_M32: #define __tune_pentium__ 1
// CHECK_I586_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=i586 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I586_M64
// CHECK_I586_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=pentium -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_M32
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PENTIUM_M32: #define __i386 1
// CHECK_PENTIUM_M32: #define __i386__ 1
// CHECK_PENTIUM_M32: #define __i586 1
// CHECK_PENTIUM_M32: #define __i586__ 1
// CHECK_PENTIUM_M32: #define __pentium 1
// CHECK_PENTIUM_M32: #define __pentium__ 1
// CHECK_PENTIUM_M32: #define __tune_i586__ 1
// CHECK_PENTIUM_M32: #define __tune_pentium__ 1
// CHECK_PENTIUM_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=pentium -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_M64
// CHECK_PENTIUM_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=pentium-mmx -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_MMX_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_PENTIUM_MMX_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PENTIUM_MMX_M32: #define __i386 1
// CHECK_PENTIUM_MMX_M32: #define __i386__ 1
// CHECK_PENTIUM_MMX_M32: #define __i586 1
// CHECK_PENTIUM_MMX_M32: #define __i586__ 1
// CHECK_PENTIUM_MMX_M32: #define __pentium 1
// CHECK_PENTIUM_MMX_M32: #define __pentium__ 1
// CHECK_PENTIUM_MMX_M32: #define __pentium_mmx__ 1
// CHECK_PENTIUM_MMX_M32: #define __tune_i586__ 1
// CHECK_PENTIUM_MMX_M32: #define __tune_pentium__ 1
// CHECK_PENTIUM_MMX_M32: #define __tune_pentium_mmx__ 1
// CHECK_PENTIUM_MMX_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=pentium-mmx -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_MMX_M64
// CHECK_PENTIUM_MMX_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=winchip-c6 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_WINCHIP_C6_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_WINCHIP_C6_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_WINCHIP_C6_M32: #define __i386 1
// CHECK_WINCHIP_C6_M32: #define __i386__ 1
// CHECK_WINCHIP_C6_M32: #define __i486 1
// CHECK_WINCHIP_C6_M32: #define __i486__ 1
// CHECK_WINCHIP_C6_M32: #define __tune_i486__ 1
// CHECK_WINCHIP_C6_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=winchip-c6 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_WINCHIP_C6_M64
// CHECK_WINCHIP_C6_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=winchip2 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_WINCHIP2_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_WINCHIP2_M32: #define __3dNOW__ 1
// CHECK_WINCHIP2_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_WINCHIP2_M32: #define __i386 1
// CHECK_WINCHIP2_M32: #define __i386__ 1
// CHECK_WINCHIP2_M32: #define __i486 1
// CHECK_WINCHIP2_M32: #define __i486__ 1
// CHECK_WINCHIP2_M32: #define __tune_i486__ 1
// CHECK_WINCHIP2_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=winchip2 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_WINCHIP2_M64
// CHECK_WINCHIP2_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=c3 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C3_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_C3_M32: #define __3dNOW__ 1
// CHECK_C3_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_C3_M32: #define __i386 1
// CHECK_C3_M32: #define __i386__ 1
// CHECK_C3_M32: #define __i486 1
// CHECK_C3_M32: #define __i486__ 1
// CHECK_C3_M32: #define __tune_i486__ 1
// CHECK_C3_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=c3 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C3_M64
// CHECK_C3_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=c3-2 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C3_2_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_C3_2_M32: #define __MMX__ 1
// CHECK_C3_2_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_C3_2_M32: #define __i386 1
// CHECK_C3_2_M32: #define __i386__ 1
// CHECK_C3_2_M32: #define __i686 1
// CHECK_C3_2_M32: #define __i686__ 1
// CHECK_C3_2_M32: #define __pentiumpro 1
// CHECK_C3_2_M32: #define __pentiumpro__ 1
// CHECK_C3_2_M32: #define __tune_i686__ 1
// CHECK_C3_2_M32: #define __tune_pentium2__ 1
// CHECK_C3_2_M32: #define __tune_pentiumpro__ 1
// CHECK_C3_2_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=c3-2 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C3_2_M64
// CHECK_C3_2_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=i686 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I686_M32
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_I686_M32: #define __i386 1
// CHECK_I686_M32: #define __i386__ 1
// CHECK_I686_M32: #define __i686 1
// CHECK_I686_M32: #define __i686__ 1
// CHECK_I686_M32: #define __pentiumpro 1
// CHECK_I686_M32: #define __pentiumpro__ 1
[X86] Make -march=i686 an alias of -march=pentiumpro I think the only reason they are different is because we don't set tune_i686 for -march=i686 to match GCC. But GCC 4.9.0 seems to have changed this behavior and they do set it now. So I think they can aliases now. Differential Revision: https://reviews.llvm.org/D39349 llvm-svn: 316712
2017-10-27 07:06:19 +08:00
// CHECK_I686_M32: #define __tune_i686__ 1
// CHECK_I686_M32: #define __tune_pentiumpro__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_I686_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=i686 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I686_M64
// CHECK_I686_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=pentiumpro -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUMPRO_M32
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PENTIUMPRO_M32: #define __i386 1
// CHECK_PENTIUMPRO_M32: #define __i386__ 1
// CHECK_PENTIUMPRO_M32: #define __i686 1
// CHECK_PENTIUMPRO_M32: #define __i686__ 1
// CHECK_PENTIUMPRO_M32: #define __pentiumpro 1
// CHECK_PENTIUMPRO_M32: #define __pentiumpro__ 1
// CHECK_PENTIUMPRO_M32: #define __tune_i686__ 1
// CHECK_PENTIUMPRO_M32: #define __tune_pentiumpro__ 1
// CHECK_PENTIUMPRO_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=pentiumpro -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUMPRO_M64
// CHECK_PENTIUMPRO_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=pentium2 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM2_M32
[X86] Add 'fxsr' feature to -march=pentium2 to match X86.td and gcc.
2019-11-07 02:27:53 +08:00
// CHECK_PENTIUM2_M32: #define __FXSR__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_PENTIUM2_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PENTIUM2_M32: #define __i386 1
// CHECK_PENTIUM2_M32: #define __i386__ 1
// CHECK_PENTIUM2_M32: #define __i686 1
// CHECK_PENTIUM2_M32: #define __i686__ 1
// CHECK_PENTIUM2_M32: #define __pentiumpro 1
// CHECK_PENTIUM2_M32: #define __pentiumpro__ 1
// CHECK_PENTIUM2_M32: #define __tune_i686__ 1
// CHECK_PENTIUM2_M32: #define __tune_pentium2__ 1
// CHECK_PENTIUM2_M32: #define __tune_pentiumpro__ 1
// CHECK_PENTIUM2_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=pentium2 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM2_M64
// CHECK_PENTIUM2_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=pentium3 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM3_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_PENTIUM3_M32: #define __MMX__ 1
// CHECK_PENTIUM3_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PENTIUM3_M32: #define __i386 1
// CHECK_PENTIUM3_M32: #define __i386__ 1
// CHECK_PENTIUM3_M32: #define __i686 1
// CHECK_PENTIUM3_M32: #define __i686__ 1
// CHECK_PENTIUM3_M32: #define __pentiumpro 1
// CHECK_PENTIUM3_M32: #define __pentiumpro__ 1
// CHECK_PENTIUM3_M32: #define __tune_i686__ 1
// CHECK_PENTIUM3_M32: #define __tune_pentium2__ 1
// CHECK_PENTIUM3_M32: #define __tune_pentium3__ 1
// CHECK_PENTIUM3_M32: #define __tune_pentiumpro__ 1
// CHECK_PENTIUM3_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=pentium3 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM3_M64
// CHECK_PENTIUM3_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=pentium3m -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM3M_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_PENTIUM3M_M32: #define __MMX__ 1
// CHECK_PENTIUM3M_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PENTIUM3M_M32: #define __i386 1
// CHECK_PENTIUM3M_M32: #define __i386__ 1
// CHECK_PENTIUM3M_M32: #define __i686 1
// CHECK_PENTIUM3M_M32: #define __i686__ 1
// CHECK_PENTIUM3M_M32: #define __pentiumpro 1
// CHECK_PENTIUM3M_M32: #define __pentiumpro__ 1
// CHECK_PENTIUM3M_M32: #define __tune_i686__ 1
// CHECK_PENTIUM3M_M32: #define __tune_pentiumpro__ 1
// CHECK_PENTIUM3M_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=pentium3m -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM3M_M64
// CHECK_PENTIUM3M_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=pentium-m -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_M_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_PENTIUM_M_M32: #define __MMX__ 1
// CHECK_PENTIUM_M_M32: #define __SSE2__ 1
// CHECK_PENTIUM_M_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PENTIUM_M_M32: #define __i386 1
// CHECK_PENTIUM_M_M32: #define __i386__ 1
// CHECK_PENTIUM_M_M32: #define __i686 1
// CHECK_PENTIUM_M_M32: #define __i686__ 1
// CHECK_PENTIUM_M_M32: #define __pentiumpro 1
// CHECK_PENTIUM_M_M32: #define __pentiumpro__ 1
// CHECK_PENTIUM_M_M32: #define __tune_i686__ 1
// CHECK_PENTIUM_M_M32: #define __tune_pentiumpro__ 1
// CHECK_PENTIUM_M_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=pentium-m -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_M_M64
// CHECK_PENTIUM_M_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=pentium4 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM4_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_PENTIUM4_M32: #define __MMX__ 1
// CHECK_PENTIUM4_M32: #define __SSE2__ 1
// CHECK_PENTIUM4_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PENTIUM4_M32: #define __i386 1
// CHECK_PENTIUM4_M32: #define __i386__ 1
// CHECK_PENTIUM4_M32: #define __pentium4 1
// CHECK_PENTIUM4_M32: #define __pentium4__ 1
// CHECK_PENTIUM4_M32: #define __tune_pentium4__ 1
// CHECK_PENTIUM4_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=pentium4 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM4_M64
// CHECK_PENTIUM4_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=pentium4m -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM4M_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_PENTIUM4M_M32: #define __MMX__ 1
// CHECK_PENTIUM4M_M32: #define __SSE2__ 1
// CHECK_PENTIUM4M_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PENTIUM4M_M32: #define __i386 1
// CHECK_PENTIUM4M_M32: #define __i386__ 1
// CHECK_PENTIUM4M_M32: #define __pentium4 1
// CHECK_PENTIUM4M_M32: #define __pentium4__ 1
// CHECK_PENTIUM4M_M32: #define __tune_pentium4__ 1
// CHECK_PENTIUM4M_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=pentium4m -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM4M_M64
// CHECK_PENTIUM4M_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[X86] Add 'yonah' test to predefined-arch-macros.c test. llvm-svn: 356007
2019-03-13 13:14:50 +08:00
// RUN: %clang -march=yonah -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_YONAH_M32
// CHECK_YONAH_M32: #define __MMX__ 1
// CHECK_YONAH_M32: #define __SSE2__ 1
// CHECK_YONAH_M32: #define __SSE3__ 1
// CHECK_YONAH_M32: #define __SSE__ 1
// CHECK_YONAH_M32: #define __i386 1
// CHECK_YONAH_M32: #define __i386__ 1
// CHECK_YONAH_M32: #define __nocona 1
// CHECK_YONAH_M32: #define __nocona__ 1
// CHECK_YONAH_M32: #define __tune_nocona__ 1
// CHECK_YONAH_M32: #define i386 1
// RUN: not %clang -march=yonah -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_YONAH_M64
// CHECK_YONAH_M64: error: {{.*}}
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=prescott -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PRESCOTT_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_PRESCOTT_M32: #define __MMX__ 1
// CHECK_PRESCOTT_M32: #define __SSE2__ 1
// CHECK_PRESCOTT_M32: #define __SSE3__ 1
// CHECK_PRESCOTT_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_PRESCOTT_M32: #define __i386 1
// CHECK_PRESCOTT_M32: #define __i386__ 1
// CHECK_PRESCOTT_M32: #define __nocona 1
// CHECK_PRESCOTT_M32: #define __nocona__ 1
// CHECK_PRESCOTT_M32: #define __tune_nocona__ 1
// CHECK_PRESCOTT_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=prescott -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PRESCOTT_M64
// CHECK_PRESCOTT_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=nocona -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_NOCONA_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_NOCONA_M32: #define __MMX__ 1
// CHECK_NOCONA_M32: #define __SSE2__ 1
// CHECK_NOCONA_M32: #define __SSE3__ 1
// CHECK_NOCONA_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_NOCONA_M32: #define __i386 1
// CHECK_NOCONA_M32: #define __i386__ 1
// CHECK_NOCONA_M32: #define __nocona 1
// CHECK_NOCONA_M32: #define __nocona__ 1
// CHECK_NOCONA_M32: #define __tune_nocona__ 1
// CHECK_NOCONA_M32: #define i386 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=nocona -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_NOCONA_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_NOCONA_M64: #define __MMX__ 1
// CHECK_NOCONA_M64: #define __SSE2_MATH__ 1
// CHECK_NOCONA_M64: #define __SSE2__ 1
// CHECK_NOCONA_M64: #define __SSE3__ 1
// CHECK_NOCONA_M64: #define __SSE_MATH__ 1
// CHECK_NOCONA_M64: #define __SSE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_NOCONA_M64: #define __amd64 1
// CHECK_NOCONA_M64: #define __amd64__ 1
// CHECK_NOCONA_M64: #define __nocona 1
// CHECK_NOCONA_M64: #define __nocona__ 1
// CHECK_NOCONA_M64: #define __tune_nocona__ 1
// CHECK_NOCONA_M64: #define __x86_64 1
// CHECK_NOCONA_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=core2 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE2_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_CORE2_M32: #define __MMX__ 1
// CHECK_CORE2_M32: #define __SSE2__ 1
// CHECK_CORE2_M32: #define __SSE3__ 1
// CHECK_CORE2_M32: #define __SSE__ 1
// CHECK_CORE2_M32: #define __SSSE3__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_CORE2_M32: #define __core2 1
// CHECK_CORE2_M32: #define __core2__ 1
// CHECK_CORE2_M32: #define __i386 1
// CHECK_CORE2_M32: #define __i386__ 1
// CHECK_CORE2_M32: #define __tune_core2__ 1
// CHECK_CORE2_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=core2 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE2_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_CORE2_M64: #define __MMX__ 1
// CHECK_CORE2_M64: #define __SSE2_MATH__ 1
// CHECK_CORE2_M64: #define __SSE2__ 1
// CHECK_CORE2_M64: #define __SSE3__ 1
// CHECK_CORE2_M64: #define __SSE_MATH__ 1
// CHECK_CORE2_M64: #define __SSE__ 1
// CHECK_CORE2_M64: #define __SSSE3__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_CORE2_M64: #define __amd64 1
// CHECK_CORE2_M64: #define __amd64__ 1
// CHECK_CORE2_M64: #define __core2 1
// CHECK_CORE2_M64: #define __core2__ 1
// CHECK_CORE2_M64: #define __tune_core2__ 1
// CHECK_CORE2_M64: #define __x86_64 1
// CHECK_CORE2_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=corei7 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_COREI7_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_COREI7_M32: #define __MMX__ 1
Add __POPCNT__ to test cases for corei7 and corei7-avx llvm-svn: 157905
2012-06-04 05:49:41 +08:00
// CHECK_COREI7_M32: #define __POPCNT__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_COREI7_M32: #define __SSE2__ 1
// CHECK_COREI7_M32: #define __SSE3__ 1
// CHECK_COREI7_M32: #define __SSE4_1__ 1
// CHECK_COREI7_M32: #define __SSE4_2__ 1
// CHECK_COREI7_M32: #define __SSE__ 1
// CHECK_COREI7_M32: #define __SSSE3__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_COREI7_M32: #define __corei7 1
// CHECK_COREI7_M32: #define __corei7__ 1
// CHECK_COREI7_M32: #define __i386 1
// CHECK_COREI7_M32: #define __i386__ 1
// CHECK_COREI7_M32: #define __tune_corei7__ 1
// CHECK_COREI7_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=corei7 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_COREI7_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_COREI7_M64: #define __MMX__ 1
Add __POPCNT__ to test cases for corei7 and corei7-avx llvm-svn: 157905
2012-06-04 05:49:41 +08:00
// CHECK_COREI7_M64: #define __POPCNT__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_COREI7_M64: #define __SSE2_MATH__ 1
// CHECK_COREI7_M64: #define __SSE2__ 1
// CHECK_COREI7_M64: #define __SSE3__ 1
// CHECK_COREI7_M64: #define __SSE4_1__ 1
// CHECK_COREI7_M64: #define __SSE4_2__ 1
// CHECK_COREI7_M64: #define __SSE_MATH__ 1
// CHECK_COREI7_M64: #define __SSE__ 1
// CHECK_COREI7_M64: #define __SSSE3__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_COREI7_M64: #define __amd64 1
// CHECK_COREI7_M64: #define __amd64__ 1
// CHECK_COREI7_M64: #define __corei7 1
// CHECK_COREI7_M64: #define __corei7__ 1
// CHECK_COREI7_M64: #define __tune_corei7__ 1
// CHECK_COREI7_M64: #define __x86_64 1
// CHECK_COREI7_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=corei7-avx -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_COREI7_AVX_M32
Enable AVX/AVX2 for Sandy Bridge, Ivy Bridge, and Haswell CPUs. llvm-svn: 155624
2012-04-26 15:31:30 +08:00
// CHECK_COREI7_AVX_M32: #define __AVX__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_COREI7_AVX_M32: #define __MMX__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_COREI7_AVX_M32: #define __PCLMUL__ 1
Wire up -mrdrnd for X86. For some reason GCC decided to call the feature rdrnd instead of rdrand, which requires translating it for LLVM. llvm-svn: 159897
2012-07-07 17:39:18 +08:00
// CHECK_COREI7_AVX_M32-NOT: __RDRND__
Add __POPCNT__ to test cases for corei7 and corei7-avx llvm-svn: 157905
2012-06-04 05:49:41 +08:00
// CHECK_COREI7_AVX_M32: #define __POPCNT__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_COREI7_AVX_M32: #define __SSE2__ 1
// CHECK_COREI7_AVX_M32: #define __SSE3__ 1
// CHECK_COREI7_AVX_M32: #define __SSE4_1__ 1
// CHECK_COREI7_AVX_M32: #define __SSE4_2__ 1
// CHECK_COREI7_AVX_M32: #define __SSE__ 1
// CHECK_COREI7_AVX_M32: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_COREI7_AVX_M32: #define __XSAVEOPT__ 1
// CHECK_COREI7_AVX_M32: #define __XSAVE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_COREI7_AVX_M32: #define __corei7 1
// CHECK_COREI7_AVX_M32: #define __corei7__ 1
// CHECK_COREI7_AVX_M32: #define __i386 1
// CHECK_COREI7_AVX_M32: #define __i386__ 1
// CHECK_COREI7_AVX_M32: #define __tune_corei7__ 1
// CHECK_COREI7_AVX_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=corei7-avx -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_COREI7_AVX_M64
Enable AVX/AVX2 for Sandy Bridge, Ivy Bridge, and Haswell CPUs. llvm-svn: 155624
2012-04-26 15:31:30 +08:00
// CHECK_COREI7_AVX_M64: #define __AVX__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_COREI7_AVX_M64: #define __MMX__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_COREI7_AVX_M64: #define __PCLMUL__ 1
Wire up -mrdrnd for X86. For some reason GCC decided to call the feature rdrnd instead of rdrand, which requires translating it for LLVM. llvm-svn: 159897
2012-07-07 17:39:18 +08:00
// CHECK_COREI7_AVX_M64-NOT: __RDRND__
Add __POPCNT__ to test cases for corei7 and corei7-avx llvm-svn: 157905
2012-06-04 05:49:41 +08:00
// CHECK_COREI7_AVX_M64: #define __POPCNT__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_COREI7_AVX_M64: #define __SSE2_MATH__ 1
// CHECK_COREI7_AVX_M64: #define __SSE2__ 1
// CHECK_COREI7_AVX_M64: #define __SSE3__ 1
// CHECK_COREI7_AVX_M64: #define __SSE4_1__ 1
// CHECK_COREI7_AVX_M64: #define __SSE4_2__ 1
// CHECK_COREI7_AVX_M64: #define __SSE_MATH__ 1
// CHECK_COREI7_AVX_M64: #define __SSE__ 1
// CHECK_COREI7_AVX_M64: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_COREI7_AVX_M64: #define __XSAVEOPT__ 1
// CHECK_COREI7_AVX_M64: #define __XSAVE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_COREI7_AVX_M64: #define __amd64 1
// CHECK_COREI7_AVX_M64: #define __amd64__ 1
// CHECK_COREI7_AVX_M64: #define __corei7 1
// CHECK_COREI7_AVX_M64: #define __corei7__ 1
// CHECK_COREI7_AVX_M64: #define __tune_corei7__ 1
// CHECK_COREI7_AVX_M64: #define __x86_64 1
// CHECK_COREI7_AVX_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=core-avx-i -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE_AVX_I_M32
Enable AVX/AVX2 for Sandy Bridge, Ivy Bridge, and Haswell CPUs. llvm-svn: 155624
2012-04-26 15:31:30 +08:00
// CHECK_CORE_AVX_I_M32: #define __AVX__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_CORE_AVX_I_M32: #define __F16C__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_CORE_AVX_I_M32: #define __MMX__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX_I_M32: #define __PCLMUL__ 1
Wire up -mrdrnd for X86. For some reason GCC decided to call the feature rdrnd instead of rdrand, which requires translating it for LLVM. llvm-svn: 159897
2012-07-07 17:39:18 +08:00
// CHECK_CORE_AVX_I_M32: #define __RDRND__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_CORE_AVX_I_M32: #define __SSE2__ 1
// CHECK_CORE_AVX_I_M32: #define __SSE3__ 1
// CHECK_CORE_AVX_I_M32: #define __SSE4_1__ 1
// CHECK_CORE_AVX_I_M32: #define __SSE4_2__ 1
// CHECK_CORE_AVX_I_M32: #define __SSE__ 1
// CHECK_CORE_AVX_I_M32: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_CORE_AVX_I_M32: #define __XSAVEOPT__ 1
// CHECK_CORE_AVX_I_M32: #define __XSAVE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_CORE_AVX_I_M32: #define __corei7 1
// CHECK_CORE_AVX_I_M32: #define __corei7__ 1
// CHECK_CORE_AVX_I_M32: #define __i386 1
// CHECK_CORE_AVX_I_M32: #define __i386__ 1
// CHECK_CORE_AVX_I_M32: #define __tune_corei7__ 1
// CHECK_CORE_AVX_I_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=core-avx-i -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE_AVX_I_M64
Enable AVX/AVX2 for Sandy Bridge, Ivy Bridge, and Haswell CPUs. llvm-svn: 155624
2012-04-26 15:31:30 +08:00
// CHECK_CORE_AVX_I_M64: #define __AVX__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_CORE_AVX_I_M64: #define __F16C__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_CORE_AVX_I_M64: #define __MMX__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX_I_M64: #define __PCLMUL__ 1
Wire up -mrdrnd for X86. For some reason GCC decided to call the feature rdrnd instead of rdrand, which requires translating it for LLVM. llvm-svn: 159897
2012-07-07 17:39:18 +08:00
// CHECK_CORE_AVX_I_M64: #define __RDRND__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_CORE_AVX_I_M64: #define __SSE2_MATH__ 1
// CHECK_CORE_AVX_I_M64: #define __SSE2__ 1
// CHECK_CORE_AVX_I_M64: #define __SSE3__ 1
// CHECK_CORE_AVX_I_M64: #define __SSE4_1__ 1
// CHECK_CORE_AVX_I_M64: #define __SSE4_2__ 1
// CHECK_CORE_AVX_I_M64: #define __SSE_MATH__ 1
// CHECK_CORE_AVX_I_M64: #define __SSE__ 1
// CHECK_CORE_AVX_I_M64: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_CORE_AVX_I_M64: #define __XSAVEOPT__ 1
// CHECK_CORE_AVX_I_M64: #define __XSAVE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_CORE_AVX_I_M64: #define __amd64 1
// CHECK_CORE_AVX_I_M64: #define __amd64__ 1
// CHECK_CORE_AVX_I_M64: #define __corei7 1
// CHECK_CORE_AVX_I_M64: #define __corei7__ 1
// CHECK_CORE_AVX_I_M64: #define __tune_corei7__ 1
// CHECK_CORE_AVX_I_M64: #define __x86_64 1
// CHECK_CORE_AVX_I_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// RUN: %clang -march=core-avx2 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE_AVX2_M32
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_CORE_AVX2_M32: #define __AVX2__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M32: #define __AVX__ 1
// CHECK_CORE_AVX2_M32: #define __BMI2__ 1
// CHECK_CORE_AVX2_M32: #define __BMI__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_CORE_AVX2_M32: #define __F16C__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M32: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_CORE_AVX2_M32: #define __INVPCID__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_CORE_AVX2_M32: #define __LAHF_SAHF__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M32: #define __LZCNT__ 1
// CHECK_CORE_AVX2_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_CORE_AVX2_M32: #define __MOVBE__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M32: #define __PCLMUL__ 1
// CHECK_CORE_AVX2_M32: #define __POPCNT__ 1
Wire up -mrdrnd for X86. For some reason GCC decided to call the feature rdrnd instead of rdrand, which requires translating it for LLVM. llvm-svn: 159897
2012-07-07 17:39:18 +08:00
// CHECK_CORE_AVX2_M32: #define __RDRND__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M32: #define __SSE2__ 1
// CHECK_CORE_AVX2_M32: #define __SSE3__ 1
// CHECK_CORE_AVX2_M32: #define __SSE4_1__ 1
// CHECK_CORE_AVX2_M32: #define __SSE4_2__ 1
// CHECK_CORE_AVX2_M32: #define __SSE__ 1
// CHECK_CORE_AVX2_M32: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_CORE_AVX2_M32: #define __XSAVEOPT__ 1
// CHECK_CORE_AVX2_M32: #define __XSAVE__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M32: #define __corei7 1
// CHECK_CORE_AVX2_M32: #define __corei7__ 1
// CHECK_CORE_AVX2_M32: #define __i386 1
// CHECK_CORE_AVX2_M32: #define __i386__ 1
// CHECK_CORE_AVX2_M32: #define __tune_corei7__ 1
// CHECK_CORE_AVX2_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// RUN: %clang -march=core-avx2 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE_AVX2_M64
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_CORE_AVX2_M64: #define __AVX2__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M64: #define __AVX__ 1
// CHECK_CORE_AVX2_M64: #define __BMI2__ 1
// CHECK_CORE_AVX2_M64: #define __BMI__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_CORE_AVX2_M64: #define __F16C__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M64: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_CORE_AVX2_M64: #define __INVPCID__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_CORE_AVX2_M64: #define __LAHF_SAHF__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M64: #define __LZCNT__ 1
// CHECK_CORE_AVX2_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_CORE_AVX2_M64: #define __MOVBE__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M64: #define __PCLMUL__ 1
// CHECK_CORE_AVX2_M64: #define __POPCNT__ 1
Wire up -mrdrnd for X86. For some reason GCC decided to call the feature rdrnd instead of rdrand, which requires translating it for LLVM. llvm-svn: 159897
2012-07-07 17:39:18 +08:00
// CHECK_CORE_AVX2_M64: #define __RDRND__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M64: #define __SSE2_MATH__ 1
// CHECK_CORE_AVX2_M64: #define __SSE2__ 1
// CHECK_CORE_AVX2_M64: #define __SSE3__ 1
// CHECK_CORE_AVX2_M64: #define __SSE4_1__ 1
// CHECK_CORE_AVX2_M64: #define __SSE4_2__ 1
// CHECK_CORE_AVX2_M64: #define __SSE_MATH__ 1
// CHECK_CORE_AVX2_M64: #define __SSE__ 1
// CHECK_CORE_AVX2_M64: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_CORE_AVX2_M64: #define __XSAVEOPT__ 1
// CHECK_CORE_AVX2_M64: #define __XSAVE__ 1
Add fma feature flag for Intel FMA instructions. llvm-svn: 157904
2012-06-04 05:46:30 +08:00
// CHECK_CORE_AVX2_M64: #define __amd64 1
// CHECK_CORE_AVX2_M64: #define __amd64__ 1
// CHECK_CORE_AVX2_M64: #define __corei7 1
// CHECK_CORE_AVX2_M64: #define __corei7__ 1
// CHECK_CORE_AVX2_M64: #define __tune_corei7__ 1
// CHECK_CORE_AVX2_M64: #define __x86_64 1
// CHECK_CORE_AVX2_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// RUN: %clang -march=broadwell -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BROADWELL_M32
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M32: #define __ADX__ 1
// CHECK_BROADWELL_M32: #define __AVX2__ 1
// CHECK_BROADWELL_M32: #define __AVX__ 1
// CHECK_BROADWELL_M32: #define __BMI2__ 1
// CHECK_BROADWELL_M32: #define __BMI__ 1
// CHECK_BROADWELL_M32: #define __F16C__ 1
// CHECK_BROADWELL_M32: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_BROADWELL_M32: #define __INVPCID__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_BROADWELL_M32: #define __LAHF_SAHF__ 1
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M32: #define __LZCNT__ 1
// CHECK_BROADWELL_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_BROADWELL_M32: #define __MOVBE__ 1
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M32: #define __PCLMUL__ 1
// CHECK_BROADWELL_M32: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_BROADWELL_M32: #define __PRFCHW__ 1
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M32: #define __RDRND__ 1
// CHECK_BROADWELL_M32: #define __RDSEED__ 1
// CHECK_BROADWELL_M32: #define __SSE2__ 1
// CHECK_BROADWELL_M32: #define __SSE3__ 1
// CHECK_BROADWELL_M32: #define __SSE4_1__ 1
// CHECK_BROADWELL_M32: #define __SSE4_2__ 1
// CHECK_BROADWELL_M32: #define __SSE__ 1
// CHECK_BROADWELL_M32: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BROADWELL_M32: #define __XSAVEOPT__ 1
// CHECK_BROADWELL_M32: #define __XSAVE__ 1
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M32: #define __corei7 1
// CHECK_BROADWELL_M32: #define __corei7__ 1
// CHECK_BROADWELL_M32: #define __i386 1
// CHECK_BROADWELL_M32: #define __i386__ 1
// CHECK_BROADWELL_M32: #define __tune_corei7__ 1
// CHECK_BROADWELL_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// RUN: %clang -march=broadwell -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BROADWELL_M64
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M64: #define __ADX__ 1
// CHECK_BROADWELL_M64: #define __AVX2__ 1
// CHECK_BROADWELL_M64: #define __AVX__ 1
// CHECK_BROADWELL_M64: #define __BMI2__ 1
// CHECK_BROADWELL_M64: #define __BMI__ 1
// CHECK_BROADWELL_M64: #define __F16C__ 1
// CHECK_BROADWELL_M64: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_BROADWELL_M64: #define __INVPCID__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_BROADWELL_M64: #define __LAHF_SAHF__ 1
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M64: #define __LZCNT__ 1
// CHECK_BROADWELL_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_BROADWELL_M64: #define __MOVBE__ 1
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M64: #define __PCLMUL__ 1
// CHECK_BROADWELL_M64: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_BROADWELL_M64: #define __PRFCHW__ 1
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M64: #define __RDRND__ 1
// CHECK_BROADWELL_M64: #define __RDSEED__ 1
// CHECK_BROADWELL_M64: #define __SSE2_MATH__ 1
// CHECK_BROADWELL_M64: #define __SSE2__ 1
// CHECK_BROADWELL_M64: #define __SSE3__ 1
// CHECK_BROADWELL_M64: #define __SSE4_1__ 1
// CHECK_BROADWELL_M64: #define __SSE4_2__ 1
// CHECK_BROADWELL_M64: #define __SSE_MATH__ 1
// CHECK_BROADWELL_M64: #define __SSE__ 1
// CHECK_BROADWELL_M64: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BROADWELL_M64: #define __XSAVEOPT__ 1
// CHECK_BROADWELL_M64: #define __XSAVE__ 1
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// CHECK_BROADWELL_M64: #define __amd64 1
// CHECK_BROADWELL_M64: #define __amd64__ 1
// CHECK_BROADWELL_M64: #define __corei7 1
// CHECK_BROADWELL_M64: #define __corei7__ 1
// CHECK_BROADWELL_M64: #define __tune_corei7__ 1
// CHECK_BROADWELL_M64: #define __x86_64 1
// CHECK_BROADWELL_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// RUN: %clang -march=skylake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SKL_M32
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M32: #define __ADX__ 1
// CHECK_SKL_M32: #define __AES__ 1
// CHECK_SKL_M32: #define __AVX2__ 1
// CHECK_SKL_M32: #define __AVX__ 1
// CHECK_SKL_M32: #define __BMI2__ 1
// CHECK_SKL_M32: #define __BMI__ 1
[X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
2017-02-08 14:48:58 +08:00
// CHECK_SKL_M32: #define __CLFLUSHOPT__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M32: #define __F16C__ 1
// CHECK_SKL_M32: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_SKL_M32: #define __INVPCID__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M32: #define __LZCNT__ 1
// CHECK_SKL_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_SKL_M32: #define __MOVBE__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M32: #define __PCLMUL__ 1
// CHECK_SKL_M32: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_SKL_M32: #define __PRFCHW__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M32: #define __RDRND__ 1
// CHECK_SKL_M32: #define __RDSEED__ 1
[X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc. llvm-svn: 294423
2017-02-08 16:23:17 +08:00
// CHECK_SKL_M32: #define __SGX__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M32: #define __SSE2__ 1
// CHECK_SKL_M32: #define __SSE3__ 1
// CHECK_SKL_M32: #define __SSE4_1__ 1
// CHECK_SKL_M32: #define __SSE4_2__ 1
// CHECK_SKL_M32: #define __SSE__ 1
// CHECK_SKL_M32: #define __SSSE3__ 1
// CHECK_SKL_M32: #define __XSAVEC__ 1
// CHECK_SKL_M32: #define __XSAVEOPT__ 1
// CHECK_SKL_M32: #define __XSAVES__ 1
// CHECK_SKL_M32: #define __XSAVE__ 1
// CHECK_SKL_M32: #define i386 1
// RUN: %clang -march=skylake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SKL_M64
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M64: #define __ADX__ 1
// CHECK_SKL_M64: #define __AES__ 1
// CHECK_SKL_M64: #define __AVX2__ 1
// CHECK_SKL_M64: #define __AVX__ 1
// CHECK_SKL_M64: #define __BMI2__ 1
// CHECK_SKL_M64: #define __BMI__ 1
[X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
2017-02-08 14:48:58 +08:00
// CHECK_SKL_M64: #define __CLFLUSHOPT__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M64: #define __F16C__ 1
// CHECK_SKL_M64: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_SKL_M64: #define __INVPCID__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M64: #define __LZCNT__ 1
// CHECK_SKL_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_SKL_M64: #define __MOVBE__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M64: #define __PCLMUL__ 1
// CHECK_SKL_M64: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_SKL_M64: #define __PRFCHW__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M64: #define __RDRND__ 1
// CHECK_SKL_M64: #define __RDSEED__ 1
[X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc. llvm-svn: 294423
2017-02-08 16:23:17 +08:00
// CHECK_SKL_M64: #define __SGX__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_SKL_M64: #define __SSE2_MATH__ 1
// CHECK_SKL_M64: #define __SSE2__ 1
// CHECK_SKL_M64: #define __SSE3__ 1
// CHECK_SKL_M64: #define __SSE4_1__ 1
// CHECK_SKL_M64: #define __SSE4_2__ 1
// CHECK_SKL_M64: #define __SSE_MATH__ 1
// CHECK_SKL_M64: #define __SSE__ 1
// CHECK_SKL_M64: #define __SSSE3__ 1
// CHECK_SKL_M64: #define __XSAVEC__ 1
// CHECK_SKL_M64: #define __XSAVEOPT__ 1
// CHECK_SKL_M64: #define __XSAVES__ 1
// CHECK_SKL_M64: #define __XSAVE__ 1
// CHECK_SKL_M64: #define __amd64 1
// CHECK_SKL_M64: #define __amd64__ 1
// CHECK_SKL_M64: #define __x86_64 1
// CHECK_SKL_M64: #define __x86_64__ 1
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// RUN: %clang -march=knl -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_KNL_M32
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M32: #define __AES__ 1
// CHECK_KNL_M32: #define __AVX2__ 1
Add avx512cd, avx512er, avx512pf feature flags and enable them on KNL CPU. llvm-svn: 188867
2013-08-21 13:29:10 +08:00
// CHECK_KNL_M32: #define __AVX512CD__ 1
// CHECK_KNL_M32: #define __AVX512ER__ 1
Rename __AVX512__ to __AVX512F__ llvm-svn: 188764
2013-08-20 15:52:37 +08:00
// CHECK_KNL_M32: #define __AVX512F__ 1
Add avx512cd, avx512er, avx512pf feature flags and enable them on KNL CPU. llvm-svn: 188867
2013-08-21 13:29:10 +08:00
// CHECK_KNL_M32: #define __AVX512PF__ 1
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M32: #define __AVX__ 1
// CHECK_KNL_M32: #define __BMI2__ 1
// CHECK_KNL_M32: #define __BMI__ 1
// CHECK_KNL_M32: #define __F16C__ 1
// CHECK_KNL_M32: #define __FMA__ 1
// CHECK_KNL_M32: #define __LZCNT__ 1
// CHECK_KNL_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_KNL_M32: #define __MOVBE__ 1
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M32: #define __PCLMUL__ 1
// CHECK_KNL_M32: #define __POPCNT__ 1
[X86] Add -mprefetchwt1/-mno-prefetchwt1 command line options and __PREFETCHWT1__ define to match gcc. llvm-svn: 294424
2017-02-08 16:23:40 +08:00
// CHECK_KNL_M32: #define __PREFETCHWT1__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_KNL_M32: #define __PRFCHW__ 1
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M32: #define __RDRND__ 1
// CHECK_KNL_M32: #define __SSE2__ 1
// CHECK_KNL_M32: #define __SSE3__ 1
// CHECK_KNL_M32: #define __SSE4_1__ 1
// CHECK_KNL_M32: #define __SSE4_2__ 1
// CHECK_KNL_M32: #define __SSE__ 1
// CHECK_KNL_M32: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_KNL_M32: #define __XSAVEOPT__ 1
// CHECK_KNL_M32: #define __XSAVE__ 1
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M32: #define __i386 1
// CHECK_KNL_M32: #define __i386__ 1
// CHECK_KNL_M32: #define __knl 1
// CHECK_KNL_M32: #define __knl__ 1
// CHECK_KNL_M32: #define __tune_knl__ 1
// CHECK_KNL_M32: #define i386 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// RUN: %clang -march=knl -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_KNL_M64
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M64: #define __AES__ 1
// CHECK_KNL_M64: #define __AVX2__ 1
Add avx512cd, avx512er, avx512pf feature flags and enable them on KNL CPU. llvm-svn: 188867
2013-08-21 13:29:10 +08:00
// CHECK_KNL_M64: #define __AVX512CD__ 1
// CHECK_KNL_M64: #define __AVX512ER__ 1
Rename __AVX512__ to __AVX512F__ llvm-svn: 188764
2013-08-20 15:52:37 +08:00
// CHECK_KNL_M64: #define __AVX512F__ 1
Add avx512cd, avx512er, avx512pf feature flags and enable them on KNL CPU. llvm-svn: 188867
2013-08-21 13:29:10 +08:00
// CHECK_KNL_M64: #define __AVX512PF__ 1
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M64: #define __AVX__ 1
// CHECK_KNL_M64: #define __BMI2__ 1
// CHECK_KNL_M64: #define __BMI__ 1
// CHECK_KNL_M64: #define __F16C__ 1
// CHECK_KNL_M64: #define __FMA__ 1
// CHECK_KNL_M64: #define __LZCNT__ 1
// CHECK_KNL_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_KNL_M64: #define __MOVBE__ 1
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M64: #define __PCLMUL__ 1
// CHECK_KNL_M64: #define __POPCNT__ 1
[X86] Add -mprefetchwt1/-mno-prefetchwt1 command line options and __PREFETCHWT1__ define to match gcc. llvm-svn: 294424
2017-02-08 16:23:40 +08:00
// CHECK_KNL_M64: #define __PREFETCHWT1__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_KNL_M64: #define __PRFCHW__ 1
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M64: #define __RDRND__ 1
// CHECK_KNL_M64: #define __SSE2_MATH__ 1
// CHECK_KNL_M64: #define __SSE2__ 1
// CHECK_KNL_M64: #define __SSE3__ 1
// CHECK_KNL_M64: #define __SSE4_1__ 1
// CHECK_KNL_M64: #define __SSE4_2__ 1
// CHECK_KNL_M64: #define __SSE_MATH__ 1
// CHECK_KNL_M64: #define __SSE__ 1
// CHECK_KNL_M64: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_KNL_M64: #define __XSAVEOPT__ 1
// CHECK_KNL_M64: #define __XSAVE__ 1
Add AVX-512 feature flag and knl cpu to clang. llvm-svn: 188758
2013-08-20 15:09:39 +08:00
// CHECK_KNL_M64: #define __amd64 1
// CHECK_KNL_M64: #define __amd64__ 1
// CHECK_KNL_M64: #define __knl 1
// CHECK_KNL_M64: #define __knl__ 1
// CHECK_KNL_M64: #define __tune_knl__ 1
// CHECK_KNL_M64: #define __x86_64 1
// CHECK_KNL_M64: #define __x86_64__ 1
[X86] Add skeleton support for knm cpu This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation. Differential Revision: https://reviews.llvm.org/D38813 llvm-svn: 315723
2017-10-14 02:14:24 +08:00
// RUN: %clang -march=knm -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_KNM_M32
// CHECK_KNM_M32: #define __AES__ 1
// CHECK_KNM_M32: #define __AVX2__ 1
// CHECK_KNM_M32: #define __AVX512CD__ 1
// CHECK_KNM_M32: #define __AVX512ER__ 1
// CHECK_KNM_M32: #define __AVX512F__ 1
// CHECK_KNM_M32: #define __AVX512PF__ 1
[X86] Add avx512vpopcntdq to Knights Mill As indicated by Table 1-1 in Intel Architecture Instruction Set Extensions and Future Features Programming Reference from October 2017. llvm-svn: 316593
2017-10-26 01:10:58 +08:00
// CHECK_KNM_M32: #define __AVX512VPOPCNTDQ__ 1
[X86] Add skeleton support for knm cpu This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation. Differential Revision: https://reviews.llvm.org/D38813 llvm-svn: 315723
2017-10-14 02:14:24 +08:00
// CHECK_KNM_M32: #define __AVX__ 1
// CHECK_KNM_M32: #define __BMI2__ 1
// CHECK_KNM_M32: #define __BMI__ 1
// CHECK_KNM_M32: #define __F16C__ 1
// CHECK_KNM_M32: #define __FMA__ 1
// CHECK_KNM_M32: #define __LZCNT__ 1
// CHECK_KNM_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_KNM_M32: #define __MOVBE__ 1
[X86] Add skeleton support for knm cpu This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation. Differential Revision: https://reviews.llvm.org/D38813 llvm-svn: 315723
2017-10-14 02:14:24 +08:00
// CHECK_KNM_M32: #define __PCLMUL__ 1
// CHECK_KNM_M32: #define __POPCNT__ 1
// CHECK_KNM_M32: #define __PREFETCHWT1__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_KNM_M32: #define __PRFCHW__ 1
[X86] Add skeleton support for knm cpu This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation. Differential Revision: https://reviews.llvm.org/D38813 llvm-svn: 315723
2017-10-14 02:14:24 +08:00
// CHECK_KNM_M32: #define __RDRND__ 1
// CHECK_KNM_M32: #define __SSE2__ 1
// CHECK_KNM_M32: #define __SSE3__ 1
// CHECK_KNM_M32: #define __SSE4_1__ 1
// CHECK_KNM_M32: #define __SSE4_2__ 1
// CHECK_KNM_M32: #define __SSE__ 1
// CHECK_KNM_M32: #define __SSSE3__ 1
// CHECK_KNM_M32: #define __XSAVEOPT__ 1
// CHECK_KNM_M32: #define __XSAVE__ 1
// CHECK_KNM_M32: #define __i386 1
// CHECK_KNM_M32: #define __i386__ 1
// CHECK_KNM_M32: #define i386 1
// RUN: %clang -march=knm -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_KNM_M64
// CHECK_KNM_M64: #define __AES__ 1
// CHECK_KNM_M64: #define __AVX2__ 1
// CHECK_KNM_M64: #define __AVX512CD__ 1
// CHECK_KNM_M64: #define __AVX512ER__ 1
// CHECK_KNM_M64: #define __AVX512F__ 1
// CHECK_KNM_M64: #define __AVX512PF__ 1
[X86] Add avx512vpopcntdq to Knights Mill As indicated by Table 1-1 in Intel Architecture Instruction Set Extensions and Future Features Programming Reference from October 2017. llvm-svn: 316593
2017-10-26 01:10:58 +08:00
// CHECK_KNM_M64: #define __AVX512VPOPCNTDQ__ 1
[X86] Add skeleton support for knm cpu This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation. Differential Revision: https://reviews.llvm.org/D38813 llvm-svn: 315723
2017-10-14 02:14:24 +08:00
// CHECK_KNM_M64: #define __AVX__ 1
// CHECK_KNM_M64: #define __BMI2__ 1
// CHECK_KNM_M64: #define __BMI__ 1
// CHECK_KNM_M64: #define __F16C__ 1
// CHECK_KNM_M64: #define __FMA__ 1
// CHECK_KNM_M64: #define __LZCNT__ 1
// CHECK_KNM_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_KNM_M64: #define __MOVBE__ 1
[X86] Add skeleton support for knm cpu This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation. Differential Revision: https://reviews.llvm.org/D38813 llvm-svn: 315723
2017-10-14 02:14:24 +08:00
// CHECK_KNM_M64: #define __PCLMUL__ 1
// CHECK_KNM_M64: #define __POPCNT__ 1
// CHECK_KNM_M64: #define __PREFETCHWT1__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_KNM_M64: #define __PRFCHW__ 1
[X86] Add skeleton support for knm cpu This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation. Differential Revision: https://reviews.llvm.org/D38813 llvm-svn: 315723
2017-10-14 02:14:24 +08:00
// CHECK_KNM_M64: #define __RDRND__ 1
// CHECK_KNM_M64: #define __SSE2_MATH__ 1
// CHECK_KNM_M64: #define __SSE2__ 1
// CHECK_KNM_M64: #define __SSE3__ 1
// CHECK_KNM_M64: #define __SSE4_1__ 1
// CHECK_KNM_M64: #define __SSE4_2__ 1
// CHECK_KNM_M64: #define __SSE_MATH__ 1
// CHECK_KNM_M64: #define __SSE__ 1
// CHECK_KNM_M64: #define __SSSE3__ 1
// CHECK_KNM_M64: #define __XSAVEOPT__ 1
// CHECK_KNM_M64: #define __XSAVE__ 1
// CHECK_KNM_M64: #define __amd64 1
// CHECK_KNM_M64: #define __amd64__ 1
// CHECK_KNM_M64: #define __x86_64 1
// CHECK_KNM_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// RUN: %clang -march=skylake-avx512 -m32 -E -dM %s -o - 2>&1 \
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SKX_M32
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M32: #define __AES__ 1
// CHECK_SKX_M32: #define __AVX2__ 1
// CHECK_SKX_M32: #define __AVX512BW__ 1
// CHECK_SKX_M32: #define __AVX512CD__ 1
// CHECK_SKX_M32: #define __AVX512DQ__ 1
// CHECK_SKX_M32: #define __AVX512F__ 1
// CHECK_SKX_M32: #define __AVX512VL__ 1
// CHECK_SKX_M32: #define __AVX__ 1
// CHECK_SKX_M32: #define __BMI2__ 1
// CHECK_SKX_M32: #define __BMI__ 1
[X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
2017-02-08 14:48:58 +08:00
// CHECK_SKX_M32: #define __CLFLUSHOPT__ 1
[X86] Add -mclwb/-mno-clwb command line arguments and __CLWB__ define to match gcc. In the future, we should also add a clwb intrinsic to the backend, a frontend builtin, and an instrinsic header file. llvm-svn: 294416
2017-02-08 15:36:58 +08:00
// CHECK_SKX_M32: #define __CLWB__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M32: #define __F16C__ 1
// CHECK_SKX_M32: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_SKX_M32: #define __INVPCID__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M32: #define __LZCNT__ 1
// CHECK_SKX_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_SKX_M32: #define __MOVBE__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M32: #define __PCLMUL__ 1
[X86] Test that -march=skx enables PKU. llvm-svn: 321503
2017-12-28 06:26:00 +08:00
// CHECK_SKX_M32: #define __PKU__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M32: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_SKX_M32: #define __PRFCHW__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M32: #define __RDRND__ 1
[X86] Add missing check for RDSEED to ICL, CNL, SKX sections of test/Preprocessor/predefined-arch-macros.c llvm-svn: 322912
2018-01-19 08:28:42 +08:00
// CHECK_SKX_M32: #define __RDSEED__ 1
[X86] Disable SGX for Skylake Server - CPP test Summary: Fix test case - corresponding to r329701 Reviewers: craig.topper, davezarzycki Reviewed By: davezarzycki Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45488 llvm-svn: 329710
2018-04-10 23:03:03 +08:00
// CHECK_SKX_M32-NOT: #define __SGX__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M32: #define __SSE2__ 1
// CHECK_SKX_M32: #define __SSE3__ 1
// CHECK_SKX_M32: #define __SSE4_1__ 1
// CHECK_SKX_M32: #define __SSE4_2__ 1
// CHECK_SKX_M32: #define __SSE__ 1
// CHECK_SKX_M32: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_SKX_M32: #define __XSAVEC__ 1
// CHECK_SKX_M32: #define __XSAVEOPT__ 1
// CHECK_SKX_M32: #define __XSAVES__ 1
// CHECK_SKX_M32: #define __XSAVE__ 1
[X86] Set __corei7__ preprocessor defines for skylake server and cannonlake. This is the resolution we came to in D38824. llvm-svn: 318616
2017-11-19 10:55:14 +08:00
// CHECK_SKX_M32: #define __corei7 1
// CHECK_SKX_M32: #define __corei7__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M32: #define __i386 1
// CHECK_SKX_M32: #define __i386__ 1
[X86] Set __corei7__ preprocessor defines for skylake server and cannonlake. This is the resolution we came to in D38824. llvm-svn: 318616
2017-11-19 10:55:14 +08:00
// CHECK_SKX_M32: #define __tune_corei7__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M32: #define i386 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// RUN: %clang -march=skylake-avx512 -m64 -E -dM %s -o - 2>&1 \
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SKX_M64
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M64: #define __AES__ 1
// CHECK_SKX_M64: #define __AVX2__ 1
// CHECK_SKX_M64: #define __AVX512BW__ 1
// CHECK_SKX_M64: #define __AVX512CD__ 1
// CHECK_SKX_M64: #define __AVX512DQ__ 1
// CHECK_SKX_M64: #define __AVX512F__ 1
// CHECK_SKX_M64: #define __AVX512VL__ 1
// CHECK_SKX_M64: #define __AVX__ 1
// CHECK_SKX_M64: #define __BMI2__ 1
// CHECK_SKX_M64: #define __BMI__ 1
[X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
2017-02-08 14:48:58 +08:00
// CHECK_SKX_M64: #define __CLFLUSHOPT__ 1
[X86] Add -mclwb/-mno-clwb command line arguments and __CLWB__ define to match gcc. In the future, we should also add a clwb intrinsic to the backend, a frontend builtin, and an instrinsic header file. llvm-svn: 294416
2017-02-08 15:36:58 +08:00
// CHECK_SKX_M64: #define __CLWB__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M64: #define __F16C__ 1
// CHECK_SKX_M64: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_SKX_M64: #define __INVPCID__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M64: #define __LZCNT__ 1
// CHECK_SKX_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_SKX_M64: #define __MOVBE__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M64: #define __PCLMUL__ 1
[X86] Test that -march=skx enables PKU. llvm-svn: 321503
2017-12-28 06:26:00 +08:00
// CHECK_SKX_M64: #define __PKU__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M64: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_SKX_M64: #define __PRFCHW__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M64: #define __RDRND__ 1
[X86] Add missing check for RDSEED to ICL, CNL, SKX sections of test/Preprocessor/predefined-arch-macros.c llvm-svn: 322912
2018-01-19 08:28:42 +08:00
// CHECK_SKX_M64: #define __RDSEED__ 1
[X86] Disable SGX for Skylake Server - CPP test Summary: Fix test case - corresponding to r329701 Reviewers: craig.topper, davezarzycki Reviewed By: davezarzycki Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45488 llvm-svn: 329710
2018-04-10 23:03:03 +08:00
// CHECK_SKX_M64-NOT: #define __SGX__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M64: #define __SSE2_MATH__ 1
// CHECK_SKX_M64: #define __SSE2__ 1
// CHECK_SKX_M64: #define __SSE3__ 1
// CHECK_SKX_M64: #define __SSE4_1__ 1
// CHECK_SKX_M64: #define __SSE4_2__ 1
// CHECK_SKX_M64: #define __SSE_MATH__ 1
// CHECK_SKX_M64: #define __SSE__ 1
// CHECK_SKX_M64: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_SKX_M64: #define __XSAVEC__ 1
// CHECK_SKX_M64: #define __XSAVEOPT__ 1
// CHECK_SKX_M64: #define __XSAVES__ 1
// CHECK_SKX_M64: #define __XSAVE__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M64: #define __amd64 1
// CHECK_SKX_M64: #define __amd64__ 1
[X86] Set __corei7__ preprocessor defines for skylake server and cannonlake. This is the resolution we came to in D38824. llvm-svn: 318616
2017-11-19 10:55:14 +08:00
// CHECK_SKX_M64: #define __corei7 1
// CHECK_SKX_M64: #define __corei7__ 1
// CHECK_SKX_M64: #define __tune_corei7__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// CHECK_SKX_M64: #define __x86_64 1
// CHECK_SKX_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[X86] Add -march=cascadelake support in clang. This is skylake-avx512 with the addition of avx512vnni ISA. Patch by Jianping Chen Differential Revision: https://reviews.llvm.org/D54792 llvm-svn: 347682
2018-11-28 02:05:14 +08:00
// RUN: %clang -march=cascadelake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CLX_M32
// CHECK_CLX_M32: #define __AES__ 1
// CHECK_CLX_M32: #define __AVX2__ 1
// CHECK_CLX_M32: #define __AVX512BW__ 1
// CHECK_CLX_M32: #define __AVX512CD__ 1
// CHECK_CLX_M32: #define __AVX512DQ__ 1
// CHECK_CLX_M32: #define __AVX512F__ 1
// CHECK_CLX_M32: #define __AVX512VL__ 1
// CHECK_CLX_M32: #define __AVX512VNNI__ 1
// CHECK_CLX_M32: #define __AVX__ 1
// CHECK_CLX_M32: #define __BMI2__ 1
// CHECK_CLX_M32: #define __BMI__ 1
// CHECK_CLX_M32: #define __CLFLUSHOPT__ 1
// CHECK_CLX_M32: #define __CLWB__ 1
// CHECK_CLX_M32: #define __F16C__ 1
// CHECK_CLX_M32: #define __FMA__ 1
// CHECK_CLX_M32: #define __INVPCID__ 1
// CHECK_CLX_M32: #define __LZCNT__ 1
// CHECK_CLX_M32: #define __MMX__ 1
// CHECK_CLX_M32: #define __MOVBE__ 1
// CHECK_CLX_M32: #define __PCLMUL__ 1
// CHECK_CLX_M32: #define __PKU__ 1
// CHECK_CLX_M32: #define __POPCNT__ 1
// CHECK_CLX_M32: #define __PRFCHW__ 1
// CHECK_CLX_M32: #define __RDRND__ 1
// CHECK_CLX_M32: #define __RDSEED__ 1
// CHECK_CLX_M32-NOT: #define __SGX__ 1
// CHECK_CLX_M32: #define __SSE2__ 1
// CHECK_CLX_M32: #define __SSE3__ 1
// CHECK_CLX_M32: #define __SSE4_1__ 1
// CHECK_CLX_M32: #define __SSE4_2__ 1
// CHECK_CLX_M32: #define __SSE__ 1
// CHECK_CLX_M32: #define __SSSE3__ 1
// CHECK_CLX_M32: #define __XSAVEC__ 1
// CHECK_CLX_M32: #define __XSAVEOPT__ 1
// CHECK_CLX_M32: #define __XSAVES__ 1
// CHECK_CLX_M32: #define __XSAVE__ 1
// CHECK_CLX_M32: #define __corei7 1
// CHECK_CLX_M32: #define __corei7__ 1
// CHECK_CLX_M32: #define __i386 1
// CHECK_CLX_M32: #define __i386__ 1
// CHECK_CLX_M32: #define __tune_corei7__ 1
// CHECK_CLX_M32: #define i386 1
// RUN: %clang -march=cascadelake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CLX_M64
// CHECK_CLX_M64: #define __AES__ 1
// CHECK_CLX_M64: #define __AVX2__ 1
// CHECK_CLX_M64: #define __AVX512BW__ 1
// CHECK_CLX_M64: #define __AVX512CD__ 1
// CHECK_CLX_M64: #define __AVX512DQ__ 1
// CHECK_CLX_M64: #define __AVX512F__ 1
// CHECK_CLX_M64: #define __AVX512VL__ 1
// CHECK_CLX_M64: #define __AVX512VNNI__ 1
// CHECK_CLX_M64: #define __AVX__ 1
// CHECK_CLX_M64: #define __BMI2__ 1
// CHECK_CLX_M64: #define __BMI__ 1
// CHECK_CLX_M64: #define __CLFLUSHOPT__ 1
// CHECK_CLX_M64: #define __CLWB__ 1
// CHECK_CLX_M64: #define __F16C__ 1
// CHECK_CLX_M64: #define __FMA__ 1
// CHECK_CLX_M64: #define __INVPCID__ 1
// CHECK_CLX_M64: #define __LZCNT__ 1
// CHECK_CLX_M64: #define __MMX__ 1
// CHECK_CLX_M64: #define __MOVBE__ 1
// CHECK_CLX_M64: #define __PCLMUL__ 1
// CHECK_CLX_M64: #define __PKU__ 1
// CHECK_CLX_M64: #define __POPCNT__ 1
// CHECK_CLX_M64: #define __PRFCHW__ 1
// CHECK_CLX_M64: #define __RDRND__ 1
// CHECK_CLX_M64: #define __RDSEED__ 1
// CHECK_CLX_M64-NOT: #define __SGX__ 1
// CHECK_CLX_M64: #define __SSE2_MATH__ 1
// CHECK_CLX_M64: #define __SSE2__ 1
// CHECK_CLX_M64: #define __SSE3__ 1
// CHECK_CLX_M64: #define __SSE4_1__ 1
// CHECK_CLX_M64: #define __SSE4_2__ 1
// CHECK_CLX_M64: #define __SSE_MATH__ 1
// CHECK_CLX_M64: #define __SSE__ 1
// CHECK_CLX_M64: #define __SSSE3__ 1
// CHECK_CLX_M64: #define __XSAVEC__ 1
// CHECK_CLX_M64: #define __XSAVEOPT__ 1
// CHECK_CLX_M64: #define __XSAVES__ 1
// CHECK_CLX_M64: #define __XSAVE__ 1
// CHECK_CLX_M64: #define __amd64 1
// CHECK_CLX_M64: #define __amd64__ 1
// CHECK_CLX_M64: #define __corei7 1
// CHECK_CLX_M64: #define __corei7__ 1
// CHECK_CLX_M64: #define __tune_corei7__ 1
// CHECK_CLX_M64: #define __x86_64 1
// CHECK_CLX_M64: #define __x86_64__ 1
[X86] -march=cooperlake (clang) Support intel -march=cooperlake in clang Patch by Shengchen Kan (skan) Differential Revision: https://reviews.llvm.org/D62835 llvm-svn: 362781
2019-06-07 16:53:37 +08:00
// RUN: %clang -march=cooperlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CPX_M32
// CHECK_CPX_M32: #define __AES__ 1
// CHECK_CPX_M32: #define __AVX2__ 1
// CHECK_CPX_M32: #define __AVX512BF16__ 1
// CHECK_CPX_M32: #define __AVX512BW__ 1
// CHECK_CPX_M32: #define __AVX512CD__ 1
// CHECK_CPX_M32: #define __AVX512DQ__ 1
// CHECK_CPX_M32: #define __AVX512F__ 1
// CHECK_CPX_M32: #define __AVX512VL__ 1
// CHECK_CPX_M32: #define __AVX512VNNI__ 1
// CHECK_CPX_M32: #define __AVX__ 1
// CHECK_CPX_M32: #define __BMI2__ 1
// CHECK_CPX_M32: #define __BMI__ 1
// CHECK_CPX_M32: #define __CLFLUSHOPT__ 1
// CHECK_CPX_M32: #define __CLWB__ 1
// CHECK_CPX_M32: #define __F16C__ 1
// CHECK_CPX_M32: #define __FMA__ 1
// CHECK_CPX_M32: #define __INVPCID__ 1
// CHECK_CPX_M32: #define __LZCNT__ 1
// CHECK_CPX_M32: #define __MMX__ 1
// CHECK_CPX_M32: #define __MOVBE__ 1
// CHECK_CPX_M32: #define __PCLMUL__ 1
// CHECK_CPX_M32: #define __PKU__ 1
// CHECK_CPX_M32: #define __POPCNT__ 1
// CHECK_CPX_M32: #define __PRFCHW__ 1
// CHECK_CPX_M32: #define __RDRND__ 1
// CHECK_CPX_M32: #define __RDSEED__ 1
// CHECK_CPX_M32-NOT: #define __SGX__ 1
// CHECK_CPX_M32: #define __SSE2__ 1
// CHECK_CPX_M32: #define __SSE3__ 1
// CHECK_CPX_M32: #define __SSE4_1__ 1
// CHECK_CPX_M32: #define __SSE4_2__ 1
// CHECK_CPX_M32: #define __SSE__ 1
// CHECK_CPX_M32: #define __SSSE3__ 1
// CHECK_CPX_M32: #define __XSAVEC__ 1
// CHECK_CPX_M32: #define __XSAVEOPT__ 1
// CHECK_CPX_M32: #define __XSAVES__ 1
// CHECK_CPX_M32: #define __XSAVE__ 1
// CHECK_CPX_M32: #define __corei7 1
// CHECK_CPX_M32: #define __corei7__ 1
// CHECK_CPX_M32: #define __i386 1
// CHECK_CPX_M32: #define __i386__ 1
// CHECK_CPX_M32: #define __tune_corei7__ 1
// CHECK_CPX_M32: #define i386 1
// RUN: %clang -march=cooperlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CPX_M64
// CHECK_CPX_M64: #define __AES__ 1
// CHECK_CPX_M64: #define __AVX2__ 1
// CHECK_CPX_M64: #define __AVX512BF16__ 1
// CHECK_CPX_M64: #define __AVX512BW__ 1
// CHECK_CPX_M64: #define __AVX512CD__ 1
// CHECK_CPX_M64: #define __AVX512DQ__ 1
// CHECK_CPX_M64: #define __AVX512F__ 1
// CHECK_CPX_M64: #define __AVX512VL__ 1
// CHECK_CPX_M64: #define __AVX512VNNI__ 1
// CHECK_CPX_M64: #define __AVX__ 1
// CHECK_CPX_M64: #define __BMI2__ 1
// CHECK_CPX_M64: #define __BMI__ 1
// CHECK_CPX_M64: #define __CLFLUSHOPT__ 1
// CHECK_CPX_M64: #define __CLWB__ 1
// CHECK_CPX_M64: #define __F16C__ 1
// CHECK_CPX_M64: #define __FMA__ 1
// CHECK_CPX_M64: #define __INVPCID__ 1
// CHECK_CPX_M64: #define __LZCNT__ 1
// CHECK_CPX_M64: #define __MMX__ 1
// CHECK_CPX_M64: #define __MOVBE__ 1
// CHECK_CPX_M64: #define __PCLMUL__ 1
// CHECK_CPX_M64: #define __PKU__ 1
// CHECK_CPX_M64: #define __POPCNT__ 1
// CHECK_CPX_M64: #define __PRFCHW__ 1
// CHECK_CPX_M64: #define __RDRND__ 1
// CHECK_CPX_M64: #define __RDSEED__ 1
// CHECK_CPX_M64-NOT: #define __SGX__ 1
// CHECK_CPX_M64: #define __SSE2_MATH__ 1
// CHECK_CPX_M64: #define __SSE2__ 1
// CHECK_CPX_M64: #define __SSE3__ 1
// CHECK_CPX_M64: #define __SSE4_1__ 1
// CHECK_CPX_M64: #define __SSE4_2__ 1
// CHECK_CPX_M64: #define __SSE_MATH__ 1
// CHECK_CPX_M64: #define __SSE__ 1
// CHECK_CPX_M64: #define __SSSE3__ 1
// CHECK_CPX_M64: #define __XSAVEC__ 1
// CHECK_CPX_M64: #define __XSAVEOPT__ 1
// CHECK_CPX_M64: #define __XSAVES__ 1
// CHECK_CPX_M64: #define __XSAVE__ 1
// CHECK_CPX_M64: #define __amd64 1
// CHECK_CPX_M64: #define __amd64__ 1
// CHECK_CPX_M64: #define __corei7 1
// CHECK_CPX_M64: #define __corei7__ 1
// CHECK_CPX_M64: #define __tune_corei7__ 1
// CHECK_CPX_M64: #define __x86_64 1
// CHECK_CPX_M64: #define __x86_64__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// RUN: %clang -march=cannonlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CNL_M32
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define __AES__ 1
// CHECK_CNL_M32: #define __AVX2__ 1
// CHECK_CNL_M32: #define __AVX512BW__ 1
// CHECK_CNL_M32: #define __AVX512CD__ 1
// CHECK_CNL_M32: #define __AVX512DQ__ 1
// CHECK_CNL_M32: #define __AVX512F__ 1
[X86] Disabling avx512f should also disable avx512vbmi and avx512ifma. Enabling avx512vbmi or avx512ifma should enable avx512f. Add command line switches and header defines for avx512ifma and avx512vbmi. llvm-svn: 262201
2016-02-29 14:51:38 +08:00
// CHECK_CNL_M32: #define __AVX512IFMA__ 1
// CHECK_CNL_M32: #define __AVX512VBMI__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define __AVX512VL__ 1
// CHECK_CNL_M32: #define __AVX__ 1
// CHECK_CNL_M32: #define __BMI2__ 1
// CHECK_CNL_M32: #define __BMI__ 1
[X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
2017-02-08 14:48:58 +08:00
// CHECK_CNL_M32: #define __CLFLUSHOPT__ 1
[X86] Disable CLWB in Cannon Lake Cannon Lake does not support CLWB, therefore it does not include all features listed under SKX. Patch by Gabor Buella Differential Revision: https://reviews.llvm.org/D43459 llvm-svn: 325655
2018-02-21 08:16:50 +08:00
// CHECK_CNL_M32-NOT: #define __CLWB__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define __F16C__ 1
// CHECK_CNL_M32: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_CNL_M32: #define __INVPCID__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define __LZCNT__ 1
// CHECK_CNL_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_CNL_M32: #define __MOVBE__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define __PCLMUL__ 1
Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake." I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Which specifically said CLWB wasn't until Icelake. But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe. I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing. llvm-svn: 321547
2017-12-29 14:39:16 +08:00
// CHECK_CNL_M32: #define __PKU__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_CNL_M32: #define __PRFCHW__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define __RDRND__ 1
[X86] Add missing check for RDSEED to ICL, CNL, SKX sections of test/Preprocessor/predefined-arch-macros.c llvm-svn: 322912
2018-01-19 08:28:42 +08:00
// CHECK_CNL_M32: #define __RDSEED__ 1
[X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc. llvm-svn: 294423
2017-02-08 16:23:17 +08:00
// CHECK_CNL_M32: #define __SGX__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define __SHA__ 1
// CHECK_CNL_M32: #define __SSE2__ 1
// CHECK_CNL_M32: #define __SSE3__ 1
// CHECK_CNL_M32: #define __SSE4_1__ 1
// CHECK_CNL_M32: #define __SSE4_2__ 1
// CHECK_CNL_M32: #define __SSE__ 1
// CHECK_CNL_M32: #define __SSSE3__ 1
// CHECK_CNL_M32: #define __XSAVEC__ 1
// CHECK_CNL_M32: #define __XSAVEOPT__ 1
// CHECK_CNL_M32: #define __XSAVES__ 1
// CHECK_CNL_M32: #define __XSAVE__ 1
[X86] Set __corei7__ preprocessor defines for skylake server and cannonlake. This is the resolution we came to in D38824. llvm-svn: 318616
2017-11-19 10:55:14 +08:00
// CHECK_CNL_M32: #define __corei7 1
// CHECK_CNL_M32: #define __corei7__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define __i386 1
// CHECK_CNL_M32: #define __i386__ 1
[X86] Set __corei7__ preprocessor defines for skylake server and cannonlake. This is the resolution we came to in D38824. llvm-svn: 318616
2017-11-19 10:55:14 +08:00
// CHECK_CNL_M32: #define __tune_corei7__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// RUN: %clang -march=cannonlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CNL_M64
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __AES__ 1
// CHECK_CNL_M64: #define __AVX2__ 1
// CHECK_CNL_M64: #define __AVX512BW__ 1
// CHECK_CNL_M64: #define __AVX512CD__ 1
// CHECK_CNL_M64: #define __AVX512DQ__ 1
// CHECK_CNL_M64: #define __AVX512F__ 1
[X86] Disabling avx512f should also disable avx512vbmi and avx512ifma. Enabling avx512vbmi or avx512ifma should enable avx512f. Add command line switches and header defines for avx512ifma and avx512vbmi. llvm-svn: 262201
2016-02-29 14:51:38 +08:00
// CHECK_CNL_M64: #define __AVX512IFMA__ 1
// CHECK_CNL_M64: #define __AVX512VBMI__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __AVX512VL__ 1
// CHECK_CNL_M64: #define __AVX__ 1
// CHECK_CNL_M64: #define __BMI2__ 1
// CHECK_CNL_M64: #define __BMI__ 1
[X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
2017-02-08 14:48:58 +08:00
// CHECK_CNL_M64: #define __CLFLUSHOPT__ 1
[X86] Disable CLWB in Cannon Lake Cannon Lake does not support CLWB, therefore it does not include all features listed under SKX. Patch by Gabor Buella Differential Revision: https://reviews.llvm.org/D43459 llvm-svn: 325655
2018-02-21 08:16:50 +08:00
// CHECK_CNL_M64-NOT: #define __CLWB__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __F16C__ 1
// CHECK_CNL_M64: #define __FMA__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_CNL_M64: #define __INVPCID__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __LZCNT__ 1
// CHECK_CNL_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_CNL_M64: #define __MOVBE__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __PCLMUL__ 1
Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake." I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Which specifically said CLWB wasn't until Icelake. But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe. I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing. llvm-svn: 321547
2017-12-29 14:39:16 +08:00
// CHECK_CNL_M64: #define __PKU__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_CNL_M64: #define __PRFCHW__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __RDRND__ 1
[X86] Add missing check for RDSEED to ICL, CNL, SKX sections of test/Preprocessor/predefined-arch-macros.c llvm-svn: 322912
2018-01-19 08:28:42 +08:00
// CHECK_CNL_M64: #define __RDSEED__ 1
[X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc. llvm-svn: 294423
2017-02-08 16:23:17 +08:00
// CHECK_CNL_M64: #define __SGX__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __SHA__ 1
// CHECK_CNL_M64: #define __SSE2__ 1
// CHECK_CNL_M64: #define __SSE3__ 1
// CHECK_CNL_M64: #define __SSE4_1__ 1
// CHECK_CNL_M64: #define __SSE4_2__ 1
// CHECK_CNL_M64: #define __SSE__ 1
// CHECK_CNL_M64: #define __SSSE3__ 1
// CHECK_CNL_M64: #define __XSAVEC__ 1
// CHECK_CNL_M64: #define __XSAVEOPT__ 1
// CHECK_CNL_M64: #define __XSAVES__ 1
// CHECK_CNL_M64: #define __XSAVE__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// CHECK_CNL_M64: #define __amd64 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __amd64__ 1
[X86] Set __corei7__ preprocessor defines for skylake server and cannonlake. This is the resolution we came to in D38824. llvm-svn: 318616
2017-11-19 10:55:14 +08:00
// CHECK_CNL_M64: #define __corei7 1
// CHECK_CNL_M64: #define __corei7__ 1
// CHECK_CNL_M64: #define __tune_corei7__ 1
Added SKL and CNL processors and features to Clang Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
2016-02-21 15:41:23 +08:00
// CHECK_CNL_M64: #define __x86_64 1
// CHECK_CNL_M64: #define __x86_64__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// RUN: %clang -march=icelake-client -m32 -E -dM %s -o - 2>&1 \
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// RUN: -target i386-unknown-linux \
[X86] Support -march=rocketlake Reviewed By: skan, craig.topper, MaskRay Differential Revision: https://reviews.llvm.org/D100085
2021-04-13 09:24:34 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M32,CHECK_ICL_M32S
// RUN: %clang -march=rocketlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M32,CHECK_RKL_M32S
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __AES__ 1
// CHECK_ICL_M32: #define __AVX2__ 1
[x86][icelake][bitalg] added bitalg feature recognition added intrinsics support for bitalg instructions _mm512_popcnt_epi16 _mm512_mask_popcnt_epi16 _mm512_maskz_popcnt_epi16 _mm512_popcnt_epi8 _mm512_mask_popcnt_epi8 _mm512_maskz_popcnt_epi8 _mm512_mask_bitshuffle_epi64_mask _mm512_bitshuffle_epi64_mask _mm256_popcnt_epi16 _mm256_mask_popcnt_epi16 _mm256_maskz_popcnt_epi16 _mm128_popcnt_epi16 _mm128_mask_popcnt_epi16 _mm128_maskz_popcnt_epi16 _mm256_popcnt_epi8 _mm256_mask_popcnt_epi8 _mm256_maskz_popcnt_epi8 _mm128_popcnt_epi8 _mm128_mask_popcnt_epi8 _mm128_maskz_popcnt_epi8 _mm256_mask_bitshuffle_epi32_mask _mm256_bitshuffle_epi32_mask _mm128_mask_bitshuffle_epi16_mask _mm128_bitshuffle_epi16_mask matching a similar work on the backend (D40222) Differential Revision: https://reviews.llvm.org/D41564 llvm-svn: 321483
2017-12-27 18:01:00 +08:00
// CHECK_ICL_M32: #define __AVX512BITALG__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __AVX512BW__ 1
// CHECK_ICL_M32: #define __AVX512CD__ 1
// CHECK_ICL_M32: #define __AVX512DQ__ 1
// CHECK_ICL_M32: #define __AVX512F__ 1
// CHECK_ICL_M32: #define __AVX512IFMA__ 1
[x86][icelake][vbmi2] added vbmi2 feature recognition added intrinsics support for vbmi2 instructions _mm[128,256,512]_mask[z]_compress_epi[16,32] _mm[128,256,512]_mask_compressstoreu_epi[16,32] _mm[128,256,512]_mask[z]_expand_epi[16,32] _mm[128,256,512]_mask[z]_expandloadu_epi[16,32] _mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64] _mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64] matching a similar work on the backend (D40206) Differential Revision: https://reviews.llvm.org/D41557 llvm-svn: 321487
2017-12-27 19:25:07 +08:00
// CHECK_ICL_M32: #define __AVX512VBMI2__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __AVX512VBMI__ 1
// CHECK_ICL_M32: #define __AVX512VL__ 1
[x86][icelake][vnni] added vnni feature recognition added intrinsics support for VNNI instructions _mm256_mask_dpbusd_epi32 _mm256_maskz_dpbusd_epi32 _mm256_dpbusd_epi32 _mm256_mask_dpbusds_epi32 _mm256_maskz_dpbusds_epi32 _mm256_dpbusds_epi32 _mm256_mask_dpwssd_epi32 _mm256_maskz_dpwssd_epi32 _mm256_dpwssd_epi32 _mm256_mask_dpwssds_epi32 _mm256_maskz_dpwssds_epi32 _mm256_dpwssds_epi32 _mm128_mask_dpbusd_epi32 _mm128_maskz_dpbusd_epi32 _mm128_dpbusd_epi32 _mm128_mask_dpbusds_epi32 _mm128_maskz_dpbusds_epi32 _mm128_dpbusds_epi32 _mm128_mask_dpwssd_epi32 _mm128_maskz_dpwssd_epi32 _mm128_dpwssd_epi32 _mm128_mask_dpwssds_epi32 _mm128_maskz_dpwssds_epi32 _mm128_dpwssds_epi32 _mm512_mask_dpbusd_epi32 _mm512_maskz_dpbusd_epi32 _mm512_dpbusd_epi32 _mm512_mask_dpbusds_epi32 _mm512_maskz_dpbusds_epi32 _mm512_dpbusds_epi32 _mm512_mask_dpwssd_epi32 _mm512_maskz_dpwssd_epi32 _mm512_dpwssd_epi32 _mm512_mask_dpwssds_epi32 _mm512_maskz_dpwssds_epi32 _mm512_dpwssds_epi32 matching a similar work on the backend (D40208) Differential Revision: https://reviews.llvm.org/D41558 llvm-svn: 321484
2017-12-27 18:37:51 +08:00
// CHECK_ICL_M32: #define __AVX512VNNI__ 1
[X86] Enable avx512vpopcntdq and clwb for icelake. Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference llvm-svn: 321502
2017-12-28 06:25:59 +08:00
// CHECK_ICL_M32: #define __AVX512VPOPCNTDQ__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __AVX__ 1
// CHECK_ICL_M32: #define __BMI2__ 1
// CHECK_ICL_M32: #define __BMI__ 1
// CHECK_ICL_M32: #define __CLFLUSHOPT__ 1
[X86] Remove FeatureCLWB from FeaturesICLClient Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D100279
2021-04-12 10:36:08 +08:00
// CHECK_ICL_M32-NOT: #define __CLWB__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __F16C__ 1
// CHECK_ICL_M32: #define __FMA__ 1
[x86][icelake][gfni] added gfni feature recognition added intrinsics support for gfni instructions _mm_gf2p8affineinv_epi64_epi8 _mm_mask_gf2p8affineinv_epi64_epi8 _mm_maskz_gf2p8affineinv_epi64_epi8 _mm256_gf2p8affineinv_epi64_epi8 _mm256_mask_gf2p8affineinv_epi64_epi8 _mm256_maskz_gf2p8affineinv_epi64_epi8 _mm512_gf2p8affineinv_epi64_epi8 _mm512_mask_gf2p8affineinv_epi64_epi8 _mm512_maskz_gf2p8affineinv_epi64_epi8 _mm_gf2p8affine_epi64_epi8 _mm_mask_gf2p8affine_epi64_epi8 _mm_maskz_gf2p8affine_epi64_epi8 _mm256_gf2p8affine_epi64_epi8 _mm256_mask_gf2p8affine_epi64_epi8 _mm256_maskz_gf2p8affine_epi64_epi8 _mm512_gf2p8affine_epi64_epi8 _mm512_mask_gf2p8affine_epi64_epi8 _mm512_maskz_gf2p8affine_epi64_epi8 _mm_gf2p8mul_epi8 _mm_mask_gf2p8mul_epi8 _mm_maskz_gf2p8mul_epi8 _mm256_gf2p8mul_epi8 _mm256_mask_gf2p8mul_epi8 _mm256_maskz_gf2p8mul_epi8 _mm512_gf2p8mul_epi8 _mm512_mask_gf2p8mul_epi8 _mm512_maskz_gf2p8mul_epi8 matching a similar work on the backend (D40373) Differential Revision: https://reviews.llvm.org/D41582 llvm-svn: 321477
2017-12-27 16:37:47 +08:00
// CHECK_ICL_M32: #define __GFNI__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_ICL_M32: #define __INVPCID__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __LZCNT__ 1
// CHECK_ICL_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_ICL_M32: #define __MOVBE__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __PCLMUL__ 1
Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake." I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Which specifically said CLWB wasn't until Icelake. But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe. I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing. llvm-svn: 321547
2017-12-29 14:39:16 +08:00
// CHECK_ICL_M32: #define __PKU__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_ICL_M32: #define __PRFCHW__ 1
[X86] Add rdpid command line option and intrinsics. Summary: This patch adds -mrdpid/-mno-rdpid and the rdpid intrinsic. The corresponding LLVM commit has already been made. Reviewers: RKSimon, spatel, zvi, AndreiGrischenko Reviewed By: RKSimon Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D42272 llvm-svn: 323047
2018-01-21 02:36:52 +08:00
// CHECK_ICL_M32: #define __RDPID__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __RDRND__ 1
[X86] Add missing check for RDSEED to ICL, CNL, SKX sections of test/Preprocessor/predefined-arch-macros.c llvm-svn: 322912
2018-01-19 08:28:42 +08:00
// CHECK_ICL_M32: #define __RDSEED__ 1
[X86] Support -march=rocketlake Reviewed By: skan, craig.topper, MaskRay Differential Revision: https://reviews.llvm.org/D100085
2021-04-13 09:24:34 +08:00
// CHECK_ICL_M32S: #define __SGX__ 1
// CHECK_RKL_M32S-NOT: #define __SGX__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __SHA__ 1
// CHECK_ICL_M32: #define __SSE2__ 1
// CHECK_ICL_M32: #define __SSE3__ 1
// CHECK_ICL_M32: #define __SSE4_1__ 1
// CHECK_ICL_M32: #define __SSE4_2__ 1
// CHECK_ICL_M32: #define __SSE__ 1
// CHECK_ICL_M32: #define __SSSE3__ 1
[x86][icelake][vaes] added vaes feature recognition added intrinsics support for vaes instructions, matching a similar work on the backend (D40078) _mm256_aesenc_epi128 _mm512_aesenc_epi128 _mm256_aesenclast_epi128 _mm512_aesenclast_epi128 _mm256_aesdec_epi128 _mm512_aesdec_epi128 _mm256_aesdeclast_epi128 _mm512_aesdeclast_epi128 llvm-svn: 321474
2017-12-27 16:16:54 +08:00
// CHECK_ICL_M32: #define __VAES__ 1
[x86][icelake][vpclmulqdq] added vpclmulqdq feature recognition added intrinsics support for vpclmulqdq instructions _mm256_clmulepi64_epi128 _mm512_clmulepi64_epi128 matching a similar work on the backend (D40101) Differential Revision: https://reviews.llvm.org/D41573 llvm-svn: 321480
2017-12-27 17:00:31 +08:00
// CHECK_ICL_M32: #define __VPCLMULQDQ__ 1
[x86] wbnoinvd intrinsic The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory but does not invalidate (flush) the internal caches. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43817 llvm-svn: 329848
2018-04-12 04:09:09 +08:00
// CHECK_ICL_M32-NOT: #define __WBNOINVD__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M32: #define __XSAVEC__ 1
// CHECK_ICL_M32: #define __XSAVEOPT__ 1
// CHECK_ICL_M32: #define __XSAVES__ 1
// CHECK_ICL_M32: #define __XSAVE__ 1
// CHECK_ICL_M32: #define __corei7 1
// CHECK_ICL_M32: #define __corei7__ 1
// CHECK_ICL_M32: #define __i386 1
// CHECK_ICL_M32: #define __i386__ 1
// CHECK_ICL_M32: #define __tune_corei7__ 1
// CHECK_ICL_M32: #define i386 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// RUN: %clang -march=icelake-client -m64 -E -dM %s -o - 2>&1 \
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// RUN: -target i386-unknown-linux \
[X86] Support -march=rocketlake Reviewed By: skan, craig.topper, MaskRay Differential Revision: https://reviews.llvm.org/D100085
2021-04-13 09:24:34 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M64,CHECK_ICL_M64S
// RUN: %clang -march=rocketlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M64,CHECK_RKL_M64S
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __AES__ 1
// CHECK_ICL_M64: #define __AVX2__ 1
[x86][icelake][bitalg] added bitalg feature recognition added intrinsics support for bitalg instructions _mm512_popcnt_epi16 _mm512_mask_popcnt_epi16 _mm512_maskz_popcnt_epi16 _mm512_popcnt_epi8 _mm512_mask_popcnt_epi8 _mm512_maskz_popcnt_epi8 _mm512_mask_bitshuffle_epi64_mask _mm512_bitshuffle_epi64_mask _mm256_popcnt_epi16 _mm256_mask_popcnt_epi16 _mm256_maskz_popcnt_epi16 _mm128_popcnt_epi16 _mm128_mask_popcnt_epi16 _mm128_maskz_popcnt_epi16 _mm256_popcnt_epi8 _mm256_mask_popcnt_epi8 _mm256_maskz_popcnt_epi8 _mm128_popcnt_epi8 _mm128_mask_popcnt_epi8 _mm128_maskz_popcnt_epi8 _mm256_mask_bitshuffle_epi32_mask _mm256_bitshuffle_epi32_mask _mm128_mask_bitshuffle_epi16_mask _mm128_bitshuffle_epi16_mask matching a similar work on the backend (D40222) Differential Revision: https://reviews.llvm.org/D41564 llvm-svn: 321483
2017-12-27 18:01:00 +08:00
// CHECK_ICL_M64: #define __AVX512BITALG__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __AVX512BW__ 1
// CHECK_ICL_M64: #define __AVX512CD__ 1
// CHECK_ICL_M64: #define __AVX512DQ__ 1
// CHECK_ICL_M64: #define __AVX512F__ 1
// CHECK_ICL_M64: #define __AVX512IFMA__ 1
[x86][icelake][vbmi2] added vbmi2 feature recognition added intrinsics support for vbmi2 instructions _mm[128,256,512]_mask[z]_compress_epi[16,32] _mm[128,256,512]_mask_compressstoreu_epi[16,32] _mm[128,256,512]_mask[z]_expand_epi[16,32] _mm[128,256,512]_mask[z]_expandloadu_epi[16,32] _mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64] _mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64] matching a similar work on the backend (D40206) Differential Revision: https://reviews.llvm.org/D41557 llvm-svn: 321487
2017-12-27 19:25:07 +08:00
// CHECK_ICL_M64: #define __AVX512VBMI2__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __AVX512VBMI__ 1
// CHECK_ICL_M64: #define __AVX512VL__ 1
[x86][icelake][vnni] added vnni feature recognition added intrinsics support for VNNI instructions _mm256_mask_dpbusd_epi32 _mm256_maskz_dpbusd_epi32 _mm256_dpbusd_epi32 _mm256_mask_dpbusds_epi32 _mm256_maskz_dpbusds_epi32 _mm256_dpbusds_epi32 _mm256_mask_dpwssd_epi32 _mm256_maskz_dpwssd_epi32 _mm256_dpwssd_epi32 _mm256_mask_dpwssds_epi32 _mm256_maskz_dpwssds_epi32 _mm256_dpwssds_epi32 _mm128_mask_dpbusd_epi32 _mm128_maskz_dpbusd_epi32 _mm128_dpbusd_epi32 _mm128_mask_dpbusds_epi32 _mm128_maskz_dpbusds_epi32 _mm128_dpbusds_epi32 _mm128_mask_dpwssd_epi32 _mm128_maskz_dpwssd_epi32 _mm128_dpwssd_epi32 _mm128_mask_dpwssds_epi32 _mm128_maskz_dpwssds_epi32 _mm128_dpwssds_epi32 _mm512_mask_dpbusd_epi32 _mm512_maskz_dpbusd_epi32 _mm512_dpbusd_epi32 _mm512_mask_dpbusds_epi32 _mm512_maskz_dpbusds_epi32 _mm512_dpbusds_epi32 _mm512_mask_dpwssd_epi32 _mm512_maskz_dpwssd_epi32 _mm512_dpwssd_epi32 _mm512_mask_dpwssds_epi32 _mm512_maskz_dpwssds_epi32 _mm512_dpwssds_epi32 matching a similar work on the backend (D40208) Differential Revision: https://reviews.llvm.org/D41558 llvm-svn: 321484
2017-12-27 18:37:51 +08:00
// CHECK_ICL_M64: #define __AVX512VNNI__ 1
[X86] Enable avx512vpopcntdq and clwb for icelake. Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference llvm-svn: 321502
2017-12-28 06:25:59 +08:00
// CHECK_ICL_M64: #define __AVX512VPOPCNTDQ__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __AVX__ 1
// CHECK_ICL_M64: #define __BMI2__ 1
// CHECK_ICL_M64: #define __BMI__ 1
// CHECK_ICL_M64: #define __CLFLUSHOPT__ 1
[X86] Remove FeatureCLWB from FeaturesICLClient Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D100279
2021-04-12 10:36:08 +08:00
// CHECK_ICL_M64-NOT: #define __CLWB__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __F16C__ 1
// CHECK_ICL_M64: #define __FMA__ 1
[x86][icelake][gfni] added gfni feature recognition added intrinsics support for gfni instructions _mm_gf2p8affineinv_epi64_epi8 _mm_mask_gf2p8affineinv_epi64_epi8 _mm_maskz_gf2p8affineinv_epi64_epi8 _mm256_gf2p8affineinv_epi64_epi8 _mm256_mask_gf2p8affineinv_epi64_epi8 _mm256_maskz_gf2p8affineinv_epi64_epi8 _mm512_gf2p8affineinv_epi64_epi8 _mm512_mask_gf2p8affineinv_epi64_epi8 _mm512_maskz_gf2p8affineinv_epi64_epi8 _mm_gf2p8affine_epi64_epi8 _mm_mask_gf2p8affine_epi64_epi8 _mm_maskz_gf2p8affine_epi64_epi8 _mm256_gf2p8affine_epi64_epi8 _mm256_mask_gf2p8affine_epi64_epi8 _mm256_maskz_gf2p8affine_epi64_epi8 _mm512_gf2p8affine_epi64_epi8 _mm512_mask_gf2p8affine_epi64_epi8 _mm512_maskz_gf2p8affine_epi64_epi8 _mm_gf2p8mul_epi8 _mm_mask_gf2p8mul_epi8 _mm_maskz_gf2p8mul_epi8 _mm256_gf2p8mul_epi8 _mm256_mask_gf2p8mul_epi8 _mm256_maskz_gf2p8mul_epi8 _mm512_gf2p8mul_epi8 _mm512_mask_gf2p8mul_epi8 _mm512_maskz_gf2p8mul_epi8 matching a similar work on the backend (D40373) Differential Revision: https://reviews.llvm.org/D41582 llvm-svn: 321477
2017-12-27 16:37:47 +08:00
// CHECK_ICL_M64: #define __GFNI__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_ICL_M64: #define __INVPCID__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __LZCNT__ 1
// CHECK_ICL_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_ICL_M64: #define __MOVBE__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __PCLMUL__ 1
Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake." I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Which specifically said CLWB wasn't until Icelake. But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe. I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing. llvm-svn: 321547
2017-12-29 14:39:16 +08:00
// CHECK_ICL_M64: #define __PKU__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_ICL_M64: #define __PRFCHW__ 1
[X86] Add rdpid command line option and intrinsics. Summary: This patch adds -mrdpid/-mno-rdpid and the rdpid intrinsic. The corresponding LLVM commit has already been made. Reviewers: RKSimon, spatel, zvi, AndreiGrischenko Reviewed By: RKSimon Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D42272 llvm-svn: 323047
2018-01-21 02:36:52 +08:00
// CHECK_ICL_M64: #define __RDPID__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __RDRND__ 1
[X86] Add missing check for RDSEED to ICL, CNL, SKX sections of test/Preprocessor/predefined-arch-macros.c llvm-svn: 322912
2018-01-19 08:28:42 +08:00
// CHECK_ICL_M64: #define __RDSEED__ 1
[X86] Support -march=rocketlake Reviewed By: skan, craig.topper, MaskRay Differential Revision: https://reviews.llvm.org/D100085
2021-04-13 09:24:34 +08:00
// CHECK_ICL_M64S: #define __SGX__ 1
// CHECK_RKL_M64S-NOT: #define __SGX__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __SHA__ 1
// CHECK_ICL_M64: #define __SSE2__ 1
// CHECK_ICL_M64: #define __SSE3__ 1
// CHECK_ICL_M64: #define __SSE4_1__ 1
// CHECK_ICL_M64: #define __SSE4_2__ 1
// CHECK_ICL_M64: #define __SSE__ 1
// CHECK_ICL_M64: #define __SSSE3__ 1
[x86][icelake][vaes] added vaes feature recognition added intrinsics support for vaes instructions, matching a similar work on the backend (D40078) _mm256_aesenc_epi128 _mm512_aesenc_epi128 _mm256_aesenclast_epi128 _mm512_aesenclast_epi128 _mm256_aesdec_epi128 _mm512_aesdec_epi128 _mm256_aesdeclast_epi128 _mm512_aesdeclast_epi128 llvm-svn: 321474
2017-12-27 16:16:54 +08:00
// CHECK_ICL_M64: #define __VAES__ 1
[x86][icelake][vpclmulqdq] added vpclmulqdq feature recognition added intrinsics support for vpclmulqdq instructions _mm256_clmulepi64_epi128 _mm512_clmulepi64_epi128 matching a similar work on the backend (D40101) Differential Revision: https://reviews.llvm.org/D41573 llvm-svn: 321480
2017-12-27 17:00:31 +08:00
// CHECK_ICL_M64: #define __VPCLMULQDQ__ 1
[x86] wbnoinvd intrinsic The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory but does not invalidate (flush) the internal caches. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43817 llvm-svn: 329848
2018-04-12 04:09:09 +08:00
// CHECK_ICL_M64-NOT: #define __WBNOINVD__ 1
[X86] Add icelake CPU support for -march. llvm-svn: 318617
2017-11-19 10:55:15 +08:00
// CHECK_ICL_M64: #define __XSAVEC__ 1
// CHECK_ICL_M64: #define __XSAVEOPT__ 1
// CHECK_ICL_M64: #define __XSAVES__ 1
// CHECK_ICL_M64: #define __XSAVE__ 1
// CHECK_ICL_M64: #define __amd64 1
// CHECK_ICL_M64: #define __amd64__ 1
// CHECK_ICL_M64: #define __corei7 1
// CHECK_ICL_M64: #define __corei7__ 1
// CHECK_ICL_M64: #define __tune_corei7__ 1
// CHECK_ICL_M64: #define __x86_64 1
// CHECK_ICL_M64: #define __x86_64__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// RUN: %clang -march=icelake-server -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICX_M32
// CHECK_ICX_M32: #define __AES__ 1
// CHECK_ICX_M32: #define __AVX2__ 1
// CHECK_ICX_M32: #define __AVX512BITALG__ 1
// CHECK_ICX_M32: #define __AVX512BW__ 1
// CHECK_ICX_M32: #define __AVX512CD__ 1
// CHECK_ICX_M32: #define __AVX512DQ__ 1
// CHECK_ICX_M32: #define __AVX512F__ 1
// CHECK_ICX_M32: #define __AVX512IFMA__ 1
// CHECK_ICX_M32: #define __AVX512VBMI2__ 1
// CHECK_ICX_M32: #define __AVX512VBMI__ 1
// CHECK_ICX_M32: #define __AVX512VL__ 1
// CHECK_ICX_M32: #define __AVX512VNNI__ 1
// CHECK_ICX_M32: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ICX_M32: #define __AVX__ 1
// CHECK_ICX_M32: #define __BMI2__ 1
// CHECK_ICX_M32: #define __BMI__ 1
// CHECK_ICX_M32: #define __CLFLUSHOPT__ 1
// CHECK_ICX_M32: #define __CLWB__ 1
// CHECK_ICX_M32: #define __F16C__ 1
// CHECK_ICX_M32: #define __FMA__ 1
// CHECK_ICX_M32: #define __GFNI__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_ICX_M32: #define __INVPCID__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// CHECK_ICX_M32: #define __LZCNT__ 1
// CHECK_ICX_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_ICX_M32: #define __MOVBE__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// CHECK_ICX_M32: #define __PCLMUL__ 1
[x86] Introduce the pconfig intrinsic Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46431 llvm-svn: 331740
2018-05-08 14:49:41 +08:00
// CHECK_ICX_M32: #define __PCONFIG__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// CHECK_ICX_M32: #define __PKU__ 1
// CHECK_ICX_M32: #define __POPCNT__ 1
// CHECK_ICX_M32: #define __PRFCHW__ 1
// CHECK_ICX_M32: #define __RDPID__ 1
// CHECK_ICX_M32: #define __RDRND__ 1
// CHECK_ICX_M32: #define __RDSEED__ 1
// CHECK_ICX_M32: #define __SGX__ 1
// CHECK_ICX_M32: #define __SHA__ 1
// CHECK_ICX_M32: #define __SSE2__ 1
// CHECK_ICX_M32: #define __SSE3__ 1
// CHECK_ICX_M32: #define __SSE4_1__ 1
// CHECK_ICX_M32: #define __SSE4_2__ 1
// CHECK_ICX_M32: #define __SSE__ 1
// CHECK_ICX_M32: #define __SSSE3__ 1
// CHECK_ICX_M32: #define __VAES__ 1
// CHECK_ICX_M32: #define __VPCLMULQDQ__ 1
[x86] wbnoinvd intrinsic The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory but does not invalidate (flush) the internal caches. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43817 llvm-svn: 329848
2018-04-12 04:09:09 +08:00
// CHECK_ICX_M32: #define __WBNOINVD__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// CHECK_ICX_M32: #define __XSAVEC__ 1
// CHECK_ICX_M32: #define __XSAVEOPT__ 1
// CHECK_ICX_M32: #define __XSAVES__ 1
// CHECK_ICX_M32: #define __XSAVE__ 1
// CHECK_ICX_M32: #define __corei7 1
// CHECK_ICX_M32: #define __corei7__ 1
// CHECK_ICX_M32: #define __i386 1
// CHECK_ICX_M32: #define __i386__ 1
// CHECK_ICX_M32: #define __tune_corei7__ 1
// CHECK_ICX_M32: #define i386 1
// RUN: %clang -march=icelake-server -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICX_M64
// CHECK_ICX_M64: #define __AES__ 1
// CHECK_ICX_M64: #define __AVX2__ 1
// CHECK_ICX_M64: #define __AVX512BITALG__ 1
// CHECK_ICX_M64: #define __AVX512BW__ 1
// CHECK_ICX_M64: #define __AVX512CD__ 1
// CHECK_ICX_M64: #define __AVX512DQ__ 1
// CHECK_ICX_M64: #define __AVX512F__ 1
// CHECK_ICX_M64: #define __AVX512IFMA__ 1
// CHECK_ICX_M64: #define __AVX512VBMI2__ 1
// CHECK_ICX_M64: #define __AVX512VBMI__ 1
// CHECK_ICX_M64: #define __AVX512VL__ 1
// CHECK_ICX_M64: #define __AVX512VNNI__ 1
// CHECK_ICX_M64: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ICX_M64: #define __AVX__ 1
// CHECK_ICX_M64: #define __BMI2__ 1
// CHECK_ICX_M64: #define __BMI__ 1
// CHECK_ICX_M64: #define __CLFLUSHOPT__ 1
// CHECK_ICX_M64: #define __CLWB__ 1
// CHECK_ICX_M64: #define __F16C__ 1
// CHECK_ICX_M64: #define __FMA__ 1
// CHECK_ICX_M64: #define __GFNI__ 1
[x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
2018-05-25 14:34:42 +08:00
// CHECK_ICX_M64: #define __INVPCID__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// CHECK_ICX_M64: #define __LZCNT__ 1
// CHECK_ICX_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_ICX_M64: #define __MOVBE__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// CHECK_ICX_M64: #define __PCLMUL__ 1
[x86] Introduce the pconfig intrinsic Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46431 llvm-svn: 331740
2018-05-08 14:49:41 +08:00
// CHECK_ICX_M64: #define __PCONFIG__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// CHECK_ICX_M64: #define __PKU__ 1
// CHECK_ICX_M64: #define __POPCNT__ 1
// CHECK_ICX_M64: #define __PRFCHW__ 1
// CHECK_ICX_M64: #define __RDPID__ 1
// CHECK_ICX_M64: #define __RDRND__ 1
// CHECK_ICX_M64: #define __RDSEED__ 1
// CHECK_ICX_M64: #define __SGX__ 1
// CHECK_ICX_M64: #define __SHA__ 1
// CHECK_ICX_M64: #define __SSE2__ 1
// CHECK_ICX_M64: #define __SSE3__ 1
// CHECK_ICX_M64: #define __SSE4_1__ 1
// CHECK_ICX_M64: #define __SSE4_2__ 1
// CHECK_ICX_M64: #define __SSE__ 1
// CHECK_ICX_M64: #define __SSSE3__ 1
// CHECK_ICX_M64: #define __VAES__ 1
// CHECK_ICX_M64: #define __VPCLMULQDQ__ 1
[x86] wbnoinvd intrinsic The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory but does not invalidate (flush) the internal caches. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43817 llvm-svn: 329848
2018-04-12 04:09:09 +08:00
// CHECK_ICX_M64: #define __WBNOINVD__ 1
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-11 02:58:26 +08:00
// CHECK_ICX_M64: #define __XSAVEC__ 1
// CHECK_ICX_M64: #define __XSAVEOPT__ 1
// CHECK_ICX_M64: #define __XSAVES__ 1
// CHECK_ICX_M64: #define __XSAVE__ 1
// CHECK_ICX_M64: #define __amd64 1
// CHECK_ICX_M64: #define __amd64__ 1
// CHECK_ICX_M64: #define __corei7 1
// CHECK_ICX_M64: #define __corei7__ 1
// CHECK_ICX_M64: #define __tune_corei7__ 1
// CHECK_ICX_M64: #define __x86_64 1
// CHECK_ICX_M64: #define __x86_64__ 1
[X86] Support -march=tigerlake Support -march=tigerlake for x86. Compare with Icelake Client, It include 4 more new features ,they are avx512vp2intersect, movdiri, movdir64b, shstk. Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D65840 llvm-svn: 368543
2019-08-12 09:29:46 +08:00
// RUN: %clang -march=tigerlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_TGL_M32
// CHECK_TGL_M32: #define __AES__ 1
// CHECK_TGL_M32: #define __AVX2__ 1
// CHECK_TGL_M32: #define __AVX512BITALG__ 1
// CHECK_TGL_M32: #define __AVX512BW__ 1
// CHECK_TGL_M32: #define __AVX512CD__ 1
// CHECK_TGL_M32: #define __AVX512DQ__ 1
// CHECK_TGL_M32: #define __AVX512F__ 1
// CHECK_TGL_M32: #define __AVX512IFMA__ 1
// CHECK_TGL_M32: #define __AVX512VBMI2__ 1
// CHECK_TGL_M32: #define __AVX512VBMI__ 1
// CHECK_TGL_M32: #define __AVX512VL__ 1
// CHECK_TGL_M32: #define __AVX512VNNI__ 1
// CHECK_TGL_M32: #define __AVX512VP2INTERSECT__ 1
// CHECK_TGL_M32: #define __AVX512VPOPCNTDQ__ 1
// CHECK_TGL_M32: #define __AVX__ 1
// CHECK_TGL_M32: #define __BMI2__ 1
// CHECK_TGL_M32: #define __BMI__ 1
// CHECK_TGL_M32: #define __CLFLUSHOPT__ 1
// CHECK_TGL_M32: #define __CLWB__ 1
// CHECK_TGL_M32: #define __F16C__ 1
// CHECK_TGL_M32: #define __FMA__ 1
// CHECK_TGL_M32: #define __GFNI__ 1
// CHECK_TGL_M32: #define __INVPCID__ 1
// CHECK_TGL_M32: #define __LZCNT__ 1
// CHECK_TGL_M32: #define __MMX__ 1
// CHECK_TGL_M32: #define __MOVBE__ 1
// CHECK_TGL_M32: #define __MOVDIR64B__ 1
// CHECK_TGL_M32: #define __MOVDIRI__ 1
// CHECK_TGL_M32: #define __PCLMUL__ 1
// CHECK_TGL_M32-NOT: #define __PCONFIG__ 1
// CHECK_TGL_M32: #define __PKU__ 1
// CHECK_TGL_M32: #define __POPCNT__ 1
// CHECK_TGL_M32: #define __PRFCHW__ 1
// CHECK_TGL_M32: #define __RDPID__ 1
// CHECK_TGL_M32: #define __RDRND__ 1
// CHECK_TGL_M32: #define __RDSEED__ 1
// CHECK_TGL_M32: #define __SGX__ 1
// CHECK_TGL_M32: #define __SHA__ 1
// CHECK_TGL_M32: #define __SHSTK__ 1
// CHECK_TGL_M32: #define __SSE2__ 1
// CHECK_TGL_M32: #define __SSE3__ 1
// CHECK_TGL_M32: #define __SSE4_1__ 1
// CHECK_TGL_M32: #define __SSE4_2__ 1
// CHECK_TGL_M32: #define __SSE__ 1
// CHECK_TGL_M32: #define __SSSE3__ 1
// CHECK_TGL_M32: #define __VAES__ 1
// CHECK_TGL_M32: #define __VPCLMULQDQ__ 1
// CHECK_TGL_M32-NOT: #define __WBNOINVD__ 1
// CHECK_TGL_M32: #define __XSAVEC__ 1
// CHECK_TGL_M32: #define __XSAVEOPT__ 1
// CHECK_TGL_M32: #define __XSAVES__ 1
// CHECK_TGL_M32: #define __XSAVE__ 1
// CHECK_TGL_M32: #define __corei7 1
// CHECK_TGL_M32: #define __corei7__ 1
// CHECK_TGL_M32: #define __i386 1
// CHECK_TGL_M32: #define __i386__ 1
// CHECK_TGL_M32: #define __tune_corei7__ 1
// CHECK_TGL_M32: #define i386 1
// RUN: %clang -march=tigerlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_TGL_M64
// CHECK_TGL_M64: #define __AES__ 1
// CHECK_TGL_M64: #define __AVX2__ 1
// CHECK_TGL_M64: #define __AVX512BITALG__ 1
// CHECK_TGL_M64: #define __AVX512BW__ 1
// CHECK_TGL_M64: #define __AVX512CD__ 1
// CHECK_TGL_M64: #define __AVX512DQ__ 1
// CHECK_TGL_M64: #define __AVX512F__ 1
// CHECK_TGL_M64: #define __AVX512IFMA__ 1
// CHECK_TGL_M64: #define __AVX512VBMI2__ 1
// CHECK_TGL_M64: #define __AVX512VBMI__ 1
// CHECK_TGL_M64: #define __AVX512VL__ 1
// CHECK_TGL_M64: #define __AVX512VNNI__ 1
// CHECK_TGL_M64: #define __AVX512VP2INTERSECT__ 1
// CHECK_TGL_M64: #define __AVX512VPOPCNTDQ__ 1
// CHECK_TGL_M64: #define __AVX__ 1
// CHECK_TGL_M64: #define __BMI2__ 1
// CHECK_TGL_M64: #define __BMI__ 1
// CHECK_TGL_M64: #define __CLFLUSHOPT__ 1
// CHECK_TGL_M64: #define __CLWB__ 1
// CHECK_TGL_M64: #define __F16C__ 1
// CHECK_TGL_M64: #define __FMA__ 1
// CHECK_TGL_M64: #define __GFNI__ 1
// CHECK_TGL_M64: #define __INVPCID__ 1
// CHECK_TGL_M64: #define __LZCNT__ 1
// CHECK_TGL_M64: #define __MMX__ 1
// CHECK_TGL_M64: #define __MOVBE__ 1
// CHECK_TGL_M64: #define __MOVDIR64B__ 1
// CHECK_TGL_M64: #define __MOVDIRI__ 1
// CHECK_TGL_M64: #define __PCLMUL__ 1
// CHECK_TGL_M64-NOT: #define __PCONFIG__ 1
// CHECK_TGL_M64: #define __PKU__ 1
// CHECK_TGL_M64: #define __POPCNT__ 1
// CHECK_TGL_M64: #define __PRFCHW__ 1
// CHECK_TGL_M64: #define __RDPID__ 1
// CHECK_TGL_M64: #define __RDRND__ 1
// CHECK_TGL_M64: #define __RDSEED__ 1
// CHECK_TGL_M64: #define __SGX__ 1
// CHECK_TGL_M64: #define __SHA__ 1
// CHECK_TGL_M64: #define __SHSTK__ 1
// CHECK_TGL_M64: #define __SSE2__ 1
// CHECK_TGL_M64: #define __SSE3__ 1
// CHECK_TGL_M64: #define __SSE4_1__ 1
// CHECK_TGL_M64: #define __SSE4_2__ 1
// CHECK_TGL_M64: #define __SSE__ 1
// CHECK_TGL_M64: #define __SSSE3__ 1
// CHECK_TGL_M64: #define __VAES__ 1
// CHECK_TGL_M64: #define __VPCLMULQDQ__ 1
// CHECK_TGL_M64-NOT: #define __WBNOINVD__ 1
// CHECK_TGL_M64: #define __XSAVEC__ 1
// CHECK_TGL_M64: #define __XSAVEOPT__ 1
// CHECK_TGL_M64: #define __XSAVES__ 1
// CHECK_TGL_M64: #define __XSAVE__ 1
// CHECK_TGL_M64: #define __amd64 1
// CHECK_TGL_M64: #define __amd64__ 1
// CHECK_TGL_M64: #define __corei7 1
// CHECK_TGL_M64: #define __corei7__ 1
// CHECK_TGL_M64: #define __tune_corei7__ 1
// CHECK_TGL_M64: #define __x86_64 1
// CHECK_TGL_M64: #define __x86_64__ 1
[X86] Support -march=sapphirerapids Support -march=sapphirerapids for x86. Compare with Icelake Server, it includes 14 more new features. They are amxtile, amxint8, amxbf16, avx512bf16, avx512vp2intersect, cldemote, enqcmd, movdir64b, movdiri, ptwrite, serialize, shstk, tsxldtrk, waitpkg. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D86503
2020-08-25 12:27:02 +08:00
// RUN: %clang -march=sapphirerapids -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPR_M32
// CHECK_SPR_M32: #define __AES__ 1
// CHECK_SPR_M32: #define __AMXBF16__ 1
// CHECK_SPR_M32: #define __AMXINT8__ 1
// CHECK_SPR_M32: #define __AMXTILE__ 1
// CHECK_SPR_M32: #define __AVX2__ 1
// CHECK_SPR_M32: #define __AVX512BF16__ 1
// CHECK_SPR_M32: #define __AVX512BITALG__ 1
// CHECK_SPR_M32: #define __AVX512BW__ 1
// CHECK_SPR_M32: #define __AVX512CD__ 1
// CHECK_SPR_M32: #define __AVX512DQ__ 1
// CHECK_SPR_M32: #define __AVX512F__ 1
// CHECK_SPR_M32: #define __AVX512IFMA__ 1
// CHECK_SPR_M32: #define __AVX512VBMI2__ 1
// CHECK_SPR_M32: #define __AVX512VBMI__ 1
// CHECK_SPR_M32: #define __AVX512VL__ 1
// CHECK_SPR_M32: #define __AVX512VNNI__ 1
// CHECK_SPR_M32: #define __AVX512VPOPCNTDQ__ 1
[X86] Support Intel avxvnni This patch mainly made the following changes: 1. Support AVX-VNNI instructions; 2. Introduce ExplicitVEXPrefix flag so that vpdpbusd/vpdpbusds/vpdpbusds/vpdpbusds instructions only use vex-encoding when user explicity add {vex} prefix. Differential Revision: https://reviews.llvm.org/D89105
2020-10-30 12:58:05 +08:00
// CHECK_SPR_M32: #define __AVXVNNI__ 1
[X86] Support -march=sapphirerapids Support -march=sapphirerapids for x86. Compare with Icelake Server, it includes 14 more new features. They are amxtile, amxint8, amxbf16, avx512bf16, avx512vp2intersect, cldemote, enqcmd, movdir64b, movdiri, ptwrite, serialize, shstk, tsxldtrk, waitpkg. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D86503
2020-08-25 12:27:02 +08:00
// CHECK_SPR_M32: #define __AVX__ 1
// CHECK_SPR_M32: #define __BMI2__ 1
// CHECK_SPR_M32: #define __BMI__ 1
// CHECK_SPR_M32: #define __CLDEMOTE__ 1
// CHECK_SPR_M32: #define __CLFLUSHOPT__ 1
// CHECK_SPR_M32: #define __CLWB__ 1
// CHECK_SPR_M32: #define __ENQCMD__ 1
// CHECK_SPR_M32: #define __F16C__ 1
// CHECK_SPR_M32: #define __FMA__ 1
// CHECK_SPR_M32: #define __GFNI__ 1
// CHECK_SPR_M32: #define __INVPCID__ 1
// CHECK_SPR_M32: #define __LZCNT__ 1
// CHECK_SPR_M32: #define __MMX__ 1
// CHECK_SPR_M32: #define __MOVBE__ 1
// CHECK_SPR_M32: #define __PCLMUL__ 1
// CHECK_SPR_M32: #define __PCONFIG__ 1
// CHECK_SPR_M32: #define __PKU__ 1
// CHECK_SPR_M32: #define __POPCNT__ 1
// CHECK_SPR_M32: #define __PRFCHW__ 1
// CHECK_SPR_M32: #define __PTWRITE__ 1
// CHECK_SPR_M32: #define __RDPID__ 1
// CHECK_SPR_M32: #define __RDRND__ 1
// CHECK_SPR_M32: #define __RDSEED__ 1
// CHECK_SPR_M32: #define __SERIALIZE__ 1
// CHECK_SPR_M32: #define __SGX__ 1
// CHECK_SPR_M32: #define __SHA__ 1
// CHECK_SPR_M32: #define __SHSTK__ 1
// CHECK_SPR_M32: #define __SSE2__ 1
// CHECK_SPR_M32: #define __SSE3__ 1
// CHECK_SPR_M32: #define __SSE4_1__ 1
// CHECK_SPR_M32: #define __SSE4_2__ 1
// CHECK_SPR_M32: #define __SSE__ 1
// CHECK_SPR_M32: #define __SSSE3__ 1
// CHECK_SPR_M32: #define __TSXLDTRK__ 1
[X86] Add User Interrupts(UINTR) instructions For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89301
2020-10-22 16:46:07 +08:00
// CHECK_SPR_M32: #define __UINTR__ 1
[X86] Support -march=sapphirerapids Support -march=sapphirerapids for x86. Compare with Icelake Server, it includes 14 more new features. They are amxtile, amxint8, amxbf16, avx512bf16, avx512vp2intersect, cldemote, enqcmd, movdir64b, movdiri, ptwrite, serialize, shstk, tsxldtrk, waitpkg. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D86503
2020-08-25 12:27:02 +08:00
// CHECK_SPR_M32: #define __VAES__ 1
// CHECK_SPR_M32: #define __VPCLMULQDQ__ 1
// CHECK_SPR_M32: #define __WAITPKG__ 1
// CHECK_SPR_M32: #define __WBNOINVD__ 1
// CHECK_SPR_M32: #define __XSAVEC__ 1
// CHECK_SPR_M32: #define __XSAVEOPT__ 1
// CHECK_SPR_M32: #define __XSAVES__ 1
// CHECK_SPR_M32: #define __XSAVE__ 1
// CHECK_SPR_M32: #define __corei7 1
// CHECK_SPR_M32: #define __corei7__ 1
// CHECK_SPR_M32: #define __i386 1
// CHECK_SPR_M32: #define __i386__ 1
// CHECK_SPR_M32: #define __tune_corei7__ 1
// CHECK_SPR_M32: #define i386 1
// RUN: %clang -march=sapphirerapids -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPR_M64
// CHECK_SPR_M64: #define __AES__ 1
// CHECK_SPR_M64: #define __AMXBF16__ 1
// CHECK_SPR_M64: #define __AMXINT8__ 1
// CHECK_SPR_M64: #define __AMXTILE__ 1
// CHECK_SPR_M64: #define __AVX2__ 1
// CHECK_SPR_M64: #define __AVX512BF16__ 1
// CHECK_SPR_M64: #define __AVX512BITALG__ 1
// CHECK_SPR_M64: #define __AVX512BW__ 1
// CHECK_SPR_M64: #define __AVX512CD__ 1
// CHECK_SPR_M64: #define __AVX512DQ__ 1
// CHECK_SPR_M64: #define __AVX512F__ 1
// CHECK_SPR_M64: #define __AVX512IFMA__ 1
// CHECK_SPR_M64: #define __AVX512VBMI2__ 1
// CHECK_SPR_M64: #define __AVX512VBMI__ 1
// CHECK_SPR_M64: #define __AVX512VL__ 1
// CHECK_SPR_M64: #define __AVX512VNNI__ 1
// CHECK_SPR_M64: #define __AVX512VPOPCNTDQ__ 1
[X86] Support Intel avxvnni This patch mainly made the following changes: 1. Support AVX-VNNI instructions; 2. Introduce ExplicitVEXPrefix flag so that vpdpbusd/vpdpbusds/vpdpbusds/vpdpbusds instructions only use vex-encoding when user explicity add {vex} prefix. Differential Revision: https://reviews.llvm.org/D89105
2020-10-30 12:58:05 +08:00
// CHECK_SPR_M64: #define __AVXVNNI__ 1
[X86] Support -march=sapphirerapids Support -march=sapphirerapids for x86. Compare with Icelake Server, it includes 14 more new features. They are amxtile, amxint8, amxbf16, avx512bf16, avx512vp2intersect, cldemote, enqcmd, movdir64b, movdiri, ptwrite, serialize, shstk, tsxldtrk, waitpkg. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D86503
2020-08-25 12:27:02 +08:00
// CHECK_SPR_M64: #define __AVX__ 1
// CHECK_SPR_M64: #define __BMI2__ 1
// CHECK_SPR_M64: #define __BMI__ 1
// CHECK_SPR_M64: #define __CLDEMOTE__ 1
// CHECK_SPR_M64: #define __CLFLUSHOPT__ 1
// CHECK_SPR_M64: #define __CLWB__ 1
// CHECK_SPR_M64: #define __ENQCMD__ 1
// CHECK_SPR_M64: #define __F16C__ 1
// CHECK_SPR_M64: #define __FMA__ 1
// CHECK_SPR_M64: #define __GFNI__ 1
// CHECK_SPR_M64: #define __INVPCID__ 1
// CHECK_SPR_M64: #define __LZCNT__ 1
// CHECK_SPR_M64: #define __MMX__ 1
// CHECK_SPR_M64: #define __MOVBE__ 1
// CHECK_SPR_M64: #define __PCLMUL__ 1
// CHECK_SPR_M64: #define __PCONFIG__ 1
// CHECK_SPR_M64: #define __PKU__ 1
// CHECK_SPR_M64: #define __POPCNT__ 1
// CHECK_SPR_M64: #define __PRFCHW__ 1
// CHECK_SPR_M64: #define __PTWRITE__ 1
// CHECK_SPR_M64: #define __RDPID__ 1
// CHECK_SPR_M64: #define __RDRND__ 1
// CHECK_SPR_M64: #define __RDSEED__ 1
// CHECK_SPR_M64: #define __SERIALIZE__ 1
// CHECK_SPR_M64: #define __SGX__ 1
// CHECK_SPR_M64: #define __SHA__ 1
// CHECK_SPR_M64: #define __SHSTK__ 1
// CHECK_SPR_M64: #define __SSE2__ 1
// CHECK_SPR_M64: #define __SSE3__ 1
// CHECK_SPR_M64: #define __SSE4_1__ 1
// CHECK_SPR_M64: #define __SSE4_2__ 1
// CHECK_SPR_M64: #define __SSE__ 1
// CHECK_SPR_M64: #define __SSSE3__ 1
// CHECK_SPR_M64: #define __TSXLDTRK__ 1
[X86] Add User Interrupts(UINTR) instructions For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89301
2020-10-22 16:46:07 +08:00
// CHECK_SPR_M64: #define __UINTR__ 1
[X86] Support -march=sapphirerapids Support -march=sapphirerapids for x86. Compare with Icelake Server, it includes 14 more new features. They are amxtile, amxint8, amxbf16, avx512bf16, avx512vp2intersect, cldemote, enqcmd, movdir64b, movdiri, ptwrite, serialize, shstk, tsxldtrk, waitpkg. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D86503
2020-08-25 12:27:02 +08:00
// CHECK_SPR_M64: #define __VAES__ 1
// CHECK_SPR_M64: #define __VPCLMULQDQ__ 1
// CHECK_SPR_M64: #define __WAITPKG__ 1
// CHECK_SPR_M64: #define __WBNOINVD__ 1
// CHECK_SPR_M64: #define __XSAVEC__ 1
// CHECK_SPR_M64: #define __XSAVEOPT__ 1
// CHECK_SPR_M64: #define __XSAVES__ 1
// CHECK_SPR_M64: #define __XSAVE__ 1
// CHECK_SPR_M64: #define __amd64 1
// CHECK_SPR_M64: #define __amd64__ 1
// CHECK_SPR_M64: #define __corei7 1
// CHECK_SPR_M64: #define __corei7__ 1
// CHECK_SPR_M64: #define __tune_corei7__ 1
// CHECK_SPR_M64: #define __x86_64 1
// CHECK_SPR_M64: #define __x86_64__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// RUN: %clang -march=alderlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ADL_M32
// CHECK_ADL_M32: #define __ADX__ 1
// CHECK_ADL_M32: #define __AES__ 1
// CHECK_ADL_M32: #define __AVX2__ 1
// CHECK_ADL_M32-NOT: AVX512
[X86] Support Intel avxvnni This patch mainly made the following changes: 1. Support AVX-VNNI instructions; 2. Introduce ExplicitVEXPrefix flag so that vpdpbusd/vpdpbusds/vpdpbusds/vpdpbusds instructions only use vex-encoding when user explicity add {vex} prefix. Differential Revision: https://reviews.llvm.org/D89105
2020-10-30 12:58:05 +08:00
// CHECK_ADL_M32: #define __AVXVNNI__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __AVX__ 1
// CHECK_ADL_M32: #define __BMI2__ 1
// CHECK_ADL_M32: #define __BMI__ 1
// CHECK_ADL_M32: #define __CLDEMOTE__ 1
// CHECK_ADL_M32: #define __CLFLUSHOPT__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __CLWB__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __F16C__ 1
// CHECK_ADL_M32: #define __FMA__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __FSGSBASE__ 1
// CHECK_ADL_M32: #define __FXSR__ 1
// CHECK_ADL_M32: #define __GFNI__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __HRESET__ 1
// CHECK_ADL_M32: #define __INVPCID__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __KL__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __LZCNT__ 1
// CHECK_ADL_M32: #define __MMX__ 1
// CHECK_ADL_M32: #define __MOVBE__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __MOVDIR64B__ 1
// CHECK_ADL_M32: #define __MOVDIRI__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __PCLMUL__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __PCONFIG__ 1
// CHECK_ADL_M32: #define __PKU__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __POPCNT__ 1
// CHECK_ADL_M32: #define __PRFCHW__ 1
// CHECK_ADL_M32: #define __PTWRITE__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __RDPID__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __RDRND__ 1
// CHECK_ADL_M32: #define __RDSEED__ 1
// CHECK_ADL_M32: #define __SERIALIZE__ 1
// CHECK_ADL_M32: #define __SGX__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __SHA__ 1
// CHECK_ADL_M32: #define __SHSTK__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __SSE2__ 1
// CHECK_ADL_M32: #define __SSE3__ 1
// CHECK_ADL_M32: #define __SSE4_1__ 1
// CHECK_ADL_M32: #define __SSE4_2__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __SSE_MATH__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __SSE__ 1
// CHECK_ADL_M32: #define __SSSE3__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __VAES__ 1
// CHECK_ADL_M32: #define __VPCLMULQDQ__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __WAITPKG__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __WIDEKL__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define __XSAVEC__ 1
// CHECK_ADL_M32: #define __XSAVEOPT__ 1
// CHECK_ADL_M32: #define __XSAVES__ 1
// CHECK_ADL_M32: #define __XSAVE__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M32: #define __corei7 1
// CHECK_ADL_M32: #define __corei7__ 1
// CHECK_ADL_M32: #define __i386 1
// CHECK_ADL_M32: #define __i386__ 1
// CHECK_ADL_M32: #define __tune_corei7__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M32: #define i386 1
// RUN: %clang -march=alderlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ADL_M64
// CHECK_ADL_M64: #define __ADX__ 1
// CHECK_ADL_M64: #define __AES__ 1
// CHECK_ADL_M64: #define __AVX2__ 1
// CHECK_ADL_M64-NOT: AVX512
[X86] Support Intel avxvnni This patch mainly made the following changes: 1. Support AVX-VNNI instructions; 2. Introduce ExplicitVEXPrefix flag so that vpdpbusd/vpdpbusds/vpdpbusds/vpdpbusds instructions only use vex-encoding when user explicity add {vex} prefix. Differential Revision: https://reviews.llvm.org/D89105
2020-10-30 12:58:05 +08:00
// CHECK_ADL_M64: #define __AVXVNNI__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __AVX__ 1
// CHECK_ADL_M64: #define __BMI2__ 1
// CHECK_ADL_M64: #define __BMI__ 1
// CHECK_ADL_M64: #define __CLDEMOTE__ 1
// CHECK_ADL_M64: #define __CLFLUSHOPT__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __CLWB__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __F16C__ 1
// CHECK_ADL_M64: #define __FMA__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __FSGSBASE__ 1
// CHECK_ADL_M64: #define __FXSR__ 1
// CHECK_ADL_M64: #define __GFNI__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __HRESET__ 1
// CHECK_ADL_M64: #define __INVPCID__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __KL__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __LZCNT__ 1
// CHECK_ADL_M64: #define __MMX__ 1
// CHECK_ADL_M64: #define __MOVBE__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __MOVDIR64B__ 1
// CHECK_ADL_M64: #define __MOVDIRI__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __PCLMUL__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __PCONFIG__ 1
// CHECK_ADL_M64: #define __PKU__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __POPCNT__ 1
// CHECK_ADL_M64: #define __PRFCHW__ 1
// CHECK_ADL_M64: #define __PTWRITE__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __RDPID__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __RDRND__ 1
// CHECK_ADL_M64: #define __RDSEED__ 1
// CHECK_ADL_M64: #define __SERIALIZE__ 1
// CHECK_ADL_M64: #define __SGX__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __SHA__ 1
// CHECK_ADL_M64: #define __SHSTK__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __SSE2_MATH__ 1
// CHECK_ADL_M64: #define __SSE2__ 1
// CHECK_ADL_M64: #define __SSE3__ 1
// CHECK_ADL_M64: #define __SSE4_1__ 1
// CHECK_ADL_M64: #define __SSE4_2__ 1
// CHECK_ADL_M64: #define __SSE_MATH__ 1
// CHECK_ADL_M64: #define __SSE__ 1
// CHECK_ADL_M64: #define __SSSE3__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __VAES__ 1
// CHECK_ADL_M64: #define __VPCLMULQDQ__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __WAITPKG__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __WIDEKL__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __XSAVEC__ 1
// CHECK_ADL_M64: #define __XSAVEOPT__ 1
// CHECK_ADL_M64: #define __XSAVES__ 1
// CHECK_ADL_M64: #define __XSAVE__ 1
// CHECK_ADL_M64: #define __amd64 1
// CHECK_ADL_M64: #define __amd64__ 1
[X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-03-03 16:17:37 +08:00
// CHECK_ADL_M64: #define __corei7 1
// CHECK_ADL_M64: #define __corei7__ 1
// CHECK_ADL_M64: #define __tune_corei7__ 1
[X86] Add a stub for Intel's alderlake. No scheduling, no autodetection.
2020-10-25 00:00:33 +08:00
// CHECK_ADL_M64: #define __x86_64 1
// CHECK_ADL_M64: #define __x86_64__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=atom -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATOM_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATOM_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_ATOM_M32: #define __MOVBE__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATOM_M32: #define __SSE2__ 1
// CHECK_ATOM_M32: #define __SSE3__ 1
// CHECK_ATOM_M32: #define __SSE__ 1
// CHECK_ATOM_M32: #define __SSSE3__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATOM_M32: #define __atom 1
// CHECK_ATOM_M32: #define __atom__ 1
// CHECK_ATOM_M32: #define __i386 1
// CHECK_ATOM_M32: #define __i386__ 1
// CHECK_ATOM_M32: #define __tune_atom__ 1
// CHECK_ATOM_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=atom -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATOM_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATOM_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_ATOM_M64: #define __MOVBE__ 1
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATOM_M64: #define __SSE2_MATH__ 1
// CHECK_ATOM_M64: #define __SSE2__ 1
// CHECK_ATOM_M64: #define __SSE3__ 1
// CHECK_ATOM_M64: #define __SSE_MATH__ 1
// CHECK_ATOM_M64: #define __SSE__ 1
// CHECK_ATOM_M64: #define __SSSE3__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_ATOM_M64: #define __amd64 1
// CHECK_ATOM_M64: #define __amd64__ 1
// CHECK_ATOM_M64: #define __atom 1
// CHECK_ATOM_M64: #define __atom__ 1
// CHECK_ATOM_M64: #define __tune_atom__ 1
// CHECK_ATOM_M64: #define __x86_64 1
// CHECK_ATOM_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[Clang][X86][Goldmont]Adding new target-cpu: Goldmont [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
2017-06-29 21:41:04 +08:00
// RUN: %clang -march=goldmont -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck %s -check-prefix=CHECK_GLM_M32
// CHECK_GLM_M32: #define __AES__ 1
// CHECK_GLM_M32: #define __CLFLUSHOPT__ 1
[Clang] Adding missing feature to goldmont Change-Id: I6c22478d16b8e02ce60dae2f8c80d43bc5ab3a9c llvm-svn: 314104
2017-09-25 21:49:32 +08:00
// CHECK_GLM_M32: #define __FSGSBASE__ 1
[Clang][X86][Goldmont]Adding new target-cpu: Goldmont [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
2017-06-29 21:41:04 +08:00
// CHECK_GLM_M32: #define __FXSR__ 1
// CHECK_GLM_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_GLM_M32: #define __MOVBE__ 1
[Clang][X86][Goldmont]Adding new target-cpu: Goldmont [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
2017-06-29 21:41:04 +08:00
// CHECK_GLM_M32: #define __PCLMUL__ 1
// CHECK_GLM_M32: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_GLM_M32: #define __PRFCHW__ 1
[X86] Add RDRND feature to Goldmont. Add MOVBE to all Atom CPUs. Diffential Revision: https://reviews.llvm.org/D34842 llvm-svn: 306851
2017-07-01 02:14:04 +08:00
// CHECK_GLM_M32: #define __RDRND__ 1
[Clang][X86][Goldmont]Adding new target-cpu: Goldmont [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
2017-06-29 21:41:04 +08:00
// CHECK_GLM_M32: #define __RDSEED__ 1
// CHECK_GLM_M32: #define __SHA__ 1
// CHECK_GLM_M32: #define __SSE2__ 1
// CHECK_GLM_M32: #define __SSE3__ 1
// CHECK_GLM_M32: #define __SSE4_1__ 1
// CHECK_GLM_M32: #define __SSE4_2__ 1
// CHECK_GLM_M32: #define __SSE_MATH__ 1
// CHECK_GLM_M32: #define __SSE__ 1
// CHECK_GLM_M32: #define __SSSE3__ 1
// CHECK_GLM_M32: #define __XSAVEC__ 1
// CHECK_GLM_M32: #define __XSAVEOPT__ 1
// CHECK_GLM_M32: #define __XSAVES__ 1
// CHECK_GLM_M32: #define __XSAVE__ 1
// CHECK_GLM_M32: #define __goldmont 1
// CHECK_GLM_M32: #define __goldmont__ 1
// CHECK_GLM_M32: #define __i386 1
// CHECK_GLM_M32: #define __i386__ 1
// CHECK_GLM_M32: #define __tune_goldmont__ 1
// CHECK_GLM_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[Clang][X86][Goldmont]Adding new target-cpu: Goldmont [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
2017-06-29 21:41:04 +08:00
// RUN: %clang -march=goldmont -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck %s -check-prefix=CHECK_GLM_M64
// CHECK_GLM_M64: #define __AES__ 1
// CHECK_GLM_M64: #define __CLFLUSHOPT__ 1
[Clang] Adding missing feature to goldmont Change-Id: I6c22478d16b8e02ce60dae2f8c80d43bc5ab3a9c llvm-svn: 314104
2017-09-25 21:49:32 +08:00
// CHECK_GLM_M64: #define __FSGSBASE__ 1
[Clang][X86][Goldmont]Adding new target-cpu: Goldmont [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
2017-06-29 21:41:04 +08:00
// CHECK_GLM_M64: #define __FXSR__ 1
// CHECK_GLM_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_GLM_M64: #define __MOVBE__ 1
[Clang][X86][Goldmont]Adding new target-cpu: Goldmont [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
2017-06-29 21:41:04 +08:00
// CHECK_GLM_M64: #define __PCLMUL__ 1
// CHECK_GLM_M64: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_GLM_M64: #define __PRFCHW__ 1
[X86] Add RDRND feature to Goldmont. Add MOVBE to all Atom CPUs. Diffential Revision: https://reviews.llvm.org/D34842 llvm-svn: 306851
2017-07-01 02:14:04 +08:00
// CHECK_GLM_M64: #define __RDRND__ 1
[Clang][X86][Goldmont]Adding new target-cpu: Goldmont [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
2017-06-29 21:41:04 +08:00
// CHECK_GLM_M64: #define __RDSEED__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_GLM_M64: #define __SHA__ 1
[Clang][X86][Goldmont]Adding new target-cpu: Goldmont [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
2017-06-29 21:41:04 +08:00
// CHECK_GLM_M64: #define __SSE2__ 1
// CHECK_GLM_M64: #define __SSE3__ 1
// CHECK_GLM_M64: #define __SSE4_1__ 1
// CHECK_GLM_M64: #define __SSE4_2__ 1
// CHECK_GLM_M64: #define __SSE__ 1
// CHECK_GLM_M64: #define __SSSE3__ 1
// CHECK_GLM_M64: #define __XSAVEC__ 1
// CHECK_GLM_M64: #define __XSAVEOPT__ 1
// CHECK_GLM_M64: #define __XSAVES__ 1
// CHECK_GLM_M64: #define __XSAVE__ 1
// CHECK_GLM_M64: #define __goldmont 1
// CHECK_GLM_M64: #define __goldmont__ 1
// CHECK_GLM_M64: #define __tune_goldmont__ 1
// CHECK_GLM_M64: #define __x86_64 1
// CHECK_GLM_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// RUN: %clang -march=goldmont-plus -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck %s -check-prefix=CHECK_GLMP_M32
// CHECK_GLMP_M32: #define __AES__ 1
// CHECK_GLMP_M32: #define __CLFLUSHOPT__ 1
// CHECK_GLMP_M32: #define __FSGSBASE__ 1
// CHECK_GLMP_M32: #define __FXSR__ 1
// CHECK_GLMP_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_GLMP_M32: #define __MOVBE__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_GLMP_M32: #define __PCLMUL__ 1
// CHECK_GLMP_M32: #define __POPCNT__ 1
// CHECK_GLMP_M32: #define __PRFCHW__ 1
[X86] ptwrite intrinsic Reviewers: craig.topper, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46540 llvm-svn: 331962
2018-05-10 15:28:54 +08:00
// CHECK_GLMP_M32: #define __PTWRITE__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_GLMP_M32: #define __RDPID__ 1
// CHECK_GLMP_M32: #define __RDRND__ 1
// CHECK_GLMP_M32: #define __RDSEED__ 1
// CHECK_GLMP_M32: #define __SGX__ 1
// CHECK_GLMP_M32: #define __SHA__ 1
// CHECK_GLMP_M32: #define __SSE2__ 1
// CHECK_GLMP_M32: #define __SSE3__ 1
// CHECK_GLMP_M32: #define __SSE4_1__ 1
// CHECK_GLMP_M32: #define __SSE4_2__ 1
// CHECK_GLMP_M32: #define __SSE_MATH__ 1
// CHECK_GLMP_M32: #define __SSE__ 1
// CHECK_GLMP_M32: #define __SSSE3__ 1
// CHECK_GLMP_M32: #define __XSAVEC__ 1
// CHECK_GLMP_M32: #define __XSAVEOPT__ 1
// CHECK_GLMP_M32: #define __XSAVES__ 1
// CHECK_GLMP_M32: #define __XSAVE__ 1
// CHECK_GLMP_M32: #define __goldmont_plus 1
// CHECK_GLMP_M32: #define __goldmont_plus__ 1
// CHECK_GLMP_M32: #define __i386 1
// CHECK_GLMP_M32: #define __i386__ 1
// CHECK_GLMP_M32: #define __tune_goldmont_plus__ 1
// CHECK_GLMP_M32: #define i386 1
// RUN: %clang -march=goldmont-plus -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck %s -check-prefix=CHECK_GLMP_M64
// CHECK_GLMP_M64: #define __AES__ 1
// CHECK_GLMP_M64: #define __CLFLUSHOPT__ 1
// CHECK_GLMP_M64: #define __FSGSBASE__ 1
// CHECK_GLMP_M64: #define __FXSR__ 1
// CHECK_GLMP_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_GLMP_M64: #define __MOVBE__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_GLMP_M64: #define __PCLMUL__ 1
// CHECK_GLMP_M64: #define __POPCNT__ 1
// CHECK_GLMP_M64: #define __PRFCHW__ 1
[X86] ptwrite intrinsic Reviewers: craig.topper, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46540 llvm-svn: 331962
2018-05-10 15:28:54 +08:00
// CHECK_GLMP_M64: #define __PTWRITE__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_GLMP_M64: #define __RDPID__ 1
// CHECK_GLMP_M64: #define __RDRND__ 1
// CHECK_GLMP_M64: #define __RDSEED__ 1
// CHECK_GLMP_M64: #define __SGX__ 1
// CHECK_GLMP_M64: #define __SHA__ 1
// CHECK_GLMP_M64: #define __SSE2__ 1
// CHECK_GLMP_M64: #define __SSE3__ 1
// CHECK_GLMP_M64: #define __SSE4_1__ 1
// CHECK_GLMP_M64: #define __SSE4_2__ 1
// CHECK_GLMP_M64: #define __SSE__ 1
// CHECK_GLMP_M64: #define __SSSE3__ 1
// CHECK_GLMP_M64: #define __XSAVEC__ 1
// CHECK_GLMP_M64: #define __XSAVEOPT__ 1
// CHECK_GLMP_M64: #define __XSAVES__ 1
// CHECK_GLMP_M64: #define __XSAVE__ 1
// CHECK_GLMP_M64: #define __goldmont_plus 1
// CHECK_GLMP_M64: #define __goldmont_plus__ 1
// CHECK_GLMP_M64: #define __tune_goldmont_plus__ 1
// CHECK_GLMP_M64: #define __x86_64 1
// CHECK_GLMP_M64: #define __x86_64__ 1
// RUN: %clang -march=tremont -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck %s -check-prefix=CHECK_TRM_M32
// CHECK_TRM_M32: #define __AES__ 1
[X86] Add CLWB to Tremont CPU. Remove CLDEMOTE, MOVDIRI, MOVDIR64B, and WAITPKG to match gcc.
2020-06-03 13:21:12 +08:00
// CHECK_TRM_M32-NOT: #define __CLDEMOTE__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M32: #define __CLFLUSHOPT__ 1
[X86] Add CLWB to Tremont CPU. Remove CLDEMOTE, MOVDIRI, MOVDIR64B, and WAITPKG to match gcc.
2020-06-03 13:21:12 +08:00
// CHECK_TRM_M32: #define __CLWB__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M32: #define __FSGSBASE__ 1
// CHECK_TRM_M32: #define __FXSR__ 1
// CHECK_TRM_M32: #define __GFNI__ 1
// CHECK_TRM_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_TRM_M32: #define __MOVBE__ 1
[X86] Add CLWB to Tremont CPU. Remove CLDEMOTE, MOVDIRI, MOVDIR64B, and WAITPKG to match gcc.
2020-06-03 13:21:12 +08:00
// CHECK_TRM_M32-NOT: #define __MOVDIR64B__ 1
// CHECK_TRM_M32-NOT: #define __MOVDIRI__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M32: #define __PCLMUL__ 1
// CHECK_TRM_M32: #define __POPCNT__ 1
// CHECK_TRM_M32: #define __PRFCHW__ 1
[X86] ptwrite intrinsic Reviewers: craig.topper, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46540 llvm-svn: 331962
2018-05-10 15:28:54 +08:00
// CHECK_TRM_M32: #define __PTWRITE__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M32: #define __RDPID__ 1
// CHECK_TRM_M32: #define __RDRND__ 1
// CHECK_TRM_M32: #define __RDSEED__ 1
// CHECK_TRM_M32: #define __SGX__ 1
// CHECK_TRM_M32: #define __SHA__ 1
// CHECK_TRM_M32: #define __SSE2__ 1
// CHECK_TRM_M32: #define __SSE3__ 1
// CHECK_TRM_M32: #define __SSE4_1__ 1
// CHECK_TRM_M32: #define __SSE4_2__ 1
// CHECK_TRM_M32: #define __SSE_MATH__ 1
// CHECK_TRM_M32: #define __SSE__ 1
// CHECK_TRM_M32: #define __SSSE3__ 1
[X86] Add CLWB to Tremont CPU. Remove CLDEMOTE, MOVDIRI, MOVDIR64B, and WAITPKG to match gcc.
2020-06-03 13:21:12 +08:00
// CHECK_TRM_M32-NOT: #define __WAITPKG__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M32: #define __XSAVEC__ 1
// CHECK_TRM_M32: #define __XSAVEOPT__ 1
// CHECK_TRM_M32: #define __XSAVES__ 1
// CHECK_TRM_M32: #define __XSAVE__ 1
// CHECK_TRM_M32: #define __i386 1
// CHECK_TRM_M32: #define __i386__ 1
// CHECK_TRM_M32: #define __tremont 1
// CHECK_TRM_M32: #define __tremont__ 1
// CHECK_TRM_M32: #define __tune_tremont__ 1
// CHECK_TRM_M32: #define i386 1
// RUN: %clang -march=tremont -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck %s -check-prefix=CHECK_TRM_M64
// CHECK_TRM_M64: #define __AES__ 1
[X86] Add CLWB to Tremont CPU. Remove CLDEMOTE, MOVDIRI, MOVDIR64B, and WAITPKG to match gcc.
2020-06-03 13:21:12 +08:00
// CHECK_TRM_M64-NOT: #define __CLDEMOTE__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M64: #define __CLFLUSHOPT__ 1
[X86] Add CLWB to Tremont CPU. Remove CLDEMOTE, MOVDIRI, MOVDIR64B, and WAITPKG to match gcc.
2020-06-03 13:21:12 +08:00
// CHECK_TRM_M64: #define __CLWB__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M64: #define __FSGSBASE__ 1
// CHECK_TRM_M64: #define __FXSR__ 1
// CHECK_TRM_M64: #define __GFNI__ 1
// CHECK_TRM_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_TRM_M64: #define __MOVBE__ 1
[X86] Add CLWB to Tremont CPU. Remove CLDEMOTE, MOVDIRI, MOVDIR64B, and WAITPKG to match gcc.
2020-06-03 13:21:12 +08:00
// CHECK_TRM_M64-NOT: #define __MOVDIR64B__ 1
// CHECK_TRM_M64-NOT: #define __MOVDIRI__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M64: #define __PCLMUL__ 1
// CHECK_TRM_M64: #define __POPCNT__ 1
// CHECK_TRM_M64: #define __PRFCHW__ 1
[X86] ptwrite intrinsic Reviewers: craig.topper, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46540 llvm-svn: 331962
2018-05-10 15:28:54 +08:00
// CHECK_TRM_M64: #define __PTWRITE__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M64: #define __RDPID__ 1
// CHECK_TRM_M64: #define __RDRND__ 1
// CHECK_TRM_M64: #define __RDSEED__ 1
// CHECK_TRM_M64: #define __SGX__ 1
// CHECK_TRM_M64: #define __SHA__ 1
// CHECK_TRM_M64: #define __SSE2__ 1
// CHECK_TRM_M64: #define __SSE3__ 1
// CHECK_TRM_M64: #define __SSE4_1__ 1
// CHECK_TRM_M64: #define __SSE4_2__ 1
// CHECK_TRM_M64: #define __SSE__ 1
// CHECK_TRM_M64: #define __SSSE3__ 1
[X86] Add CLWB to Tremont CPU. Remove CLDEMOTE, MOVDIRI, MOVDIR64B, and WAITPKG to match gcc.
2020-06-03 13:21:12 +08:00
// CHECK_TRM_M64-NOT: #define __WAITPKG__ 1
[X86] Introduce archs: goldmont-plus & tremont Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
2018-04-16 16:10:10 +08:00
// CHECK_TRM_M64: #define __XSAVEC__ 1
// CHECK_TRM_M64: #define __XSAVEOPT__ 1
// CHECK_TRM_M64: #define __XSAVES__ 1
// CHECK_TRM_M64: #define __XSAVE__ 1
// CHECK_TRM_M64: #define __tremont 1
// CHECK_TRM_M64: #define __tremont__ 1
// CHECK_TRM_M64: #define __tune_tremont__ 1
// CHECK_TRM_M64: #define __x86_64 1
// CHECK_TRM_M64: #define __x86_64__ 1
Add support for -march=slm, aka Intel Atom Silvermont. llvm-svn: 189670
2013-08-30 22:05:34 +08:00
// RUN: %clang -march=slm -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SLM_M32
[X86] Add missing check lines for the silvermont cases in predefined-arch-macros.c test. llvm-svn: 321343
2017-12-22 13:09:38 +08:00
// CHECK_SLM_M32: #define __FXSR__ 1
Add support for -march=slm, aka Intel Atom Silvermont. llvm-svn: 189670
2013-08-30 22:05:34 +08:00
// CHECK_SLM_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_SLM_M32: #define __MOVBE__ 1
[X86] Add missing check lines for the silvermont cases in predefined-arch-macros.c test. llvm-svn: 321343
2017-12-22 13:09:38 +08:00
// CHECK_SLM_M32: #define __PCLMUL__ 1
// CHECK_SLM_M32: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_SLM_M32: #define __PRFCHW__ 1
[X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix. gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546 llvm-svn: 323552
2018-01-27 03:34:45 +08:00
// CHECK_SLM_M32: #define __RDRND__ 1
Add support for -march=slm, aka Intel Atom Silvermont. llvm-svn: 189670
2013-08-30 22:05:34 +08:00
// CHECK_SLM_M32: #define __SSE2__ 1
// CHECK_SLM_M32: #define __SSE3__ 1
// CHECK_SLM_M32: #define __SSE4_1__ 1
// CHECK_SLM_M32: #define __SSE4_2__ 1
// CHECK_SLM_M32: #define __SSE__ 1
// CHECK_SLM_M32: #define __SSSE3__ 1
// CHECK_SLM_M32: #define __i386 1
// CHECK_SLM_M32: #define __i386__ 1
// CHECK_SLM_M32: #define __slm 1
// CHECK_SLM_M32: #define __slm__ 1
// CHECK_SLM_M32: #define __tune_slm__ 1
// CHECK_SLM_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add support for -march=slm, aka Intel Atom Silvermont. llvm-svn: 189670
2013-08-30 22:05:34 +08:00
// RUN: %clang -march=slm -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SLM_M64
[X86] Add missing check lines for the silvermont cases in predefined-arch-macros.c test. llvm-svn: 321343
2017-12-22 13:09:38 +08:00
// CHECK_SLM_M64: #define __FXSR__ 1
Add support for -march=slm, aka Intel Atom Silvermont. llvm-svn: 189670
2013-08-30 22:05:34 +08:00
// CHECK_SLM_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_SLM_M64: #define __MOVBE__ 1
[X86] Add missing check lines for the silvermont cases in predefined-arch-macros.c test. llvm-svn: 321343
2017-12-22 13:09:38 +08:00
// CHECK_SLM_M64: #define __PCLMUL__ 1
// CHECK_SLM_M64: #define __POPCNT__ 1
[X86] Add 'prfchw' to the correct CPUs to match the backend. llvm-svn: 321341
2017-12-22 12:51:00 +08:00
// CHECK_SLM_M64: #define __PRFCHW__ 1
[X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix. gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546 llvm-svn: 323552
2018-01-27 03:34:45 +08:00
// CHECK_SLM_M64: #define __RDRND__ 1
Add support for -march=slm, aka Intel Atom Silvermont. llvm-svn: 189670
2013-08-30 22:05:34 +08:00
// CHECK_SLM_M64: #define __SSE2_MATH__ 1
// CHECK_SLM_M64: #define __SSE2__ 1
// CHECK_SLM_M64: #define __SSE3__ 1
// CHECK_SLM_M64: #define __SSE4_1__ 1
// CHECK_SLM_M64: #define __SSE4_2__ 1
// CHECK_SLM_M64: #define __SSE_MATH__ 1
// CHECK_SLM_M64: #define __SSE__ 1
// CHECK_SLM_M64: #define __SSSE3__ 1
// CHECK_SLM_M64: #define __amd64 1
// CHECK_SLM_M64: #define __amd64__ 1
// CHECK_SLM_M64: #define __slm 1
// CHECK_SLM_M64: #define __slm__ 1
// CHECK_SLM_M64: #define __tune_slm__ 1
// CHECK_SLM_M64: #define __x86_64 1
// CHECK_SLM_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[X86] Introduction of -march=lakemont. Differential Revision: http://reviews.llvm.org/D18651 llvm-svn: 265405
2016-04-05 23:04:26 +08:00
// RUN: %clang -march=lakemont -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
[X86] Define i586 and pentium preprocessor defines for -march=lakemont to match GCC llvm-svn: 317069
2017-11-01 10:18:49 +08:00
// RUN: | FileCheck %s -check-prefix=CHECK_LAKEMONT_M32
// CHECK_LAKEMONT_M32: #define __i386 1
// CHECK_LAKEMONT_M32: #define __i386__ 1
// CHECK_LAKEMONT_M32: #define __i586 1
// CHECK_LAKEMONT_M32: #define __i586__ 1
// CHECK_LAKEMONT_M32: #define __pentium 1
// CHECK_LAKEMONT_M32: #define __pentium__ 1
// CHECK_LAKEMONT_M32: #define __tune_lakemont__ 1
// CHECK_LAKEMONT_M32: #define i386 1
[X86] Introduction of -march=lakemont. Differential Revision: http://reviews.llvm.org/D18651 llvm-svn: 265405
2016-04-05 23:04:26 +08:00
// RUN: not %clang -march=lakemont -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
[X86] Define i586 and pentium preprocessor defines for -march=lakemont to match GCC llvm-svn: 317069
2017-11-01 10:18:49 +08:00
// RUN: | FileCheck %s -check-prefix=CHECK_LAKEMONT_M64
// CHECK_LAKEMONT_M64: error:
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=geode -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_GEODE_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_GEODE_M32: #define __3dNOW_A__ 1
// CHECK_GEODE_M32: #define __3dNOW__ 1
// CHECK_GEODE_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_GEODE_M32: #define __geode 1
// CHECK_GEODE_M32: #define __geode__ 1
// CHECK_GEODE_M32: #define __i386 1
// CHECK_GEODE_M32: #define __i386__ 1
// CHECK_GEODE_M32: #define __tune_geode__ 1
// CHECK_GEODE_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=geode -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_GEODE_M64
// CHECK_GEODE_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=k6 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_K6_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_K6_M32: #define __i386 1
// CHECK_K6_M32: #define __i386__ 1
// CHECK_K6_M32: #define __k6 1
// CHECK_K6_M32: #define __k6__ 1
// CHECK_K6_M32: #define __tune_k6__ 1
// CHECK_K6_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=k6 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_M64
// CHECK_K6_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=k6-2 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_2_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_K6_2_M32: #define __3dNOW__ 1
// CHECK_K6_2_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_K6_2_M32: #define __i386 1
// CHECK_K6_2_M32: #define __i386__ 1
// CHECK_K6_2_M32: #define __k6 1
// CHECK_K6_2_M32: #define __k6_2__ 1
// CHECK_K6_2_M32: #define __k6__ 1
// CHECK_K6_2_M32: #define __tune_k6_2__ 1
// CHECK_K6_2_M32: #define __tune_k6__ 1
// CHECK_K6_2_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=k6-2 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_2_M64
// CHECK_K6_2_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=k6-3 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_3_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_K6_3_M32: #define __3dNOW__ 1
// CHECK_K6_3_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_K6_3_M32: #define __i386 1
// CHECK_K6_3_M32: #define __i386__ 1
// CHECK_K6_3_M32: #define __k6 1
// CHECK_K6_3_M32: #define __k6_3__ 1
// CHECK_K6_3_M32: #define __k6__ 1
// CHECK_K6_3_M32: #define __tune_k6_3__ 1
// CHECK_K6_3_M32: #define __tune_k6__ 1
// CHECK_K6_3_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=k6-3 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_3_M64
// CHECK_K6_3_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=athlon -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON_M32: #define __3dNOW_A__ 1
// CHECK_ATHLON_M32: #define __3dNOW__ 1
// CHECK_ATHLON_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON_M32: #define __athlon 1
// CHECK_ATHLON_M32: #define __athlon__ 1
// CHECK_ATHLON_M32: #define __i386 1
// CHECK_ATHLON_M32: #define __i386__ 1
// CHECK_ATHLON_M32: #define __tune_athlon__ 1
// CHECK_ATHLON_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=athlon -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_M64
// CHECK_ATHLON_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=athlon-tbird -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_TBIRD_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON_TBIRD_M32: #define __3dNOW_A__ 1
// CHECK_ATHLON_TBIRD_M32: #define __3dNOW__ 1
// CHECK_ATHLON_TBIRD_M32: #define __MMX__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON_TBIRD_M32: #define __athlon 1
// CHECK_ATHLON_TBIRD_M32: #define __athlon__ 1
// CHECK_ATHLON_TBIRD_M32: #define __i386 1
// CHECK_ATHLON_TBIRD_M32: #define __i386__ 1
// CHECK_ATHLON_TBIRD_M32: #define __tune_athlon__ 1
// CHECK_ATHLON_TBIRD_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=athlon-tbird -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_TBIRD_M64
// CHECK_ATHLON_TBIRD_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=athlon-4 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_4_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON_4_M32: #define __3dNOW_A__ 1
// CHECK_ATHLON_4_M32: #define __3dNOW__ 1
// CHECK_ATHLON_4_M32: #define __MMX__ 1
// CHECK_ATHLON_4_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON_4_M32: #define __athlon 1
// CHECK_ATHLON_4_M32: #define __athlon__ 1
// CHECK_ATHLON_4_M32: #define __athlon_sse__ 1
// CHECK_ATHLON_4_M32: #define __i386 1
// CHECK_ATHLON_4_M32: #define __i386__ 1
// CHECK_ATHLON_4_M32: #define __tune_athlon__ 1
Fix a think-o on my part that got enshrined in a FIXME by setting up the __tune_...__ define as well. llvm-svn: 140690
2011-09-28 17:54:11 +08:00
// CHECK_ATHLON_4_M32: #define __tune_athlon_sse__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON_4_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=athlon-4 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_4_M64
// CHECK_ATHLON_4_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=athlon-xp -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_XP_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON_XP_M32: #define __3dNOW_A__ 1
// CHECK_ATHLON_XP_M32: #define __3dNOW__ 1
// CHECK_ATHLON_XP_M32: #define __MMX__ 1
// CHECK_ATHLON_XP_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON_XP_M32: #define __athlon 1
// CHECK_ATHLON_XP_M32: #define __athlon__ 1
// CHECK_ATHLON_XP_M32: #define __athlon_sse__ 1
// CHECK_ATHLON_XP_M32: #define __i386 1
// CHECK_ATHLON_XP_M32: #define __i386__ 1
// CHECK_ATHLON_XP_M32: #define __tune_athlon__ 1
Fix a think-o on my part that got enshrined in a FIXME by setting up the __tune_...__ define as well. llvm-svn: 140690
2011-09-28 17:54:11 +08:00
// CHECK_ATHLON_XP_M32: #define __tune_athlon_sse__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON_XP_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=athlon-xp -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_XP_M64
// CHECK_ATHLON_XP_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=athlon-mp -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_MP_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON_MP_M32: #define __3dNOW_A__ 1
// CHECK_ATHLON_MP_M32: #define __3dNOW__ 1
// CHECK_ATHLON_MP_M32: #define __MMX__ 1
// CHECK_ATHLON_MP_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON_MP_M32: #define __athlon 1
// CHECK_ATHLON_MP_M32: #define __athlon__ 1
// CHECK_ATHLON_MP_M32: #define __athlon_sse__ 1
// CHECK_ATHLON_MP_M32: #define __i386 1
// CHECK_ATHLON_MP_M32: #define __i386__ 1
// CHECK_ATHLON_MP_M32: #define __tune_athlon__ 1
Fix a think-o on my part that got enshrined in a FIXME by setting up the __tune_...__ define as well. llvm-svn: 140690
2011-09-28 17:54:11 +08:00
// CHECK_ATHLON_MP_M32: #define __tune_athlon_sse__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON_MP_M32: #define i386 1
Add 'not' to commands that are expected to fail. This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
2013-07-05 00:16:58 +08:00
// RUN: not %clang -march=athlon-mp -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_MP_M64
// CHECK_ATHLON_MP_M64: error: {{.*}}
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=x86-64 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_X86_64_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_X86_64_M32: #define __MMX__ 1
// CHECK_X86_64_M32: #define __SSE2__ 1
// CHECK_X86_64_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_X86_64_M32: #define __i386 1
// CHECK_X86_64_M32: #define __i386__ 1
// CHECK_X86_64_M32: #define __k8 1
// CHECK_X86_64_M32: #define __k8__ 1
// CHECK_X86_64_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=k8 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K8_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_K8_M32: #define __3dNOW_A__ 1
// CHECK_K8_M32: #define __3dNOW__ 1
// CHECK_K8_M32: #define __MMX__ 1
// CHECK_K8_M32: #define __SSE2__ 1
// CHECK_K8_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_K8_M32: #define __i386 1
// CHECK_K8_M32: #define __i386__ 1
// CHECK_K8_M32: #define __k8 1
// CHECK_K8_M32: #define __k8__ 1
// CHECK_K8_M32: #define __tune_k8__ 1
// CHECK_K8_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=k8 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K8_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_K8_M64: #define __3dNOW_A__ 1
// CHECK_K8_M64: #define __3dNOW__ 1
// CHECK_K8_M64: #define __MMX__ 1
// CHECK_K8_M64: #define __SSE2_MATH__ 1
// CHECK_K8_M64: #define __SSE2__ 1
// CHECK_K8_M64: #define __SSE_MATH__ 1
// CHECK_K8_M64: #define __SSE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_K8_M64: #define __amd64 1
// CHECK_K8_M64: #define __amd64__ 1
// CHECK_K8_M64: #define __k8 1
// CHECK_K8_M64: #define __k8__ 1
// CHECK_K8_M64: #define __tune_k8__ 1
// CHECK_K8_M64: #define __x86_64 1
// CHECK_K8_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=k8-sse3 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K8_SSE3_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_K8_SSE3_M32: #define __3dNOW_A__ 1
// CHECK_K8_SSE3_M32: #define __3dNOW__ 1
// CHECK_K8_SSE3_M32: #define __MMX__ 1
// CHECK_K8_SSE3_M32: #define __SSE2__ 1
// CHECK_K8_SSE3_M32: #define __SSE3__ 1
// CHECK_K8_SSE3_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_K8_SSE3_M32: #define __i386 1
// CHECK_K8_SSE3_M32: #define __i386__ 1
// CHECK_K8_SSE3_M32: #define __k8 1
// CHECK_K8_SSE3_M32: #define __k8__ 1
// CHECK_K8_SSE3_M32: #define __tune_k8__ 1
// CHECK_K8_SSE3_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=k8-sse3 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K8_SSE3_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_K8_SSE3_M64: #define __3dNOW_A__ 1
// CHECK_K8_SSE3_M64: #define __3dNOW__ 1
// CHECK_K8_SSE3_M64: #define __MMX__ 1
// CHECK_K8_SSE3_M64: #define __SSE2_MATH__ 1
// CHECK_K8_SSE3_M64: #define __SSE2__ 1
// CHECK_K8_SSE3_M64: #define __SSE3__ 1
// CHECK_K8_SSE3_M64: #define __SSE_MATH__ 1
// CHECK_K8_SSE3_M64: #define __SSE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_K8_SSE3_M64: #define __amd64 1
// CHECK_K8_SSE3_M64: #define __amd64__ 1
// CHECK_K8_SSE3_M64: #define __k8 1
// CHECK_K8_SSE3_M64: #define __k8__ 1
// CHECK_K8_SSE3_M64: #define __tune_k8__ 1
// CHECK_K8_SSE3_M64: #define __x86_64 1
// CHECK_K8_SSE3_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=opteron -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_OPTERON_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_OPTERON_M32: #define __3dNOW_A__ 1
// CHECK_OPTERON_M32: #define __3dNOW__ 1
// CHECK_OPTERON_M32: #define __MMX__ 1
// CHECK_OPTERON_M32: #define __SSE2__ 1
// CHECK_OPTERON_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_OPTERON_M32: #define __i386 1
// CHECK_OPTERON_M32: #define __i386__ 1
// CHECK_OPTERON_M32: #define __k8 1
// CHECK_OPTERON_M32: #define __k8__ 1
// CHECK_OPTERON_M32: #define __tune_k8__ 1
// CHECK_OPTERON_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=opteron -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_OPTERON_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_OPTERON_M64: #define __3dNOW_A__ 1
// CHECK_OPTERON_M64: #define __3dNOW__ 1
// CHECK_OPTERON_M64: #define __MMX__ 1
// CHECK_OPTERON_M64: #define __SSE2_MATH__ 1
// CHECK_OPTERON_M64: #define __SSE2__ 1
// CHECK_OPTERON_M64: #define __SSE_MATH__ 1
// CHECK_OPTERON_M64: #define __SSE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_OPTERON_M64: #define __amd64 1
// CHECK_OPTERON_M64: #define __amd64__ 1
// CHECK_OPTERON_M64: #define __k8 1
// CHECK_OPTERON_M64: #define __k8__ 1
// CHECK_OPTERON_M64: #define __tune_k8__ 1
// CHECK_OPTERON_M64: #define __x86_64 1
// CHECK_OPTERON_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=opteron-sse3 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_OPTERON_SSE3_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_OPTERON_SSE3_M32: #define __3dNOW_A__ 1
// CHECK_OPTERON_SSE3_M32: #define __3dNOW__ 1
// CHECK_OPTERON_SSE3_M32: #define __MMX__ 1
// CHECK_OPTERON_SSE3_M32: #define __SSE2__ 1
// CHECK_OPTERON_SSE3_M32: #define __SSE3__ 1
// CHECK_OPTERON_SSE3_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_OPTERON_SSE3_M32: #define __i386 1
// CHECK_OPTERON_SSE3_M32: #define __i386__ 1
// CHECK_OPTERON_SSE3_M32: #define __k8 1
// CHECK_OPTERON_SSE3_M32: #define __k8__ 1
// CHECK_OPTERON_SSE3_M32: #define __tune_k8__ 1
// CHECK_OPTERON_SSE3_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=opteron-sse3 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_OPTERON_SSE3_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_OPTERON_SSE3_M64: #define __3dNOW_A__ 1
// CHECK_OPTERON_SSE3_M64: #define __3dNOW__ 1
// CHECK_OPTERON_SSE3_M64: #define __MMX__ 1
// CHECK_OPTERON_SSE3_M64: #define __SSE2_MATH__ 1
// CHECK_OPTERON_SSE3_M64: #define __SSE2__ 1
// CHECK_OPTERON_SSE3_M64: #define __SSE3__ 1
// CHECK_OPTERON_SSE3_M64: #define __SSE_MATH__ 1
// CHECK_OPTERON_SSE3_M64: #define __SSE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_OPTERON_SSE3_M64: #define __amd64 1
// CHECK_OPTERON_SSE3_M64: #define __amd64__ 1
// CHECK_OPTERON_SSE3_M64: #define __k8 1
// CHECK_OPTERON_SSE3_M64: #define __k8__ 1
// CHECK_OPTERON_SSE3_M64: #define __tune_k8__ 1
// CHECK_OPTERON_SSE3_M64: #define __x86_64 1
// CHECK_OPTERON_SSE3_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=athlon64 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON64_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON64_M32: #define __3dNOW_A__ 1
// CHECK_ATHLON64_M32: #define __3dNOW__ 1
// CHECK_ATHLON64_M32: #define __MMX__ 1
// CHECK_ATHLON64_M32: #define __SSE2__ 1
// CHECK_ATHLON64_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON64_M32: #define __i386 1
// CHECK_ATHLON64_M32: #define __i386__ 1
// CHECK_ATHLON64_M32: #define __k8 1
// CHECK_ATHLON64_M32: #define __k8__ 1
// CHECK_ATHLON64_M32: #define __tune_k8__ 1
// CHECK_ATHLON64_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=athlon64 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON64_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON64_M64: #define __3dNOW_A__ 1
// CHECK_ATHLON64_M64: #define __3dNOW__ 1
// CHECK_ATHLON64_M64: #define __MMX__ 1
// CHECK_ATHLON64_M64: #define __SSE2_MATH__ 1
// CHECK_ATHLON64_M64: #define __SSE2__ 1
// CHECK_ATHLON64_M64: #define __SSE_MATH__ 1
// CHECK_ATHLON64_M64: #define __SSE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_ATHLON64_M64: #define __amd64 1
// CHECK_ATHLON64_M64: #define __amd64__ 1
// CHECK_ATHLON64_M64: #define __k8 1
// CHECK_ATHLON64_M64: #define __k8__ 1
// CHECK_ATHLON64_M64: #define __tune_k8__ 1
// CHECK_ATHLON64_M64: #define __x86_64 1
// CHECK_ATHLON64_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=athlon64-sse3 -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON64_SSE3_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON64_SSE3_M32: #define __3dNOW_A__ 1
// CHECK_ATHLON64_SSE3_M32: #define __3dNOW__ 1
// CHECK_ATHLON64_SSE3_M32: #define __MMX__ 1
// CHECK_ATHLON64_SSE3_M32: #define __SSE2__ 1
// CHECK_ATHLON64_SSE3_M32: #define __SSE3__ 1
// CHECK_ATHLON64_SSE3_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON64_SSE3_M32: #define __i386 1
// CHECK_ATHLON64_SSE3_M32: #define __i386__ 1
// CHECK_ATHLON64_SSE3_M32: #define __k8 1
// CHECK_ATHLON64_SSE3_M32: #define __k8__ 1
// CHECK_ATHLON64_SSE3_M32: #define __tune_k8__ 1
// CHECK_ATHLON64_SSE3_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=athlon64-sse3 -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON64_SSE3_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON64_SSE3_M64: #define __3dNOW_A__ 1
// CHECK_ATHLON64_SSE3_M64: #define __3dNOW__ 1
// CHECK_ATHLON64_SSE3_M64: #define __MMX__ 1
// CHECK_ATHLON64_SSE3_M64: #define __SSE2_MATH__ 1
// CHECK_ATHLON64_SSE3_M64: #define __SSE2__ 1
// CHECK_ATHLON64_SSE3_M64: #define __SSE3__ 1
// CHECK_ATHLON64_SSE3_M64: #define __SSE_MATH__ 1
// CHECK_ATHLON64_SSE3_M64: #define __SSE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_ATHLON64_SSE3_M64: #define __amd64 1
// CHECK_ATHLON64_SSE3_M64: #define __amd64__ 1
// CHECK_ATHLON64_SSE3_M64: #define __k8 1
// CHECK_ATHLON64_SSE3_M64: #define __k8__ 1
// CHECK_ATHLON64_SSE3_M64: #define __tune_k8__ 1
// CHECK_ATHLON64_SSE3_M64: #define __x86_64 1
// CHECK_ATHLON64_SSE3_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// RUN: %clang -march=athlon-fx -m32 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_FX_M32
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON_FX_M32: #define __3dNOW_A__ 1
// CHECK_ATHLON_FX_M32: #define __3dNOW__ 1
// CHECK_ATHLON_FX_M32: #define __MMX__ 1
// CHECK_ATHLON_FX_M32: #define __SSE2__ 1
// CHECK_ATHLON_FX_M32: #define __SSE__ 1
Begin fixing Clang's predefined macros for various architectures. This is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
2011-09-28 10:59:25 +08:00
// CHECK_ATHLON_FX_M32: #define __i386 1
// CHECK_ATHLON_FX_M32: #define __i386__ 1
// CHECK_ATHLON_FX_M32: #define __k8 1
// CHECK_ATHLON_FX_M32: #define __k8__ 1
// CHECK_ATHLON_FX_M32: #define __tune_k8__ 1
// CHECK_ATHLON_FX_M32: #define i386 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// RUN: %clang -march=athlon-fx -m64 -E -dM %s -o - 2>&1 \
Pass a target triple explicitly to check platform specific macros definitions. That allows to run the tests on all platforms successfully. llvm-svn: 156500
2012-05-10 02:49:52 +08:00
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_FX_M64
Generate tests for all of the x86 SIMD instruction feature set predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
2011-09-28 18:36:46 +08:00
// CHECK_ATHLON_FX_M64: #define __3dNOW_A__ 1
// CHECK_ATHLON_FX_M64: #define __3dNOW__ 1
// CHECK_ATHLON_FX_M64: #define __MMX__ 1
// CHECK_ATHLON_FX_M64: #define __SSE2_MATH__ 1
// CHECK_ATHLON_FX_M64: #define __SSE2__ 1
// CHECK_ATHLON_FX_M64: #define __SSE_MATH__ 1
// CHECK_ATHLON_FX_M64: #define __SSE__ 1
Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode. Add 64-bit preprocessor macro tests. llvm-svn: 140688
2011-09-28 17:45:08 +08:00
// CHECK_ATHLON_FX_M64: #define __amd64 1
// CHECK_ATHLON_FX_M64: #define __amd64__ 1
// CHECK_ATHLON_FX_M64: #define __k8 1
// CHECK_ATHLON_FX_M64: #define __k8__ 1
// CHECK_ATHLON_FX_M64: #define __tune_k8__ 1
// CHECK_ATHLON_FX_M64: #define __x86_64 1
// CHECK_ATHLON_FX_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// RUN: %clang -march=amdfam10 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_AMDFAM10_M32
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_AMDFAM10_M32: #define __3dNOW_A__ 1
// CHECK_AMDFAM10_M32: #define __3dNOW__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_AMDFAM10_M32: #define __LAHF_SAHF__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_AMDFAM10_M32: #define __LZCNT__ 1
// CHECK_AMDFAM10_M32: #define __MMX__ 1
// CHECK_AMDFAM10_M32: #define __POPCNT__ 1
[X86] Don't imply -mprfchw when -m3dnow is specified. Enable prefetchw in the backend with 3dnow feature. The PREFETCHW instruction was originally part of the 3DNow. But it was given its own CPUID bit on later CPUs just before 3DNow was deprecated. We were setting the -mprfchw flag if -m3dnow was passed or the CPU supported 3dnow unless -mno-prfchw was passed. But -march=native on a CPU without the PRFCHW CPUID bit set will pass -mno-prfchw. So -march=k8 will behave differently than -march=native on a K8 for example. So remove this implicit setting from the frontend and instead enable the backend to use PREFETCHW if 3dnow OR prfchw is enabled. Also enable PRFCHW flag on amdfam10/barcelona which seems to be where this CPUID bit was introduced. That CPU also supported 3dnow.
2020-06-26 02:45:09 +08:00
// CHECK_AMDFAM10_M32: #define __PRFCHW__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_AMDFAM10_M32: #define __SSE2_MATH__ 1
// CHECK_AMDFAM10_M32: #define __SSE2__ 1
// CHECK_AMDFAM10_M32: #define __SSE3__ 1
// CHECK_AMDFAM10_M32: #define __SSE4A__ 1
// CHECK_AMDFAM10_M32: #define __SSE_MATH__ 1
// CHECK_AMDFAM10_M32: #define __SSE__ 1
[X86] SSE4_A should only imply SSE3 not SSSE3 in the frontend. SSE4_1 and SSE4_2 due imply SSSE3. So I guess I got confused when switching the code to being table based in D83273. Fixes PR47464
2020-09-09 01:49:32 +08:00
// CHECK_AMDFAM10_M32-NOT: #define __SSSE3__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_AMDFAM10_M32: #define __amdfam10 1
// CHECK_AMDFAM10_M32: #define __amdfam10__ 1
// CHECK_AMDFAM10_M32: #define __i386 1
// CHECK_AMDFAM10_M32: #define __i386__ 1
// CHECK_AMDFAM10_M32: #define __tune_amdfam10__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// RUN: %clang -march=amdfam10 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_AMDFAM10_M64
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// CHECK_AMDFAM10_M64: #define __3dNOW_A__ 1
// CHECK_AMDFAM10_M64: #define __3dNOW__ 1
[X86] Add CMPXCHG16B feature to amdfam10 in the frontend. We already have this feature on it in the backend.
2020-06-26 13:55:36 +08:00
// CHECK_AMDFAM10_M64: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_AMDFAM10_M64: #define __LAHF_SAHF__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_AMDFAM10_M64: #define __LZCNT__ 1
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// CHECK_AMDFAM10_M64: #define __MMX__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_AMDFAM10_M64: #define __POPCNT__ 1
[X86] Don't imply -mprfchw when -m3dnow is specified. Enable prefetchw in the backend with 3dnow feature. The PREFETCHW instruction was originally part of the 3DNow. But it was given its own CPUID bit on later CPUs just before 3DNow was deprecated. We were setting the -mprfchw flag if -m3dnow was passed or the CPU supported 3dnow unless -mno-prfchw was passed. But -march=native on a CPU without the PRFCHW CPUID bit set will pass -mno-prfchw. So -march=k8 will behave differently than -march=native on a K8 for example. So remove this implicit setting from the frontend and instead enable the backend to use PREFETCHW if 3dnow OR prfchw is enabled. Also enable PRFCHW flag on amdfam10/barcelona which seems to be where this CPUID bit was introduced. That CPU also supported 3dnow.
2020-06-26 02:45:09 +08:00
// CHECK_AMDFAM10_M64: #define __PRFCHW__ 1
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// CHECK_AMDFAM10_M64: #define __SSE2_MATH__ 1
// CHECK_AMDFAM10_M64: #define __SSE2__ 1
// CHECK_AMDFAM10_M64: #define __SSE3__ 1
// CHECK_AMDFAM10_M64: #define __SSE4A__ 1
// CHECK_AMDFAM10_M64: #define __SSE_MATH__ 1
// CHECK_AMDFAM10_M64: #define __SSE__ 1
[X86] SSE4_A should only imply SSE3 not SSSE3 in the frontend. SSE4_1 and SSE4_2 due imply SSSE3. So I guess I got confused when switching the code to being table based in D83273. Fixes PR47464
2020-09-09 01:49:32 +08:00
// CHECK_AMDFAM10_M64-NOT: #define __SSSE3__ 1
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// CHECK_AMDFAM10_M64: #define __amd64 1
// CHECK_AMDFAM10_M64: #define __amd64__ 1
// CHECK_AMDFAM10_M64: #define __amdfam10 1
// CHECK_AMDFAM10_M64: #define __amdfam10__ 1
// CHECK_AMDFAM10_M64: #define __tune_amdfam10__ 1
// CHECK_AMDFAM10_M64: #define __x86_64 1
// CHECK_AMDFAM10_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// RUN: %clang -march=btver1 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER1_M32
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BTVER1_M32-NOT: #define __3dNOW_A__ 1
// CHECK_BTVER1_M32-NOT: #define __3dNOW__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_BTVER1_M32: #define __LAHF_SAHF__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BTVER1_M32: #define __LZCNT__ 1
// CHECK_BTVER1_M32: #define __MMX__ 1
// CHECK_BTVER1_M32: #define __POPCNT__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// CHECK_BTVER1_M32: #define __PRFCHW__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BTVER1_M32: #define __SSE2_MATH__ 1
// CHECK_BTVER1_M32: #define __SSE2__ 1
// CHECK_BTVER1_M32: #define __SSE3__ 1
// CHECK_BTVER1_M32: #define __SSE4A__ 1
// CHECK_BTVER1_M32: #define __SSE_MATH__ 1
// CHECK_BTVER1_M32: #define __SSE__ 1
// CHECK_BTVER1_M32: #define __SSSE3__ 1
// CHECK_BTVER1_M32: #define __btver1 1
// CHECK_BTVER1_M32: #define __btver1__ 1
// CHECK_BTVER1_M32: #define __i386 1
// CHECK_BTVER1_M32: #define __i386__ 1
// CHECK_BTVER1_M32: #define __tune_btver1__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// RUN: %clang -march=btver1 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER1_M64
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BTVER1_M64-NOT: #define __3dNOW_A__ 1
// CHECK_BTVER1_M64-NOT: #define __3dNOW__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_BTVER1_M64: #define __LAHF_SAHF__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BTVER1_M64: #define __LZCNT__ 1
// CHECK_BTVER1_M64: #define __MMX__ 1
// CHECK_BTVER1_M64: #define __POPCNT__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// CHECK_BTVER1_M64: #define __PRFCHW__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BTVER1_M64: #define __SSE2_MATH__ 1
// CHECK_BTVER1_M64: #define __SSE2__ 1
// CHECK_BTVER1_M64: #define __SSE3__ 1
// CHECK_BTVER1_M64: #define __SSE4A__ 1
// CHECK_BTVER1_M64: #define __SSE_MATH__ 1
// CHECK_BTVER1_M64: #define __SSE__ 1
// CHECK_BTVER1_M64: #define __SSSE3__ 1
// CHECK_BTVER1_M64: #define __amd64 1
// CHECK_BTVER1_M64: #define __amd64__ 1
// CHECK_BTVER1_M64: #define __btver1 1
// CHECK_BTVER1_M64: #define __btver1__ 1
// CHECK_BTVER1_M64: #define __tune_btver1__ 1
// CHECK_BTVER1_M64: #define __x86_64 1
// CHECK_BTVER1_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// RUN: %clang -march=btver2 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER2_M32
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M32-NOT: #define __3dNOW_A__ 1
// CHECK_BTVER2_M32-NOT: #define __3dNOW__ 1
// CHECK_BTVER2_M32: #define __AES__ 1
// CHECK_BTVER2_M32: #define __AVX__ 1
[X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
2014-11-06 20:08:57 +08:00
// CHECK_BTVER2_M32: #define __BMI__ 1
// CHECK_BTVER2_M32: #define __F16C__ 1
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M32: #define __LZCNT__ 1
// CHECK_BTVER2_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_BTVER2_M32: #define __MOVBE__ 1
[X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
2014-11-06 20:08:57 +08:00
// CHECK_BTVER2_M32: #define __PCLMUL__ 1
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M32: #define __POPCNT__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// CHECK_BTVER2_M32: #define __PRFCHW__ 1
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M32: #define __SSE2_MATH__ 1
// CHECK_BTVER2_M32: #define __SSE2__ 1
// CHECK_BTVER2_M32: #define __SSE3__ 1
// CHECK_BTVER2_M32: #define __SSE4A__ 1
// CHECK_BTVER2_M32: #define __SSE_MATH__ 1
// CHECK_BTVER2_M32: #define __SSE__ 1
// CHECK_BTVER2_M32: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BTVER2_M32: #define __XSAVEOPT__ 1
// CHECK_BTVER2_M32: #define __XSAVE__ 1
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M32: #define __btver2 1
// CHECK_BTVER2_M32: #define __btver2__ 1
// CHECK_BTVER2_M32: #define __i386 1
// CHECK_BTVER2_M32: #define __i386__ 1
// CHECK_BTVER2_M32: #define __tune_btver2__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// RUN: %clang -march=btver2 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER2_M64
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M64-NOT: #define __3dNOW_A__ 1
// CHECK_BTVER2_M64-NOT: #define __3dNOW__ 1
// CHECK_BTVER2_M64: #define __AES__ 1
// CHECK_BTVER2_M64: #define __AVX__ 1
[X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
2014-11-06 20:08:57 +08:00
// CHECK_BTVER2_M64: #define __BMI__ 1
// CHECK_BTVER2_M64: #define __F16C__ 1
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M64: #define __LZCNT__ 1
// CHECK_BTVER2_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_BTVER2_M64: #define __MOVBE__ 1
[X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
2014-11-06 20:08:57 +08:00
// CHECK_BTVER2_M64: #define __PCLMUL__ 1
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M64: #define __POPCNT__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// CHECK_BTVER2_M64: #define __PRFCHW__ 1
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M64: #define __SSE2_MATH__ 1
// CHECK_BTVER2_M64: #define __SSE2__ 1
// CHECK_BTVER2_M64: #define __SSE3__ 1
// CHECK_BTVER2_M64: #define __SSE4A__ 1
// CHECK_BTVER2_M64: #define __SSE_MATH__ 1
// CHECK_BTVER2_M64: #define __SSE__ 1
// CHECK_BTVER2_M64: #define __SSSE3__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BTVER2_M64: #define __XSAVEOPT__ 1
// CHECK_BTVER2_M64: #define __XSAVE__ 1
Add support for -march=btver2. llvm-svn: 181006
2013-05-03 18:47:15 +08:00
// CHECK_BTVER2_M64: #define __amd64 1
// CHECK_BTVER2_M64: #define __amd64__ 1
// CHECK_BTVER2_M64: #define __btver2 1
// CHECK_BTVER2_M64: #define __btver2__ 1
// CHECK_BTVER2_M64: #define __tune_btver2__ 1
// CHECK_BTVER2_M64: #define __x86_64 1
// CHECK_BTVER2_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// RUN: %clang -march=bdver1 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER1_M32
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER1_M32-NOT: #define __3dNOW_A__ 1
// CHECK_BDVER1_M32-NOT: #define __3dNOW__ 1
// CHECK_BDVER1_M32: #define __AES__ 1
// CHECK_BDVER1_M32: #define __AVX__ 1
// CHECK_BDVER1_M32: #define __FMA4__ 1
[X86][LWP] Add __LWP__ macro tests Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
2017-05-09 01:25:48 +08:00
// CHECK_BDVER1_M32: #define __LWP__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER1_M32: #define __LZCNT__ 1
// CHECK_BDVER1_M32: #define __MMX__ 1
// CHECK_BDVER1_M32: #define __PCLMUL__ 1
// CHECK_BDVER1_M32: #define __POPCNT__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// CHECK_BDVER1_M32: #define __PRFCHW__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER1_M32: #define __SSE2_MATH__ 1
// CHECK_BDVER1_M32: #define __SSE2__ 1
// CHECK_BDVER1_M32: #define __SSE3__ 1
// CHECK_BDVER1_M32: #define __SSE4A__ 1
// CHECK_BDVER1_M32: #define __SSE4_1__ 1
// CHECK_BDVER1_M32: #define __SSE4_2__ 1
// CHECK_BDVER1_M32: #define __SSE_MATH__ 1
// CHECK_BDVER1_M32: #define __SSE__ 1
// CHECK_BDVER1_M32: #define __SSSE3__ 1
// CHECK_BDVER1_M32: #define __XOP__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BDVER1_M32: #define __XSAVE__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER1_M32: #define __bdver1 1
// CHECK_BDVER1_M32: #define __bdver1__ 1
// CHECK_BDVER1_M32: #define __i386 1
// CHECK_BDVER1_M32: #define __i386__ 1
// CHECK_BDVER1_M32: #define __tune_bdver1__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// RUN: %clang -march=bdver1 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER1_M64
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// CHECK_BDVER1_M64-NOT: #define __3dNOW_A__ 1
// CHECK_BDVER1_M64-NOT: #define __3dNOW__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER1_M64: #define __AES__ 1
// CHECK_BDVER1_M64: #define __AVX__ 1
Add XOP feature flag. llvm-svn: 158284
2012-06-10 06:24:14 +08:00
// CHECK_BDVER1_M64: #define __FMA4__ 1
[X86][LWP] Add __LWP__ macro tests Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
2017-05-09 01:25:48 +08:00
// CHECK_BDVER1_M64: #define __LWP__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER1_M64: #define __LZCNT__ 1
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// CHECK_BDVER1_M64: #define __MMX__ 1
Add XOP feature flag. llvm-svn: 158284
2012-06-10 06:24:14 +08:00
// CHECK_BDVER1_M64: #define __PCLMUL__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER1_M64: #define __POPCNT__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// CHECK_BDVER1_M64: #define __PRFCHW__ 1
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// CHECK_BDVER1_M64: #define __SSE2_MATH__ 1
// CHECK_BDVER1_M64: #define __SSE2__ 1
// CHECK_BDVER1_M64: #define __SSE3__ 1
// CHECK_BDVER1_M64: #define __SSE4A__ 1
// CHECK_BDVER1_M64: #define __SSE4_1__ 1
// CHECK_BDVER1_M64: #define __SSE4_2__ 1
// CHECK_BDVER1_M64: #define __SSE_MATH__ 1
// CHECK_BDVER1_M64: #define __SSE__ 1
// CHECK_BDVER1_M64: #define __SSSE3__ 1
Add XOP feature flag. llvm-svn: 158284
2012-06-10 06:24:14 +08:00
// CHECK_BDVER1_M64: #define __XOP__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BDVER1_M64: #define __XSAVE__ 1
Define __SSE4A__ when targeting new AMD CPUs. This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
2012-05-30 01:48:39 +08:00
// CHECK_BDVER1_M64: #define __amd64 1
// CHECK_BDVER1_M64: #define __amd64__ 1
// CHECK_BDVER1_M64: #define __bdver1 1
// CHECK_BDVER1_M64: #define __bdver1__ 1
// CHECK_BDVER1_M64: #define __tune_bdver1__ 1
// CHECK_BDVER1_M64: #define __x86_64 1
// CHECK_BDVER1_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// RUN: %clang -march=bdver2 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER2_M32
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M32-NOT: #define __3dNOW_A__ 1
// CHECK_BDVER2_M32-NOT: #define __3dNOW__ 1
// CHECK_BDVER2_M32: #define __AES__ 1
// CHECK_BDVER2_M32: #define __AVX__ 1
// CHECK_BDVER2_M32: #define __BMI__ 1
// CHECK_BDVER2_M32: #define __F16C__ 1
// CHECK_BDVER2_M32: #define __FMA4__ 1
// CHECK_BDVER2_M32: #define __FMA__ 1
[X86][LWP] Add __LWP__ macro tests Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
2017-05-09 01:25:48 +08:00
// CHECK_BDVER2_M32: #define __LWP__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M32: #define __LZCNT__ 1
// CHECK_BDVER2_M32: #define __MMX__ 1
// CHECK_BDVER2_M32: #define __PCLMUL__ 1
// CHECK_BDVER2_M32: #define __POPCNT__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// CHECK_BDVER2_M32: #define __PRFCHW__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M32: #define __SSE2_MATH__ 1
// CHECK_BDVER2_M32: #define __SSE2__ 1
// CHECK_BDVER2_M32: #define __SSE3__ 1
// CHECK_BDVER2_M32: #define __SSE4A__ 1
// CHECK_BDVER2_M32: #define __SSE4_1__ 1
// CHECK_BDVER2_M32: #define __SSE4_2__ 1
// CHECK_BDVER2_M32: #define __SSE_MATH__ 1
// CHECK_BDVER2_M32: #define __SSE__ 1
// CHECK_BDVER2_M32: #define __SSSE3__ 1
Adding -mtbm and -mno-tbm command line options to the clang front end for the x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is enabled. Otherwise there should be no functionality change to existing features. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693 llvm-svn: 191326
2013-09-25 03:00:58 +08:00
// CHECK_BDVER2_M32: #define __TBM__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M32: #define __XOP__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BDVER2_M32: #define __XSAVE__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M32: #define __bdver2 1
// CHECK_BDVER2_M32: #define __bdver2__ 1
// CHECK_BDVER2_M32: #define __i386 1
// CHECK_BDVER2_M32: #define __i386__ 1
// CHECK_BDVER2_M32: #define __tune_bdver2__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// RUN: %clang -march=bdver2 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER2_M64
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M64-NOT: #define __3dNOW_A__ 1
// CHECK_BDVER2_M64-NOT: #define __3dNOW__ 1
// CHECK_BDVER2_M64: #define __AES__ 1
// CHECK_BDVER2_M64: #define __AVX__ 1
// CHECK_BDVER2_M64: #define __BMI__ 1
// CHECK_BDVER2_M64: #define __F16C__ 1
// CHECK_BDVER2_M64: #define __FMA4__ 1
// CHECK_BDVER2_M64: #define __FMA__ 1
[X86][LWP] Add __LWP__ macro tests Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
2017-05-09 01:25:48 +08:00
// CHECK_BDVER2_M64: #define __LWP__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M64: #define __LZCNT__ 1
// CHECK_BDVER2_M64: #define __MMX__ 1
// CHECK_BDVER2_M64: #define __PCLMUL__ 1
// CHECK_BDVER2_M64: #define __POPCNT__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// CHECK_BDVER2_M64: #define __PRFCHW__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M64: #define __SSE2_MATH__ 1
// CHECK_BDVER2_M64: #define __SSE2__ 1
// CHECK_BDVER2_M64: #define __SSE3__ 1
// CHECK_BDVER2_M64: #define __SSE4A__ 1
// CHECK_BDVER2_M64: #define __SSE4_1__ 1
// CHECK_BDVER2_M64: #define __SSE4_2__ 1
// CHECK_BDVER2_M64: #define __SSE_MATH__ 1
// CHECK_BDVER2_M64: #define __SSE__ 1
// CHECK_BDVER2_M64: #define __SSSE3__ 1
Adding -mtbm and -mno-tbm command line options to the clang front end for the x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is enabled. Otherwise there should be no functionality change to existing features. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693 llvm-svn: 191326
2013-09-25 03:00:58 +08:00
// CHECK_BDVER2_M64: #define __TBM__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M64: #define __XOP__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BDVER2_M64: #define __XSAVE__ 1
Add missing features for misc x86 CPUs to CPU feature translation. Patch by Jung-uk Kim. llvm-svn: 168239
2012-11-17 09:43:10 +08:00
// CHECK_BDVER2_M64: #define __amd64 1
// CHECK_BDVER2_M64: #define __amd64__ 1
// CHECK_BDVER2_M64: #define __bdver2 1
// CHECK_BDVER2_M64: #define __bdver2__ 1
// CHECK_BDVER2_M64: #define __tune_bdver2__ 1
// CHECK_BDVER2_M64: #define __x86_64 1
// CHECK_BDVER2_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Driver: Add support for -march=bdver3 on x86. llvm-svn: 193985
2013-11-04 18:29:51 +08:00
// RUN: %clang -march=bdver3 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER3_M32
Driver: Add support for -march=bdver3 on x86. llvm-svn: 193985
2013-11-04 18:29:51 +08:00
// CHECK_BDVER3_M32-NOT: #define __3dNOW_A__ 1
// CHECK_BDVER3_M32-NOT: #define __3dNOW__ 1
// CHECK_BDVER3_M32: #define __AES__ 1
// CHECK_BDVER3_M32: #define __AVX__ 1
// CHECK_BDVER3_M32: #define __BMI__ 1
// CHECK_BDVER3_M32: #define __F16C__ 1
// CHECK_BDVER3_M32: #define __FMA4__ 1
// CHECK_BDVER3_M32: #define __FMA__ 1
[X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
2014-11-06 20:08:57 +08:00
// CHECK_BDVER3_M32: #define __FSGSBASE__ 1
[X86][LWP] Add __LWP__ macro tests Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
2017-05-09 01:25:48 +08:00
// CHECK_BDVER3_M32: #define __LWP__ 1
Driver: Add support for -march=bdver3 on x86. llvm-svn: 193985
2013-11-04 18:29:51 +08:00
// CHECK_BDVER3_M32: #define __LZCNT__ 1
// CHECK_BDVER3_M32: #define __MMX__ 1
// CHECK_BDVER3_M32: #define __PCLMUL__ 1
// CHECK_BDVER3_M32: #define __POPCNT__ 1
// CHECK_BDVER3_M32: #define __PRFCHW__ 1
// CHECK_BDVER3_M32: #define __SSE2_MATH__ 1
// CHECK_BDVER3_M32: #define __SSE2__ 1
// CHECK_BDVER3_M32: #define __SSE3__ 1
// CHECK_BDVER3_M32: #define __SSE4A__ 1
// CHECK_BDVER3_M32: #define __SSE4_1__ 1
// CHECK_BDVER3_M32: #define __SSE4_2__ 1
// CHECK_BDVER3_M32: #define __SSE_MATH__ 1
// CHECK_BDVER3_M32: #define __SSE__ 1
// CHECK_BDVER3_M32: #define __SSSE3__ 1
// CHECK_BDVER3_M32: #define __TBM__ 1
// CHECK_BDVER3_M32: #define __XOP__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BDVER3_M32: #define __XSAVEOPT__ 1
// CHECK_BDVER3_M32: #define __XSAVE__ 1
Driver: Add support for -march=bdver3 on x86. llvm-svn: 193985
2013-11-04 18:29:51 +08:00
// CHECK_BDVER3_M32: #define __bdver3 1
// CHECK_BDVER3_M32: #define __bdver3__ 1
// CHECK_BDVER3_M32: #define __i386 1
// CHECK_BDVER3_M32: #define __i386__ 1
// CHECK_BDVER3_M32: #define __tune_bdver3__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Driver: Add support for -march=bdver3 on x86. llvm-svn: 193985
2013-11-04 18:29:51 +08:00
// RUN: %clang -march=bdver3 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER3_M64
Driver: Add support for -march=bdver3 on x86. llvm-svn: 193985
2013-11-04 18:29:51 +08:00
// CHECK_BDVER3_M64-NOT: #define __3dNOW_A__ 1
// CHECK_BDVER3_M64-NOT: #define __3dNOW__ 1
// CHECK_BDVER3_M64: #define __AES__ 1
// CHECK_BDVER3_M64: #define __AVX__ 1
// CHECK_BDVER3_M64: #define __BMI__ 1
// CHECK_BDVER3_M64: #define __F16C__ 1
// CHECK_BDVER3_M64: #define __FMA4__ 1
// CHECK_BDVER3_M64: #define __FMA__ 1
[X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
2014-11-06 20:08:57 +08:00
// CHECK_BDVER3_M64: #define __FSGSBASE__ 1
[X86][LWP] Add __LWP__ macro tests Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
2017-05-09 01:25:48 +08:00
// CHECK_BDVER3_M64: #define __LWP__ 1
Driver: Add support for -march=bdver3 on x86. llvm-svn: 193985
2013-11-04 18:29:51 +08:00
// CHECK_BDVER3_M64: #define __LZCNT__ 1
// CHECK_BDVER3_M64: #define __MMX__ 1
// CHECK_BDVER3_M64: #define __PCLMUL__ 1
// CHECK_BDVER3_M64: #define __POPCNT__ 1
// CHECK_BDVER3_M64: #define __PRFCHW__ 1
// CHECK_BDVER3_M64: #define __SSE2_MATH__ 1
// CHECK_BDVER3_M64: #define __SSE2__ 1
// CHECK_BDVER3_M64: #define __SSE3__ 1
// CHECK_BDVER3_M64: #define __SSE4A__ 1
// CHECK_BDVER3_M64: #define __SSE4_1__ 1
// CHECK_BDVER3_M64: #define __SSE4_2__ 1
// CHECK_BDVER3_M64: #define __SSE_MATH__ 1
// CHECK_BDVER3_M64: #define __SSE__ 1
// CHECK_BDVER3_M64: #define __SSSE3__ 1
// CHECK_BDVER3_M64: #define __TBM__ 1
// CHECK_BDVER3_M64: #define __XOP__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BDVER3_M64: #define __XSAVEOPT__ 1
// CHECK_BDVER3_M64: #define __XSAVE__ 1
Driver: Add support for -march=bdver3 on x86. llvm-svn: 193985
2013-11-04 18:29:51 +08:00
// CHECK_BDVER3_M64: #define __amd64 1
// CHECK_BDVER3_M64: #define __amd64__ 1
// CHECK_BDVER3_M64: #define __bdver3 1
// CHECK_BDVER3_M64: #define __bdver3__ 1
// CHECK_BDVER3_M64: #define __tune_bdver3__ 1
// CHECK_BDVER3_M64: #define __x86_64 1
// CHECK_BDVER3_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// RUN: %clang -march=bdver4 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER4_M32
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M32-NOT: #define __3dNOW_A__ 1
// CHECK_BDVER4_M32-NOT: #define __3dNOW__ 1
// CHECK_BDVER4_M32: #define __AES__ 1
// CHECK_BDVER4_M32: #define __AVX2__ 1
// CHECK_BDVER4_M32: #define __AVX__ 1
// CHECK_BDVER4_M32: #define __BMI2__ 1
// CHECK_BDVER4_M32: #define __BMI__ 1
// CHECK_BDVER4_M32: #define __F16C__ 1
// CHECK_BDVER4_M32: #define __FMA4__ 1
// CHECK_BDVER4_M32: #define __FMA__ 1
[X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
2014-11-06 20:08:57 +08:00
// CHECK_BDVER4_M32: #define __FSGSBASE__ 1
[X86][LWP] Add __LWP__ macro tests Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
2017-05-09 01:25:48 +08:00
// CHECK_BDVER4_M32: #define __LWP__ 1
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M32: #define __LZCNT__ 1
// CHECK_BDVER4_M32: #define __MMX__ 1
[X86] Add MOVBE and RDRND features to BDVER4. Only 6 years behind gcc. https://gcc.gnu.org/legacy-ml/gcc-patches/2014-08/msg00231.html Found while working on improving how we define CPU features for clang and auditing for correctness.
2020-06-27 14:32:17 +08:00
// CHECK_BDVER4_M32: #define __MOVBE__ 1
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M32: #define __PCLMUL__ 1
// CHECK_BDVER4_M32: #define __POPCNT__ 1
// CHECK_BDVER4_M32: #define __PRFCHW__ 1
[X86] Add MOVBE and RDRND features to BDVER4. Only 6 years behind gcc. https://gcc.gnu.org/legacy-ml/gcc-patches/2014-08/msg00231.html Found while working on improving how we define CPU features for clang and auditing for correctness.
2020-06-27 14:32:17 +08:00
// CHECK_BDVER4_M32: #define __RDRND__ 1
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M32: #define __SSE2_MATH__ 1
// CHECK_BDVER4_M32: #define __SSE2__ 1
// CHECK_BDVER4_M32: #define __SSE3__ 1
// CHECK_BDVER4_M32: #define __SSE4A__ 1
// CHECK_BDVER4_M32: #define __SSE4_1__ 1
// CHECK_BDVER4_M32: #define __SSE4_2__ 1
// CHECK_BDVER4_M32: #define __SSE_MATH__ 1
// CHECK_BDVER4_M32: #define __SSE__ 1
// CHECK_BDVER4_M32: #define __SSSE3__ 1
// CHECK_BDVER4_M32: #define __TBM__ 1
// CHECK_BDVER4_M32: #define __XOP__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BDVER4_M32: #define __XSAVE__ 1
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M32: #define __bdver4 1
// CHECK_BDVER4_M32: #define __bdver4__ 1
// CHECK_BDVER4_M32: #define __i386 1
// CHECK_BDVER4_M32: #define __i386__ 1
// CHECK_BDVER4_M32: #define __tune_bdver4__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// RUN: %clang -march=bdver4 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER4_M64
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M64-NOT: #define __3dNOW_A__ 1
// CHECK_BDVER4_M64-NOT: #define __3dNOW__ 1
// CHECK_BDVER4_M64: #define __AES__ 1
// CHECK_BDVER4_M64: #define __AVX2__ 1
// CHECK_BDVER4_M64: #define __AVX__ 1
// CHECK_BDVER4_M64: #define __BMI2__ 1
// CHECK_BDVER4_M64: #define __BMI__ 1
// CHECK_BDVER4_M64: #define __F16C__ 1
// CHECK_BDVER4_M64: #define __FMA4__ 1
// CHECK_BDVER4_M64: #define __FMA__ 1
[X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
2014-11-06 20:08:57 +08:00
// CHECK_BDVER4_M64: #define __FSGSBASE__ 1
[X86][LWP] Add __LWP__ macro tests Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
2017-05-09 01:25:48 +08:00
// CHECK_BDVER4_M64: #define __LWP__ 1
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M64: #define __LZCNT__ 1
// CHECK_BDVER4_M64: #define __MMX__ 1
[X86] Add MOVBE and RDRND features to BDVER4. Only 6 years behind gcc. https://gcc.gnu.org/legacy-ml/gcc-patches/2014-08/msg00231.html Found while working on improving how we define CPU features for clang and auditing for correctness.
2020-06-27 14:32:17 +08:00
// CHECK_BDVER4_M64: #define __MOVBE__ 1
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M64: #define __PCLMUL__ 1
// CHECK_BDVER4_M64: #define __POPCNT__ 1
// CHECK_BDVER4_M64: #define __PRFCHW__ 1
[X86] Add MOVBE and RDRND features to BDVER4. Only 6 years behind gcc. https://gcc.gnu.org/legacy-ml/gcc-patches/2014-08/msg00231.html Found while working on improving how we define CPU features for clang and auditing for correctness.
2020-06-27 14:32:17 +08:00
// CHECK_BDVER4_M64: #define __RDRND__ 1
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M64: #define __SSE2_MATH__ 1
// CHECK_BDVER4_M64: #define __SSE2__ 1
// CHECK_BDVER4_M64: #define __SSE3__ 1
// CHECK_BDVER4_M64: #define __SSE4A__ 1
// CHECK_BDVER4_M64: #define __SSE4_1__ 1
// CHECK_BDVER4_M64: #define __SSE4_2__ 1
// CHECK_BDVER4_M64: #define __SSE_MATH__ 1
// CHECK_BDVER4_M64: #define __SSE__ 1
// CHECK_BDVER4_M64: #define __SSSE3__ 1
// CHECK_BDVER4_M64: #define __TBM__ 1
// CHECK_BDVER4_M64: #define __XOP__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// CHECK_BDVER4_M64: #define __XSAVE__ 1
Add support for -march=bdver4. llvm-svn: 207848
2014-05-02 23:47:51 +08:00
// CHECK_BDVER4_M64: #define __amd64 1
// CHECK_BDVER4_M64: #define __amd64__ 1
// CHECK_BDVER4_M64: #define __bdver4 1
// CHECK_BDVER4_M64: #define __bdver4__ 1
// CHECK_BDVER4_M64: #define __tune_bdver4__ 1
// CHECK_BDVER4_M64: #define __x86_64 1
// CHECK_BDVER4_M64: #define __x86_64__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// RUN: %clang -march=znver1 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER1_M32
// CHECK_ZNVER1_M32-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER1_M32-NOT: #define __3dNOW__ 1
// CHECK_ZNVER1_M32: #define __ADX__ 1
// CHECK_ZNVER1_M32: #define __AES__ 1
// CHECK_ZNVER1_M32: #define __AVX2__ 1
// CHECK_ZNVER1_M32: #define __AVX__ 1
// CHECK_ZNVER1_M32: #define __BMI2__ 1
// CHECK_ZNVER1_M32: #define __BMI__ 1
[X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
2017-02-08 14:48:58 +08:00
// CHECK_ZNVER1_M32: #define __CLFLUSHOPT__ 1
[X86] Clzero flag addition and inclusion under znver1 1. Adds the command line flag for clzero. 2. Includes the clzero flag under znver1. 3. Defines the macro for clzero. 4. Adds a new file which has the intrinsic definition for clzero instruction. Patch by Ganesh Gopalasubramanian with some additional tests from me. Differential revision: https://reviews.llvm.org/D29386 llvm-svn: 294559
2017-02-09 14:10:14 +08:00
// CHECK_ZNVER1_M32: #define __CLZERO__ 1
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// CHECK_ZNVER1_M32: #define __F16C__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER1_M32-NOT: #define __FMA4__ 1
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// CHECK_ZNVER1_M32: #define __FMA__ 1
// CHECK_ZNVER1_M32: #define __FSGSBASE__ 1
// CHECK_ZNVER1_M32: #define __LZCNT__ 1
// CHECK_ZNVER1_M32: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_ZNVER1_M32: #define __MOVBE__ 1
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// CHECK_ZNVER1_M32: #define __PCLMUL__ 1
// CHECK_ZNVER1_M32: #define __POPCNT__ 1
// CHECK_ZNVER1_M32: #define __PRFCHW__ 1
// CHECK_ZNVER1_M32: #define __RDRND__ 1
// CHECK_ZNVER1_M32: #define __RDSEED__ 1
// CHECK_ZNVER1_M32: #define __SHA__ 1
// CHECK_ZNVER1_M32: #define __SSE2_MATH__ 1
// CHECK_ZNVER1_M32: #define __SSE2__ 1
// CHECK_ZNVER1_M32: #define __SSE3__ 1
// CHECK_ZNVER1_M32: #define __SSE4A__ 1
// CHECK_ZNVER1_M32: #define __SSE4_1__ 1
// CHECK_ZNVER1_M32: #define __SSE4_2__ 1
// CHECK_ZNVER1_M32: #define __SSE_MATH__ 1
// CHECK_ZNVER1_M32: #define __SSE__ 1
// CHECK_ZNVER1_M32: #define __SSSE3__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER1_M32-NOT: #define __TBM__ 1
// CHECK_ZNVER1_M32-NOT: #define __XOP__ 1
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// CHECK_ZNVER1_M32: #define __XSAVEC__ 1
// CHECK_ZNVER1_M32: #define __XSAVEOPT__ 1
// CHECK_ZNVER1_M32: #define __XSAVES__ 1
// CHECK_ZNVER1_M32: #define __XSAVE__ 1
// CHECK_ZNVER1_M32: #define __i386 1
// CHECK_ZNVER1_M32: #define __i386__ 1
// CHECK_ZNVER1_M32: #define __tune_znver1__ 1
// CHECK_ZNVER1_M32: #define __znver1 1
// CHECK_ZNVER1_M32: #define __znver1__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// RUN: %clang -march=znver1 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER1_M64
// CHECK_ZNVER1_M64-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER1_M64-NOT: #define __3dNOW__ 1
// CHECK_ZNVER1_M64: #define __ADX__ 1
// CHECK_ZNVER1_M64: #define __AES__ 1
// CHECK_ZNVER1_M64: #define __AVX2__ 1
// CHECK_ZNVER1_M64: #define __AVX__ 1
// CHECK_ZNVER1_M64: #define __BMI2__ 1
// CHECK_ZNVER1_M64: #define __BMI__ 1
[X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
2017-02-08 14:48:58 +08:00
// CHECK_ZNVER1_M64: #define __CLFLUSHOPT__ 1
[X86] Clzero flag addition and inclusion under znver1 1. Adds the command line flag for clzero. 2. Includes the clzero flag under znver1. 3. Defines the macro for clzero. 4. Adds a new file which has the intrinsic definition for clzero instruction. Patch by Ganesh Gopalasubramanian with some additional tests from me. Differential revision: https://reviews.llvm.org/D29386 llvm-svn: 294559
2017-02-09 14:10:14 +08:00
// CHECK_ZNVER1_M64: #define __CLZERO__ 1
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// CHECK_ZNVER1_M64: #define __F16C__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER1_M64-NOT: #define __FMA4__ 1
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// CHECK_ZNVER1_M64: #define __FMA__ 1
// CHECK_ZNVER1_M64: #define __FSGSBASE__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_ZNVER1_M64: #define __LAHF_SAHF__ 1
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// CHECK_ZNVER1_M64: #define __LZCNT__ 1
// CHECK_ZNVER1_M64: #define __MMX__ 1
[X86] Add the movbe instruction intrinsics from icc. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
2018-09-29 01:09:51 +08:00
// CHECK_ZNVER1_M64: #define __MOVBE__ 1
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// CHECK_ZNVER1_M64: #define __PCLMUL__ 1
// CHECK_ZNVER1_M64: #define __POPCNT__ 1
// CHECK_ZNVER1_M64: #define __PRFCHW__ 1
// CHECK_ZNVER1_M64: #define __RDRND__ 1
// CHECK_ZNVER1_M64: #define __RDSEED__ 1
// CHECK_ZNVER1_M64: #define __SHA__ 1
// CHECK_ZNVER1_M64: #define __SSE2_MATH__ 1
// CHECK_ZNVER1_M64: #define __SSE2__ 1
// CHECK_ZNVER1_M64: #define __SSE3__ 1
// CHECK_ZNVER1_M64: #define __SSE4A__ 1
// CHECK_ZNVER1_M64: #define __SSE4_1__ 1
// CHECK_ZNVER1_M64: #define __SSE4_2__ 1
// CHECK_ZNVER1_M64: #define __SSE_MATH__ 1
// CHECK_ZNVER1_M64: #define __SSE__ 1
// CHECK_ZNVER1_M64: #define __SSSE3__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER1_M64-NOT: #define __TBM__ 1
// CHECK_ZNVER1_M64-NOT: #define __XOP__ 1
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 14:02:12 +08:00
// CHECK_ZNVER1_M64: #define __XSAVEC__ 1
// CHECK_ZNVER1_M64: #define __XSAVEOPT__ 1
// CHECK_ZNVER1_M64: #define __XSAVES__ 1
// CHECK_ZNVER1_M64: #define __XSAVE__ 1
// CHECK_ZNVER1_M64: #define __amd64 1
// CHECK_ZNVER1_M64: #define __amd64__ 1
// CHECK_ZNVER1_M64: #define __tune_znver1__ 1
// CHECK_ZNVER1_M64: #define __x86_64 1
// CHECK_ZNVER1_M64: #define __x86_64__ 1
// CHECK_ZNVER1_M64: #define __znver1 1
// CHECK_ZNVER1_M64: #define __znver1__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-27 01:15:36 +08:00
// RUN: %clang -march=znver2 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER2_M32
// CHECK_ZNVER2_M32-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER2_M32-NOT: #define __3dNOW__ 1
// CHECK_ZNVER2_M32: #define __ADX__ 1
// CHECK_ZNVER2_M32: #define __AES__ 1
// CHECK_ZNVER2_M32: #define __AVX2__ 1
// CHECK_ZNVER2_M32: #define __AVX__ 1
// CHECK_ZNVER2_M32: #define __BMI2__ 1
// CHECK_ZNVER2_M32: #define __BMI__ 1
// CHECK_ZNVER2_M32: #define __CLFLUSHOPT__ 1
// CHECK_ZNVER2_M32: #define __CLWB__ 1
// CHECK_ZNVER2_M32: #define __CLZERO__ 1
// CHECK_ZNVER2_M32: #define __F16C__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER2_M32-NOT: #define __FMA4__ 1
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-27 01:15:36 +08:00
// CHECK_ZNVER2_M32: #define __FMA__ 1
// CHECK_ZNVER2_M32: #define __FSGSBASE__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_ZNVER2_M32: #define __LAHF_SAHF__ 1
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-27 01:15:36 +08:00
// CHECK_ZNVER2_M32: #define __LZCNT__ 1
// CHECK_ZNVER2_M32: #define __MMX__ 1
// CHECK_ZNVER2_M32: #define __PCLMUL__ 1
// CHECK_ZNVER2_M32: #define __POPCNT__ 1
// CHECK_ZNVER2_M32: #define __PRFCHW__ 1
// CHECK_ZNVER2_M32: #define __RDPID__ 1
// CHECK_ZNVER2_M32: #define __RDRND__ 1
// CHECK_ZNVER2_M32: #define __RDSEED__ 1
// CHECK_ZNVER2_M32: #define __SHA__ 1
// CHECK_ZNVER2_M32: #define __SSE2_MATH__ 1
// CHECK_ZNVER2_M32: #define __SSE2__ 1
// CHECK_ZNVER2_M32: #define __SSE3__ 1
// CHECK_ZNVER2_M32: #define __SSE4A__ 1
// CHECK_ZNVER2_M32: #define __SSE4_1__ 1
// CHECK_ZNVER2_M32: #define __SSE4_2__ 1
// CHECK_ZNVER2_M32: #define __SSE_MATH__ 1
// CHECK_ZNVER2_M32: #define __SSE__ 1
// CHECK_ZNVER2_M32: #define __SSSE3__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER2_M32-NOT: #define __TBM__ 1
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-27 01:15:36 +08:00
// CHECK_ZNVER2_M32: #define __WBNOINVD__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER2_M32-NOT: #define __XOP__ 1
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-27 01:15:36 +08:00
// CHECK_ZNVER2_M32: #define __XSAVEC__ 1
// CHECK_ZNVER2_M32: #define __XSAVEOPT__ 1
// CHECK_ZNVER2_M32: #define __XSAVES__ 1
// CHECK_ZNVER2_M32: #define __XSAVE__ 1
// CHECK_ZNVER2_M32: #define __i386 1
// CHECK_ZNVER2_M32: #define __i386__ 1
// CHECK_ZNVER2_M32: #define __tune_znver2__ 1
// CHECK_ZNVER2_M32: #define __znver2 1
// CHECK_ZNVER2_M32: #define __znver2__ 1
// RUN: %clang -march=znver2 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER2_M64
// CHECK_ZNVER2_M64-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER2_M64-NOT: #define __3dNOW__ 1
// CHECK_ZNVER2_M64: #define __ADX__ 1
// CHECK_ZNVER2_M64: #define __AES__ 1
// CHECK_ZNVER2_M64: #define __AVX2__ 1
// CHECK_ZNVER2_M64: #define __AVX__ 1
// CHECK_ZNVER2_M64: #define __BMI2__ 1
// CHECK_ZNVER2_M64: #define __BMI__ 1
// CHECK_ZNVER2_M64: #define __CLFLUSHOPT__ 1
// CHECK_ZNVER2_M64: #define __CLWB__ 1
// CHECK_ZNVER2_M64: #define __CLZERO__ 1
// CHECK_ZNVER2_M64: #define __F16C__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER2_M64-NOT: #define __FMA4__ 1
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-27 01:15:36 +08:00
// CHECK_ZNVER2_M64: #define __FMA__ 1
// CHECK_ZNVER2_M64: #define __FSGSBASE__ 1
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode GCC 11 will define this macro. In LLVM, the feature flag only applies to 64-bit mode and we always define the macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can suppress the macro. The discrepancy can unlikely cause trouble. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89198
2020-10-11 13:21:47 +08:00
// CHECK_ZNVER2_M64: #define __LAHF_SAHF__ 1
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-27 01:15:36 +08:00
// CHECK_ZNVER2_M64: #define __LZCNT__ 1
// CHECK_ZNVER2_M64: #define __MMX__ 1
// CHECK_ZNVER2_M64: #define __PCLMUL__ 1
// CHECK_ZNVER2_M64: #define __POPCNT__ 1
// CHECK_ZNVER2_M64: #define __PRFCHW__ 1
// CHECK_ZNVER2_M64: #define __RDPID__ 1
// CHECK_ZNVER2_M64: #define __RDRND__ 1
// CHECK_ZNVER2_M64: #define __RDSEED__ 1
// CHECK_ZNVER2_M64: #define __SHA__ 1
// CHECK_ZNVER2_M64: #define __SSE2_MATH__ 1
// CHECK_ZNVER2_M64: #define __SSE2__ 1
// CHECK_ZNVER2_M64: #define __SSE3__ 1
// CHECK_ZNVER2_M64: #define __SSE4A__ 1
// CHECK_ZNVER2_M64: #define __SSE4_1__ 1
// CHECK_ZNVER2_M64: #define __SSE4_2__ 1
// CHECK_ZNVER2_M64: #define __SSE_MATH__ 1
// CHECK_ZNVER2_M64: #define __SSE__ 1
// CHECK_ZNVER2_M64: #define __SSSE3__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER2_M64-NOT: #define __TBM__ 1
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-27 01:15:36 +08:00
// CHECK_ZNVER2_M64: #define __WBNOINVD__ 1
[X86] Some CHECK-NOTs for FMA4/TBM/XOP for znver1/znver2 in predefined-arch-macros.c These features exist in earlier CPUs, but were deprecated on znver1/znver2. While working on D82731 I accidentally copied them from the earlier CPU. And nothing caught my mistake. Having these additional checks would have helped.
2020-07-01 00:58:48 +08:00
// CHECK_ZNVER2_M64-NOT: #define __XOP__ 1
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-27 01:15:36 +08:00
// CHECK_ZNVER2_M64: #define __XSAVEC__ 1
// CHECK_ZNVER2_M64: #define __XSAVEOPT__ 1
// CHECK_ZNVER2_M64: #define __XSAVES__ 1
// CHECK_ZNVER2_M64: #define __XSAVE__ 1
// CHECK_ZNVER2_M64: #define __amd64 1
// CHECK_ZNVER2_M64: #define __amd64__ 1
// CHECK_ZNVER2_M64: #define __tune_znver2__ 1
// CHECK_ZNVER2_M64: #define __x86_64 1
// CHECK_ZNVER2_M64: #define __x86_64__ 1
// CHECK_ZNVER2_M64: #define __znver2 1
// CHECK_ZNVER2_M64: #define __znver2__ 1
[X86] Add a stub for znver3 based on the little public information there is in AMD's manuals No scheduling, no autodetection. Just enough so -march=znver3 works.
2020-10-25 00:00:20 +08:00
// RUN: %clang -march=znver3 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER3_M32
// CHECK_ZNVER3_M32-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER3_M32-NOT: #define __3dNOW__ 1
// CHECK_ZNVER3_M32: #define __ADX__ 1
// CHECK_ZNVER3_M32: #define __AES__ 1
// CHECK_ZNVER3_M32: #define __AVX2__ 1
// CHECK_ZNVER3_M32: #define __AVX__ 1
// CHECK_ZNVER3_M32: #define __BMI2__ 1
// CHECK_ZNVER3_M32: #define __BMI__ 1
// CHECK_ZNVER3_M32: #define __CLFLUSHOPT__ 1
// CHECK_ZNVER3_M32: #define __CLWB__ 1
// CHECK_ZNVER3_M32: #define __CLZERO__ 1
// CHECK_ZNVER3_M32: #define __F16C__ 1
// CHECK_ZNVER3_M32-NOT: #define __FMA4__ 1
// CHECK_ZNVER3_M32: #define __FMA__ 1
// CHECK_ZNVER3_M32: #define __FSGSBASE__ 1
// CHECK_ZNVER3_M32: #define __LZCNT__ 1
// CHECK_ZNVER3_M32: #define __MMX__ 1
// CHECK_ZNVER3_M32: #define __PCLMUL__ 1
// CHECK_ZNVER3_M32: #define __PKU__ 1
// CHECK_ZNVER3_M32: #define __POPCNT__ 1
// CHECK_ZNVER3_M32: #define __PRFCHW__ 1
// CHECK_ZNVER3_M32: #define __RDPID__ 1
// CHECK_ZNVER3_M32: #define __RDRND__ 1
// CHECK_ZNVER3_M32: #define __RDSEED__ 1
// CHECK_ZNVER3_M32: #define __SHA__ 1
// CHECK_ZNVER3_M32: #define __SSE2_MATH__ 1
// CHECK_ZNVER3_M32: #define __SSE2__ 1
// CHECK_ZNVER3_M32: #define __SSE3__ 1
// CHECK_ZNVER3_M32: #define __SSE4A__ 1
// CHECK_ZNVER3_M32: #define __SSE4_1__ 1
// CHECK_ZNVER3_M32: #define __SSE4_2__ 1
// CHECK_ZNVER3_M32: #define __SSE_MATH__ 1
// CHECK_ZNVER3_M32: #define __SSE__ 1
// CHECK_ZNVER3_M32: #define __SSSE3__ 1
// CHECK_ZNVER3_M32-NOT: #define __TBM__ 1
// CHECK_ZNVER3_M32: #define __WBNOINVD__ 1
// CHECK_ZNVER3_M32-NOT: #define __XOP__ 1
// CHECK_ZNVER3_M32: #define __XSAVEC__ 1
// CHECK_ZNVER3_M32: #define __XSAVEOPT__ 1
// CHECK_ZNVER3_M32: #define __XSAVES__ 1
// CHECK_ZNVER3_M32: #define __XSAVE__ 1
// CHECK_ZNVER3_M32: #define __i386 1
// CHECK_ZNVER3_M32: #define __i386__ 1
// CHECK_ZNVER3_M32: #define __tune_znver3__ 1
// CHECK_ZNVER3_M32: #define __znver3 1
// CHECK_ZNVER3_M32: #define __znver3__ 1
// RUN: %clang -march=znver3 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER3_M64
// CHECK_ZNVER3_M64-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER3_M64-NOT: #define __3dNOW__ 1
// CHECK_ZNVER3_M64: #define __ADX__ 1
// CHECK_ZNVER3_M64: #define __AES__ 1
// CHECK_ZNVER3_M64: #define __AVX2__ 1
// CHECK_ZNVER3_M64: #define __AVX__ 1
// CHECK_ZNVER3_M64: #define __BMI2__ 1
// CHECK_ZNVER3_M64: #define __BMI__ 1
// CHECK_ZNVER3_M64: #define __CLFLUSHOPT__ 1
// CHECK_ZNVER3_M64: #define __CLWB__ 1
// CHECK_ZNVER3_M64: #define __CLZERO__ 1
// CHECK_ZNVER3_M64: #define __F16C__ 1
// CHECK_ZNVER3_M64-NOT: #define __FMA4__ 1
// CHECK_ZNVER3_M64: #define __FMA__ 1
// CHECK_ZNVER3_M64: #define __FSGSBASE__ 1
// CHECK_ZNVER3_M64: #define __LZCNT__ 1
// CHECK_ZNVER3_M64: #define __MMX__ 1
// CHECK_ZNVER3_M64: #define __PCLMUL__ 1
// CHECK_ZNVER3_M64: #define __PKU__ 1
// CHECK_ZNVER3_M64: #define __POPCNT__ 1
// CHECK_ZNVER3_M64: #define __PRFCHW__ 1
// CHECK_ZNVER3_M64: #define __RDPID__ 1
// CHECK_ZNVER3_M64: #define __RDRND__ 1
// CHECK_ZNVER3_M64: #define __RDSEED__ 1
// CHECK_ZNVER3_M64: #define __SHA__ 1
// CHECK_ZNVER3_M64: #define __SSE2_MATH__ 1
// CHECK_ZNVER3_M64: #define __SSE2__ 1
// CHECK_ZNVER3_M64: #define __SSE3__ 1
// CHECK_ZNVER3_M64: #define __SSE4A__ 1
// CHECK_ZNVER3_M64: #define __SSE4_1__ 1
// CHECK_ZNVER3_M64: #define __SSE4_2__ 1
// CHECK_ZNVER3_M64: #define __SSE_MATH__ 1
// CHECK_ZNVER3_M64: #define __SSE__ 1
// CHECK_ZNVER3_M64: #define __SSSE3__ 1
// CHECK_ZNVER3_M64-NOT: #define __TBM__ 1
// CHECK_ZNVER3_M64: #define __VAES__ 1
// CHECK_ZNVER3_M64: #define __VPCLMULQDQ__ 1
// CHECK_ZNVER3_M64: #define __WBNOINVD__ 1
// CHECK_ZNVER3_M64-NOT: #define __XOP__ 1
// CHECK_ZNVER3_M64: #define __XSAVEC__ 1
// CHECK_ZNVER3_M64: #define __XSAVEOPT__ 1
// CHECK_ZNVER3_M64: #define __XSAVES__ 1
// CHECK_ZNVER3_M64: #define __XSAVE__ 1
// CHECK_ZNVER3_M64: #define __amd64 1
// CHECK_ZNVER3_M64: #define __amd64__ 1
// CHECK_ZNVER3_M64: #define __tune_znver3__ 1
// CHECK_ZNVER3_M64: #define __x86_64 1
// CHECK_ZNVER3_M64: #define __x86_64__ 1
// CHECK_ZNVER3_M64: #define __znver3 1
// CHECK_ZNVER3_M64: #define __znver3__ 1
Add a little banner to this test. This lets my scripts more easily automate the process of updating and generating these tests. If anyone is really interested, I can check my scripts for generating this test in, but its a horrible pile of shell... Not sure its really worth it. llvm-svn: 140691
2011-09-28 18:17:41 +08:00
// End X86/GCC/Linux tests ------------------
Add preprocessor support for powerpc vsx. The test should be expanded upon for more powerpc checking. llvm-svn: 192849
2013-10-17 05:19:26 +08:00
// Begin PPC/GCC/Linux tests ----------------
When we turn on vsx it should also turn on altivec explicitly, same with disabling it as well as disabling all vsx specific features when turning off altivec. Fixes PR32663. llvm-svn: 300395
2017-04-15 14:15:00 +08:00
// Check that VSX also turns on altivec.
// RUN: %clang -mvsx -E -dM %s -o - 2>&1 \
// RUN: -target powerpc-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_VSX_M32
// CHECK_PPC_VSX_M32: #define __ALTIVEC__ 1
// CHECK_PPC_VSX_M32: #define __VSX__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add preprocessor support for powerpc vsx. The test should be expanded upon for more powerpc checking. llvm-svn: 192849
2013-10-17 05:19:26 +08:00
// RUN: %clang -mvsx -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_VSX_M64
// CHECK_PPC_VSX_M64: #define __VSX__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[PowerPC] Add feature for Power8 vector extensions The current VSX feature for PowerPC specifies availability of the VSX instructions added with the 2.06 architecture version. With 2.07, the architecture adds new instructions to both the Category:Vector and Category:VSX instruction sets. Additionally, unaligned vector storage operations have improved performance. This patch adds a feature to provide access to the new instructions and performance capabilities of Power8. For compatibility with GCC, the feature is controlled via a new -mpower8-vector switch, and the feature causes the __POWER8_VECTOR__ builtin define to be generated by the preprocessor. There is a companion patch for llvm being committed at the same time. llvm-svn: 219502
2014-10-10 23:09:43 +08:00
// RUN: %clang -mpower8-vector -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_POWER8_VECTOR_M64
// CHECK_PPC_POWER8_VECTOR_M64: #define __POWER8_VECTOR__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[Power9] Builtins for ELF v.2 ABI conformance - front end portion This patch corresponds to review: https://reviews.llvm.org/D24397 It adds the __POWER9_VECTOR__ macro and the -mpower9-vector option along with a number of altivec.h functions (refer to the code review for a list). llvm-svn: 282481
2016-09-27 18:45:22 +08:00
// RUN: %clang -mpower9-vector -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_POWER9_VECTOR_M64
// CHECK_PPC_POWER9_VECTOR_M64: #define __POWER9_VECTOR__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add Clang support for PPC cryptography builtins Review: http://reviews.llvm.org/D7951 llvm-svn: 231291
2015-03-05 05:48:22 +08:00
// RUN: %clang -mcrypto -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_CRYPTO_M64
// CHECK_PPC_CRYPTO_M64: #define __CRYPTO__ 1
Turn on HTM on power8 and later (including powerpc64le) since it's available by default on those cpus and configurations. llvm-svn: 298307
2017-03-21 05:12:53 +08:00
// HTM is available on power8 or later which includes all of powerpc64le as an
// ABI choice. Test that, the cpus, and the option.
// RUN: %clang -mhtm -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_HTM
// RUN: %clang -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64le-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_HTM
// RUN: %clang -mcpu=pwr8 -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_HTM
// RUN: %clang -mcpu=pwr9 -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_HTM
// CHECK_PPC_HTM: #define __HTM__ 1
[PowerPC] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros on all PPC cores We support all __sync_val_compare_and_swap_* builtins (only 64-bit on 64-bit targets) on all cores, and should define the corresponding __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros, just as GCC does. As it turns out, this is really important because they're needed to prevent a bad ODR violation with libstdc++'s std::shared_ptr (this is well explained in PR12730). We were doing this only for P8, but this is necessary on all PPC systems. llvm-svn: 249009
2015-10-01 21:39:49 +08:00
// RUN: %clang -mcpu=ppc64 -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64-unknown-unknown \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS
Testing for the fix for bug 23429. Follow-up to commit for revision 236848. Just a test case for the macro definition under the right CPU/Arch. One combination was actually missed in the initial fix: - powerpc64-unknown-unknown -mcpu=pwr8 (rather than -mcpu=power8). llvm-svn: 237386
2015-05-15 04:02:24 +08:00
// RUN: %clang -mcpu=pwr8 -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64-unknown-unknown \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS
Testing for the fix for bug 23429. Follow-up to commit for revision 236848. Just a test case for the macro definition under the right CPU/Arch. One combination was actually missed in the initial fix: - powerpc64-unknown-unknown -mcpu=pwr8 (rather than -mcpu=power8). llvm-svn: 237386
2015-05-15 04:02:24 +08:00
// RUN: %clang -E -dM %s -o - 2>&1 \
// RUN: -target powerpc64le-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS
// CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Testing for the fix for bug 23429. Follow-up to commit for revision 236848. Just a test case for the macro definition under the right CPU/Arch. One combination was actually missed in the initial fix: - powerpc64-unknown-unknown -mcpu=pwr8 (rather than -mcpu=power8). llvm-svn: 237386
2015-05-15 04:02:24 +08:00
// End PPC/GCC/Linux tests ------------------
[SystemZ] Support transactional execution on zEC12 The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
2015-04-01 20:54:25 +08:00
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// Begin Sparc/GCC/Linux tests ----------------
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// RUN: %clang -E -dM %s -o - 2>&1 \
// RUN: -target sparc-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARC
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// CHECK_SPARC: #define __BIG_ENDIAN__ 1
// CHECK_SPARC: #define __sparc 1
// CHECK_SPARC: #define __sparc__ 1
Reorganise CPU handling for Sparc. When using -mcpu=v9 and co, __sparcv8 is not defined for 32bit mode, but __sparcv9 is. Pass down the correct -target-cpu flags to the backend, so that instruction restrictions are applied correctly. Pass down the correct -A flag when not using IAS. The latter is limited to NetBSD targets in this commit. llvm-svn: 252545
2015-11-10 07:39:45 +08:00
// CHECK_SPARC-NOT: #define __sparcv9 1
Add the variant of __sparc_v9__ with five underscores, not just four. llvm-svn: 252640
2015-11-11 03:28:17 +08:00
// CHECK_SPARC-NOT: #define __sparcv9__ 1
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// CHECK_SPARC: #define __sparcv8 1
Reorganise CPU handling for Sparc. When using -mcpu=v9 and co, __sparcv8 is not defined for 32bit mode, but __sparcv9 is. Pass down the correct -target-cpu flags to the backend, so that instruction restrictions are applied correctly. Pass down the correct -A flag when not using IAS. The latter is limited to NetBSD targets in this commit. llvm-svn: 252545
2015-11-10 07:39:45 +08:00
// CHECK_SPARC-NOT: #define __sparcv9 1
Add the variant of __sparc_v9__ with five underscores, not just four. llvm-svn: 252640
2015-11-11 03:28:17 +08:00
// CHECK_SPARC-NOT: #define __sparcv9__ 1
Reorganise CPU handling for Sparc. When using -mcpu=v9 and co, __sparcv8 is not defined for 32bit mode, but __sparcv9 is. Pass down the correct -target-cpu flags to the backend, so that instruction restrictions are applied correctly. Pass down the correct -A flag when not using IAS. The latter is limited to NetBSD targets in this commit. llvm-svn: 252545
2015-11-10 07:39:45 +08:00
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
// RUN: %clang -mcpu=v9 -E -dM %s -o - 2>&1 \
// RUN: -target sparc-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARC-V9
Reorganise CPU handling for Sparc. When using -mcpu=v9 and co, __sparcv8 is not defined for 32bit mode, but __sparcv9 is. Pass down the correct -target-cpu flags to the backend, so that instruction restrictions are applied correctly. Pass down the correct -A flag when not using IAS. The latter is limited to NetBSD targets in this commit. llvm-svn: 252545
2015-11-10 07:39:45 +08:00
// CHECK_SPARC-V9-NOT: #define __sparcv8 1
[clang][Sparc] Default to -mcpu=v9 for Sparc V8 on Solaris As reported in Bug 42535, `clang` doesn't inline atomic ops on 32-bit Sparc, unlike `gcc` on Solaris. In a 1-stage build with `gcc`, only two testcases are affected (currently `XFAIL`ed), while in a 2-stage build more than 100 tests `FAIL` due to this issue. The reason for this `gcc`/`clang` difference is that `gcc` on 32-bit Solaris/SPARC defaults to `-mpcu=v9` where atomic ops are supported, unlike with `clang`'s default of `-mcpu=v8`. This patch changes `clang` to use `-mcpu=v9` on 32-bit Solaris/SPARC, too. Doing so uncovered two bugs: `clang -m32 -mcpu=v9` chokes with any Solaris system headers included: /usr/include/sys/isa_defs.h:461:2: error: "Both _ILP32 and _LP64 are defined" #error "Both _ILP32 and _LP64 are defined" While `clang` currently defines `__sparcv9` in a 32-bit `-mcpu=v9` compilation, neither `gcc` nor Studio `cc` do. In fact, the Studio 12.6 `cc(1)` man page clearly states: These predefinitions are valid in all modes: [...] __sparcv8 (SPARC) __sparcv9 (SPARC -m64) At the same time, the patch defines `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_[1248]` for a 32-bit Sparc compilation with any V9 cpu. I've also changed `MaxAtomicInlineWidth` for V9, matching what `gcc` does and the Oracle Developer Studio 12.6: C User's Guide documents (Ch. 3, Support for Atomic Types, 3.1 Size and Alignment of Atomic C Types). The two testcases that had been `XFAIL`ed for Bug 42535 are un-`XFAIL`ed again. Tested on `sparcv9-sun-solaris2.11` and `amd64-pc-solaris2.11`. Differential Revision: https://reviews.llvm.org/D86621
2020-09-11 15:53:19 +08:00
// CHECK_SPARC-V9-NOT: #define __sparcv8__ 1
Add the variant of __sparc_v9__ with five underscores, not just four. llvm-svn: 252640
2015-11-11 03:28:17 +08:00
// CHECK_SPARC-V9: #define __sparc_v9__ 1
Reorganise CPU handling for Sparc. When using -mcpu=v9 and co, __sparcv8 is not defined for 32bit mode, but __sparcv9 is. Pass down the correct -target-cpu flags to the backend, so that instruction restrictions are applied correctly. Pass down the correct -A flag when not using IAS. The latter is limited to NetBSD targets in this commit. llvm-svn: 252545
2015-11-10 07:39:45 +08:00
// CHECK_SPARC-V9: #define __sparcv9 1
[clang][Sparc] Default to -mcpu=v9 for Sparc V8 on Solaris As reported in Bug 42535, `clang` doesn't inline atomic ops on 32-bit Sparc, unlike `gcc` on Solaris. In a 1-stage build with `gcc`, only two testcases are affected (currently `XFAIL`ed), while in a 2-stage build more than 100 tests `FAIL` due to this issue. The reason for this `gcc`/`clang` difference is that `gcc` on 32-bit Solaris/SPARC defaults to `-mpcu=v9` where atomic ops are supported, unlike with `clang`'s default of `-mcpu=v8`. This patch changes `clang` to use `-mcpu=v9` on 32-bit Solaris/SPARC, too. Doing so uncovered two bugs: `clang -m32 -mcpu=v9` chokes with any Solaris system headers included: /usr/include/sys/isa_defs.h:461:2: error: "Both _ILP32 and _LP64 are defined" #error "Both _ILP32 and _LP64 are defined" While `clang` currently defines `__sparcv9` in a 32-bit `-mcpu=v9` compilation, neither `gcc` nor Studio `cc` do. In fact, the Studio 12.6 `cc(1)` man page clearly states: These predefinitions are valid in all modes: [...] __sparcv8 (SPARC) __sparcv9 (SPARC -m64) At the same time, the patch defines `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_[1248]` for a 32-bit Sparc compilation with any V9 cpu. I've also changed `MaxAtomicInlineWidth` for V9, matching what `gcc` does and the Oracle Developer Studio 12.6: C User's Guide documents (Ch. 3, Support for Atomic Types, 3.1 Size and Alignment of Atomic C Types). The two testcases that had been `XFAIL`ed for Bug 42535 are un-`XFAIL`ed again. Tested on `sparcv9-sun-solaris2.11` and `amd64-pc-solaris2.11`. Differential Revision: https://reviews.llvm.org/D86621
2020-09-11 15:53:19 +08:00
// CHECK_SPARC-V9: #define __sparcv9__ 1
// RUN: %clang -E -dM %s -o - 2>&1 \
// RUN: -target sparc-sun-solaris \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARC_SOLARIS_GCC_ATOMICS
// CHECK_SPARC_SOLARIS_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SPARC_SOLARIS_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_SPARC_SOLARIS_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_SPARC_SOLARIS_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
// RUN: %clang -mcpu=v8 -E -dM %s -o - 2>&1 \
// RUN: -target sparc-sun-solaris \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARC_SOLARIS_GCC_ATOMICS-V8
// CHECK_SPARC_SOLARIS_GCC_ATOMICS-V8-NOT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SPARC_SOLARIS_GCC_ATOMICS-V8-NOT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_SPARC_SOLARIS_GCC_ATOMICS-V8-NOT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_SPARC_SOLARIS_GCC_ATOMICS-V8-NOT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// RUN: %clang -E -dM %s -o - 2>&1 \
// RUN: -target sparcel-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARCEL
Myriad: define __myriad2 macro automatically llvm-svn: 263596
2016-03-16 06:34:02 +08:00
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=myriad2 2>&1 \
Add support for Myriad ma2x8x series of CPUs Summary: Also: - Add support for some older Myriad CPUs that were missing. - Fix some incorrect compiler defines for exisitng CPUs. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37551 llvm-svn: 314706
2017-10-03 02:50:57 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
Myriad: define __myriad2 macro automatically llvm-svn: 263596
2016-03-16 06:34:02 +08:00
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=myriad2.1 2>&1 \
Add support for Myriad ma2x8x series of CPUs Summary: Also: - Add support for some older Myriad CPUs that were missing. - Fix some incorrect compiler defines for exisitng CPUs. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37551 llvm-svn: 314706
2017-10-03 02:50:57 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-1 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
Myriad: define __myriad2 macro automatically llvm-svn: 263596
2016-03-16 06:34:02 +08:00
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=myriad2.2 2>&1 \
Add support for Myriad ma2x8x series of CPUs Summary: Also: - Add support for some older Myriad CPUs that were missing. - Fix some incorrect compiler defines for exisitng CPUs. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37551 llvm-svn: 314706
2017-10-03 02:50:57 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=myriad2.3 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2100 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-1 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2150 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2155 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
[Myriad]: better compatibility with vendor source - Accept ma{2100,2150,2150} for -mcpu - Define more preprocessor macros - Don't append "le/" to little-endian lib dirs llvm-svn: 276646
2016-07-26 00:36:02 +08:00
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2450 2>&1 \
Add support for Myriad ma2x8x series of CPUs Summary: Also: - Add support for some older Myriad CPUs that were missing. - Fix some incorrect compiler defines for exisitng CPUs. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37551 llvm-svn: 314706
2017-10-03 02:50:57 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2455 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2x5x 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2080 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2085 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2480 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2485 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
// RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2x8x 2>&1 \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \
// RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// CHECK_SPARCEL: #define __LITTLE_ENDIAN__ 1
Add support for Myriad ma2x8x series of CPUs Summary: Also: - Add support for some older Myriad CPUs that were missing. - Fix some incorrect compiler defines for exisitng CPUs. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37551 llvm-svn: 314706
2017-10-03 02:50:57 +08:00
// CHECK_MYRIAD2: #define __leon__ 1
Myriad: define __myriad2 macro automatically llvm-svn: 263596
2016-03-16 06:34:02 +08:00
// CHECK_MYRIAD2-1: #define __myriad2 1
// CHECK_MYRIAD2-1: #define __myriad2__ 1
[Myriad] Define __ma2x5x and __ma2x8x Summary: Add architecture defines for ma2x5x and ma2x8x. Reviewers: jyknight Subscribers: fedor.sergeev, MartinO Differential Revision: https://reviews.llvm.org/D42882 llvm-svn: 324420
2018-02-07 06:39:47 +08:00
// CHECK_MYRIAD2-2: #define __ma2x5x 1
// CHECK_MYRIAD2-2: #define __ma2x5x__ 1
Myriad: define __myriad2 macro automatically llvm-svn: 263596
2016-03-16 06:34:02 +08:00
// CHECK_MYRIAD2-2: #define __myriad2 2
// CHECK_MYRIAD2-2: #define __myriad2__ 2
[Myriad] Define __ma2x5x and __ma2x8x Summary: Add architecture defines for ma2x5x and ma2x8x. Reviewers: jyknight Subscribers: fedor.sergeev, MartinO Differential Revision: https://reviews.llvm.org/D42882 llvm-svn: 324420
2018-02-07 06:39:47 +08:00
// CHECK_MYRIAD2-3: #define __ma2x8x 1
// CHECK_MYRIAD2-3: #define __ma2x8x__ 1
Add support for Myriad ma2x8x series of CPUs Summary: Also: - Add support for some older Myriad CPUs that were missing. - Fix some incorrect compiler defines for exisitng CPUs. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37551 llvm-svn: 314706
2017-10-03 02:50:57 +08:00
// CHECK_MYRIAD2-3: #define __myriad2 3
// CHECK_MYRIAD2-3: #define __myriad2__ 3
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// CHECK_SPARCEL: #define __sparc 1
// CHECK_SPARCEL: #define __sparc__ 1
Add support for Myriad ma2x8x series of CPUs Summary: Also: - Add support for some older Myriad CPUs that were missing. - Fix some incorrect compiler defines for exisitng CPUs. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37551 llvm-svn: 314706
2017-10-03 02:50:57 +08:00
// CHECK_MYRIAD2: #define __sparc_v8__ 1
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// CHECK_SPARCEL: #define __sparcv8 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// RUN: %clang -E -dM %s -o - 2>&1 \
// RUN: -target sparcv9-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARCV9
[Sparc] Add support for 'sparcel' to clang. Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
2015-05-11 23:21:44 +08:00
// CHECK_SPARCV9: #define __BIG_ENDIAN__ 1
// CHECK_SPARCV9: #define __sparc 1
// CHECK_SPARCV9: #define __sparc64__ 1
// CHECK_SPARCV9: #define __sparc__ 1
// CHECK_SPARCV9: #define __sparc_v9__ 1
// CHECK_SPARCV9: #define __sparcv9 1
// CHECK_SPARCV9: #define __sparcv9__ 1
[Sparc] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros on SPARCv9
2020-08-11 12:04:24 +08:00
// RUN: %clang -E -dM %s -o - 2>&1 \
// RUN: -target sparcv9-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARCV9_GCC_ATOMICS
// CHECK_SPARCV9_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SPARCV9_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_SPARCV9_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_SPARCV9_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
[SystemZ] Support transactional execution on zEC12 The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
2015-04-01 20:54:25 +08:00
// Begin SystemZ/GCC/Linux tests ----------------
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[SystemZ] Provide predefined __ARCH__ and __VX__ macros GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
2017-02-07 01:04:22 +08:00
// RUN: %clang -march=arch8 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH8
[SystemZ] Support transactional execution on zEC12 The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
2015-04-01 20:54:25 +08:00
// RUN: %clang -march=z10 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
[SystemZ] Provide predefined __ARCH__ and __VX__ macros GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
2017-02-07 01:04:22 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH8
// CHECK_SYSTEMZ_ARCH8: #define __ARCH__ 8
// CHECK_SYSTEMZ_ARCH8: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SYSTEMZ_ARCH8: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_SYSTEMZ_ARCH8: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_SYSTEMZ_ARCH8: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
// CHECK_SYSTEMZ_ARCH8: #define __LONG_DOUBLE_128__ 1
// CHECK_SYSTEMZ_ARCH8: #define __s390__ 1
// CHECK_SYSTEMZ_ARCH8: #define __s390x__ 1
// CHECK_SYSTEMZ_ARCH8: #define __zarch__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[SystemZ] Provide predefined __ARCH__ and __VX__ macros GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
2017-02-07 01:04:22 +08:00
// RUN: %clang -march=arch9 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH9
// RUN: %clang -march=z196 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH9
// CHECK_SYSTEMZ_ARCH9: #define __ARCH__ 9
// CHECK_SYSTEMZ_ARCH9: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SYSTEMZ_ARCH9: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_SYSTEMZ_ARCH9: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_SYSTEMZ_ARCH9: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
// CHECK_SYSTEMZ_ARCH9: #define __LONG_DOUBLE_128__ 1
// CHECK_SYSTEMZ_ARCH9: #define __s390__ 1
// CHECK_SYSTEMZ_ARCH9: #define __s390x__ 1
// CHECK_SYSTEMZ_ARCH9: #define __zarch__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[SystemZ] Provide predefined __ARCH__ and __VX__ macros GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
2017-02-07 01:04:22 +08:00
// RUN: %clang -march=arch10 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH10
[SystemZ] Support transactional execution on zEC12 The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
2015-04-01 20:54:25 +08:00
// RUN: %clang -march=zEC12 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
[SystemZ] Provide predefined __ARCH__ and __VX__ macros GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
2017-02-07 01:04:22 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH10
// CHECK_SYSTEMZ_ARCH10: #define __ARCH__ 10
// CHECK_SYSTEMZ_ARCH10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SYSTEMZ_ARCH10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_SYSTEMZ_ARCH10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_SYSTEMZ_ARCH10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
// CHECK_SYSTEMZ_ARCH10: #define __HTM__ 1
// CHECK_SYSTEMZ_ARCH10: #define __LONG_DOUBLE_128__ 1
// CHECK_SYSTEMZ_ARCH10: #define __s390__ 1
// CHECK_SYSTEMZ_ARCH10: #define __s390x__ 1
// CHECK_SYSTEMZ_ARCH10: #define __zarch__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[SystemZ] Provide predefined __ARCH__ and __VX__ macros GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
2017-02-07 01:04:22 +08:00
// RUN: %clang -march=arch11 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH11
// RUN: %clang -march=z13 -E -dM %s -o - 2>&1 \
[SystemZ] Add -march=archX aliases For compatibility with other compilers on the platform, allow specifying levels of the z/Architecture instead of model names with -march. In particular, the following aliases are now supported: -march=arch8 equals -march=z10 -march=arch9 equals -march=z196 -march=arch10 equals -march=zEC12 -march=arch11 equals -march=z13 This parallels the equivalent (and prerequisite) LLVM change in r285577. llvm-svn: 285578
2016-10-31 22:38:05 +08:00
// RUN: -target s390x-unknown-linux \
[SystemZ] Provide predefined __ARCH__ and __VX__ macros GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
2017-02-07 01:04:22 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH11
// CHECK_SYSTEMZ_ARCH11: #define __ARCH__ 11
// CHECK_SYSTEMZ_ARCH11: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SYSTEMZ_ARCH11: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_SYSTEMZ_ARCH11: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_SYSTEMZ_ARCH11: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
// CHECK_SYSTEMZ_ARCH11: #define __HTM__ 1
// CHECK_SYSTEMZ_ARCH11: #define __LONG_DOUBLE_128__ 1
// CHECK_SYSTEMZ_ARCH11: #define __VX__ 1
// CHECK_SYSTEMZ_ARCH11: #define __s390__ 1
// CHECK_SYSTEMZ_ARCH11: #define __s390x__ 1
// CHECK_SYSTEMZ_ARCH11: #define __zarch__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[SystemZ] Add support for IBM z14 processor (1/3) This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. Support for the -fzvector extension to vector float and the new high-level vector intrinsics is provided by separate patches. llvm-svn: 308197
2017-07-18 01:45:57 +08:00
// RUN: %clang -march=arch12 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH12
// RUN: %clang -march=z14 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH12
// CHECK_SYSTEMZ_ARCH12: #define __ARCH__ 12
// CHECK_SYSTEMZ_ARCH12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SYSTEMZ_ARCH12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_SYSTEMZ_ARCH12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_SYSTEMZ_ARCH12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
// CHECK_SYSTEMZ_ARCH12: #define __HTM__ 1
// CHECK_SYSTEMZ_ARCH12: #define __LONG_DOUBLE_128__ 1
// CHECK_SYSTEMZ_ARCH12: #define __VX__ 1
// CHECK_SYSTEMZ_ARCH12: #define __s390__ 1
// CHECK_SYSTEMZ_ARCH12: #define __s390x__ 1
// CHECK_SYSTEMZ_ARCH12: #define __zarch__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[SystemZ] Add support for new cpu architecture - arch13 This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10303. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365933
2019-07-13 02:14:51 +08:00
// RUN: %clang -march=arch13 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH13
[SystemZ] Support z15 processor name The recently announced IBM z15 processor implements the architecture already supported as "arch13" in LLVM. This patch adds support for "z15" as an alternate architecture name for arch13. Corrsponding LLVM support was committed as rev. 372435. llvm-svn: 372436
2019-09-21 07:06:03 +08:00
// RUN: %clang -march=z15 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH13
[SystemZ] Add support for new cpu architecture - arch13 This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10303. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365933
2019-07-13 02:14:51 +08:00
// CHECK_SYSTEMZ_ARCH13: #define __ARCH__ 13
// CHECK_SYSTEMZ_ARCH13: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SYSTEMZ_ARCH13: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// CHECK_SYSTEMZ_ARCH13: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// CHECK_SYSTEMZ_ARCH13: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
// CHECK_SYSTEMZ_ARCH13: #define __HTM__ 1
// CHECK_SYSTEMZ_ARCH13: #define __LONG_DOUBLE_128__ 1
// CHECK_SYSTEMZ_ARCH13: #define __VX__ 1
// CHECK_SYSTEMZ_ARCH13: #define __s390__ 1
// CHECK_SYSTEMZ_ARCH13: #define __s390x__ 1
// CHECK_SYSTEMZ_ARCH13: #define __zarch__ 1
[SystemZ] Support transactional execution on zEC12 The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
2015-04-01 20:54:25 +08:00
// RUN: %clang -mhtm -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_HTM
[SystemZ] Support transactional execution on zEC12 The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
2015-04-01 20:54:25 +08:00
// CHECK_SYSTEMZ_HTM: #define __HTM__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
[SystemZ] Provide predefined __ARCH__ and __VX__ macros GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
2017-02-07 01:04:22 +08:00
// RUN: %clang -mvx -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_VX
// CHECK_SYSTEMZ_VX: #define __VX__ 1
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
Add support for System z vector language extensions The z13 vector facility has an associated language extension, closely modeled on AltiVec/VSX. The main differences are: - vector long, vector float and vector pixel are not supported - vector long long and vector double are supported (like VSX) - comparison operators return a vector rather than a scalar integer - shift operators behave like the OpenCL shift operators - vector bool is only supported as argument to certain operators; some operators allow mixing a bool with a non-bool vector This patch adds clang support for the extension. It is closely modelled on the AltiVec support. Similarly to the -faltivec option, there's a new -fzvector option to enable the extensions (as well as an -mzvector alias for compatibility with GCC). There's also a separate LangOpt. The extension as implemented here is intended to be compatible with the -mzvector extension recently implemented by GCC. Based on a patch by Richard Sandiford. Differential Revision: http://reviews.llvm.org/D11001 llvm-svn: 243642
2015-07-30 22:08:36 +08:00
// RUN: %clang -fzvector -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ZVECTOR
Add support for System z vector language extensions The z13 vector facility has an associated language extension, closely modeled on AltiVec/VSX. The main differences are: - vector long, vector float and vector pixel are not supported - vector long long and vector double are supported (like VSX) - comparison operators return a vector rather than a scalar integer - shift operators behave like the OpenCL shift operators - vector bool is only supported as argument to certain operators; some operators allow mixing a bool with a non-bool vector This patch adds clang support for the extension. It is closely modelled on the AltiVec support. Similarly to the -faltivec option, there's a new -fzvector option to enable the extensions (as well as an -mzvector alias for compatibility with GCC). There's also a separate LangOpt. The extension as implemented here is intended to be compatible with the -mzvector extension recently implemented by GCC. Based on a patch by Richard Sandiford. Differential Revision: http://reviews.llvm.org/D11001 llvm-svn: 243642
2015-07-30 22:08:36 +08:00
// RUN: %clang -mzvector -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ZVECTOR
[SystemZ] Add support for new cpu architecture - arch13 This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10303. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365933
2019-07-13 02:14:51 +08:00
// CHECK_SYSTEMZ_ZVECTOR: #define __VEC__ 10303
AMDGPU: Fix broken/confusing predefined macro amdgcn should not be defining __R600__ llvm-svn: 262124
2016-02-27 17:06:26 +08:00
// Begin amdgcn tests ----------------
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
AMDGPU: Fix broken/confusing predefined macro amdgcn should not be defining __R600__ llvm-svn: 262124
2016-02-27 17:06:26 +08:00
// RUN: %clang -march=amdgcn -E -dM %s -o - 2>&1 \
// RUN: -target amdgcn-unknown-unknown \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_AMDGCN
AMDGPU: Fix broken/confusing predefined macro amdgcn should not be defining __R600__ llvm-svn: 262124
2016-02-27 17:06:26 +08:00
// CHECK_AMDGCN: #define __AMDGCN__ 1
AMDGPU: Parse r600 CPU name early and expose FMAF capability Improve amdgcn macro test Differential Revision: https://reviews.llvm.org/D38667 llvm-svn: 316181
2017-10-20 04:40:13 +08:00
// CHECK_AMDGCN: #define __HAS_FMAF__ 1
// CHECK_AMDGCN: #define __HAS_FP64__ 1
// CHECK_AMDGCN: #define __HAS_LDEXPF__ 1
AMDGPU: Fix broken/confusing predefined macro amdgcn should not be defining __R600__ llvm-svn: 262124
2016-02-27 17:06:26 +08:00
// Begin r600 tests ----------------
NFC - Indentation fixes in predefined-arch-macros.c Consistently separating tests with empty lines. Helps while navigating this file. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45561 llvm-svn: 329932
2018-04-13 02:15:39 +08:00
AMDGPU: Fix broken/confusing predefined macro amdgcn should not be defining __R600__ llvm-svn: 262124
2016-02-27 17:06:26 +08:00
// RUN: %clang -march=amdgcn -E -dM %s -o - 2>&1 \
// RUN: -target r600-unknown-unknown \
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_R600
AMDGPU: Fix broken/confusing predefined macro amdgcn should not be defining __R600__ llvm-svn: 262124
2016-02-27 17:06:26 +08:00
// CHECK_R600: #define __R600__ 1
AMDGPU: Parse r600 CPU name early and expose FMAF capability Improve amdgcn macro test Differential Revision: https://reviews.llvm.org/D38667 llvm-svn: 316181
2017-10-20 04:40:13 +08:00
// CHECK_R600-NOT: #define __HAS_FMAF__ 1
// RUN: %clang -march=amdgcn -mcpu=cypress -E -dM %s -o - 2>&1 \
// RUN: -target r600-unknown-unknown \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_R600_FP64
// CHECK_R600_FP64-DAG: #define __R600__ 1
// CHECK_R600_FP64-DAG: #define __HAS_FMAF__ 1