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Add test cases for merging stores of multiply used stores llvm-svn: 296667
2017-03-02 04:18:14 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -o - | FileCheck %s
[SDAG] Relax conditions under stores of loaded values can be merged Summary: Allow consecutive stores whose values come from consecutive loads to merged in the presense of other uses of the loads. Previously this was disallowed as in general the merged load cannot be shared with the other uses. Merging N stores into 1 may cause as many as N redundant loads. However in the context of caching this should have neglible affect on memory pressure and reduce instruction count making it almost always a win. Fixes PR32086. Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30471 llvm-svn: 302712
2017-05-11 03:53:41 +08:00
; PR32086
Add test cases for merging stores of multiply used stores llvm-svn: 296667
2017-03-02 04:18:14 +08:00
target triple = "x86_64-unknown-linux-gnu"
define void @merge_double(double* noalias nocapture %st, double* noalias nocapture readonly %ld) #0 {
; CHECK-LABEL: merge_double:
; CHECK: # BB#0:
[SDAG] Relax conditions under stores of loaded values can be merged Summary: Allow consecutive stores whose values come from consecutive loads to merged in the presense of other uses of the loads. Previously this was disallowed as in general the merged load cannot be shared with the other uses. Merging N stores into 1 may cause as many as N redundant loads. However in the context of caching this should have neglible affect on memory pressure and reduce instruction count making it almost always a win. Fixes PR32086. Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30471 llvm-svn: 302712
2017-05-11 03:53:41 +08:00
; CHECK-NEXT: movups (%rsi), %xmm0
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: movups %xmm0, 16(%rdi)
Add test cases for merging stores of multiply used stores llvm-svn: 296667
2017-03-02 04:18:14 +08:00
; CHECK-NEXT: retq
%ld_idx1 = getelementptr inbounds double, double* %ld, i64 1
%ld0 = load double, double* %ld, align 8, !tbaa !2
%ld1 = load double, double* %ld_idx1, align 8, !tbaa !2
%st_idx1 = getelementptr inbounds double, double* %st, i64 1
%st_idx2 = getelementptr inbounds double, double* %st, i64 2
%st_idx3 = getelementptr inbounds double, double* %st, i64 3
store double %ld0, double* %st, align 8, !tbaa !2
store double %ld1, double* %st_idx1, align 8, !tbaa !2
store double %ld0, double* %st_idx2, align 8, !tbaa !2
store double %ld1, double* %st_idx3, align 8, !tbaa !2
ret void
}
define void @merge_loadstore_int(i64* noalias nocapture readonly %p, i64* noalias nocapture %q) local_unnamed_addr #0 {
; CHECK-LABEL: merge_loadstore_int:
; CHECK: # BB#0: # %entry
[SDAG] Relax conditions under stores of loaded values can be merged Summary: Allow consecutive stores whose values come from consecutive loads to merged in the presense of other uses of the loads. Previously this was disallowed as in general the merged load cannot be shared with the other uses. Merging N stores into 1 may cause as many as N redundant loads. However in the context of caching this should have neglible affect on memory pressure and reduce instruction count making it almost always a win. Fixes PR32086. Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30471 llvm-svn: 302712
2017-05-11 03:53:41 +08:00
; CHECK-NEXT: movups (%rdi), %xmm0
; CHECK-NEXT: movups %xmm0, (%rsi)
; CHECK-NEXT: movups %xmm0, 16(%rsi)
Add test cases for merging stores of multiply used stores llvm-svn: 296667
2017-03-02 04:18:14 +08:00
; CHECK-NEXT: retq
entry:
%0 = load i64, i64* %p, align 8, !tbaa !1
%arrayidx1 = getelementptr inbounds i64, i64* %p, i64 1
%1 = load i64, i64* %arrayidx1, align 8, !tbaa !1
store i64 %0, i64* %q, align 8, !tbaa !1
%arrayidx3 = getelementptr inbounds i64, i64* %q, i64 1
store i64 %1, i64* %arrayidx3, align 8, !tbaa !1
%arrayidx4 = getelementptr inbounds i64, i64* %q, i64 2
store i64 %0, i64* %arrayidx4, align 8, !tbaa !1
%arrayidx5 = getelementptr inbounds i64, i64* %q, i64 3
store i64 %1, i64* %arrayidx5, align 8, !tbaa !1
ret void
}
define i64 @merge_loadstore_int_with_extra_use(i64* noalias nocapture readonly %p, i64* noalias nocapture %q) local_unnamed_addr #0 {
; CHECK-LABEL: merge_loadstore_int_with_extra_use:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: movq (%rdi), %rax
[SDAG] Relax conditions under stores of loaded values can be merged Summary: Allow consecutive stores whose values come from consecutive loads to merged in the presense of other uses of the loads. Previously this was disallowed as in general the merged load cannot be shared with the other uses. Merging N stores into 1 may cause as many as N redundant loads. However in the context of caching this should have neglible affect on memory pressure and reduce instruction count making it almost always a win. Fixes PR32086. Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30471 llvm-svn: 302712
2017-05-11 03:53:41 +08:00
; CHECK-NEXT: movups (%rdi), %xmm0
; CHECK-NEXT: movups %xmm0, (%rsi)
; CHECK-NEXT: movups %xmm0, 16(%rsi)
Add test cases for merging stores of multiply used stores llvm-svn: 296667
2017-03-02 04:18:14 +08:00
; CHECK-NEXT: retq
entry:
%0 = load i64, i64* %p, align 8, !tbaa !1
%arrayidx1 = getelementptr inbounds i64, i64* %p, i64 1
%1 = load i64, i64* %arrayidx1, align 8, !tbaa !1
store i64 %0, i64* %q, align 8, !tbaa !1
%arrayidx3 = getelementptr inbounds i64, i64* %q, i64 1
store i64 %1, i64* %arrayidx3, align 8, !tbaa !1
%arrayidx4 = getelementptr inbounds i64, i64* %q, i64 2
store i64 %0, i64* %arrayidx4, align 8, !tbaa !1
%arrayidx5 = getelementptr inbounds i64, i64* %q, i64 3
store i64 %1, i64* %arrayidx5, align 8, !tbaa !1
ret i64 %0
}
attributes #0 = { "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" }
!0 = !{!"clang version 5.0.0 (trunk 296467) (llvm/trunk 296476)"}
!1 = !{!2, !2, i64 0}
!2 = !{!"double", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}