2004-02-24 07:08:11 +08:00
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//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2004-02-24 07:08:11 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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2004-09-30 09:54:45 +08:00
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// This file implements the VirtRegMap class.
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//
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// It also contains implementations of the the Spiller interface, which, given a
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// virtual register map and a machine function, eliminates all virtual
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// references by replacing them with physical register references - adding spill
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2004-02-24 16:58:30 +08:00
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// code as necessary.
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2004-02-24 07:08:11 +08:00
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//
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//===----------------------------------------------------------------------===//
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2004-09-30 09:54:45 +08:00
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#define DEBUG_TYPE "spiller"
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2004-02-24 07:08:11 +08:00
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#include "VirtRegMap.h"
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2004-02-24 16:58:30 +08:00
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#include "llvm/Function.h"
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2004-02-24 07:08:11 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2004-09-30 09:54:45 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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2008-04-12 01:53:36 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 12:13:23 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2004-02-24 07:08:11 +08:00
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#include "llvm/Target/TargetMachine.h"
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2004-02-24 16:58:30 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
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2004-09-02 06:55:40 +08:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2006-08-27 20:54:02 +08:00
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#include "llvm/Support/Compiler.h"
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2007-02-21 10:22:03 +08:00
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#include "llvm/ADT/BitVector.h"
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2004-09-02 06:55:40 +08:00
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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2007-01-23 08:59:48 +08:00
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#include "llvm/ADT/SmallSet.h"
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2004-10-26 23:35:58 +08:00
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#include <algorithm>
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2004-02-24 07:08:11 +08:00
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using namespace llvm;
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2006-12-20 06:41:21 +08:00
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STATISTIC(NumSpills, "Number of register spills");
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2008-03-12 05:34:46 +08:00
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STATISTIC(NumPSpills,"Number of physical register spills");
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2007-03-20 16:13:50 +08:00
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STATISTIC(NumReMats, "Number of re-materialization");
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2007-08-15 07:25:37 +08:00
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STATISTIC(NumDRM , "Number of re-materializable defs elided");
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2006-12-20 06:41:21 +08:00
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STATISTIC(NumStores, "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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STATISTIC(NumReused, "Number of values reused");
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STATISTIC(NumDSE , "Number of dead stores elided");
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STATISTIC(NumDCE , "Number of copies elided");
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2008-02-27 11:04:06 +08:00
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STATISTIC(NumDSS , "Number of dead spill slots removed");
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2004-09-30 09:54:45 +08:00
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2006-12-20 06:41:21 +08:00
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namespace {
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2004-09-30 09:54:45 +08:00
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enum SpillerName { simple, local };
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}
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2008-05-13 08:00:25 +08:00
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static cl::opt<SpillerName>
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SpillerOpt("spiller",
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cl::desc("Spiller to use: (default: local)"),
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cl::Prefix,
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cl::values(clEnumVal(simple, " simple spiller"),
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clEnumVal(local, " local spiller"),
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clEnumValEnd),
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cl::init(local));
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2004-09-30 09:54:45 +08:00
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//===----------------------------------------------------------------------===//
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// VirtRegMap implementation
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//===----------------------------------------------------------------------===//
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2006-09-05 10:12:02 +08:00
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VirtRegMap::VirtRegMap(MachineFunction &mf)
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: TII(*mf.getTarget().getInstrInfo()), MF(mf),
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2007-03-20 16:13:50 +08:00
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Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
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Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
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Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
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2008-02-27 11:04:06 +08:00
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Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1),
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LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) {
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SpillSlotToUsesMap.resize(8);
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2008-04-12 01:53:36 +08:00
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ImplicitDefed.resize(MF.getRegInfo().getLastVirtReg()+1-
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TargetRegisterInfo::FirstVirtualRegister);
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2006-09-05 10:12:02 +08:00
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grow();
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}
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2004-09-30 09:54:45 +08:00
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void VirtRegMap::grow() {
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2007-12-31 12:13:23 +08:00
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unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg();
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2007-08-14 07:45:17 +08:00
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Virt2PhysMap.grow(LastVirtReg);
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Virt2StackSlotMap.grow(LastVirtReg);
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Virt2ReMatIdMap.grow(LastVirtReg);
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Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
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Virt2SplitMap.grow(LastVirtReg);
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2007-12-05 17:51:10 +08:00
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Virt2SplitKillMap.grow(LastVirtReg);
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2007-08-14 07:45:17 +08:00
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ReMatMap.grow(LastVirtReg);
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2008-04-12 01:53:36 +08:00
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ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1);
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2004-02-24 07:08:11 +08:00
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}
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2004-09-30 09:54:45 +08:00
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int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
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2008-02-11 02:45:23 +08:00
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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2004-09-30 10:15:18 +08:00
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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2004-09-30 09:54:45 +08:00
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"attempt to assign stack slot to already spilled register");
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2007-12-31 12:13:23 +08:00
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const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg);
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2008-02-27 11:04:06 +08:00
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int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment());
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if (LowSpillSlot == NO_STACK_SLOT)
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LowSpillSlot = SS;
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if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
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HighSpillSlot = SS;
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unsigned Idx = SS-LowSpillSlot;
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while (Idx >= SpillSlotToUsesMap.size())
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SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
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Virt2StackSlotMap[virtReg] = SS;
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2004-09-30 09:54:45 +08:00
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++NumSpills;
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2008-02-27 11:04:06 +08:00
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return SS;
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2004-02-24 07:08:11 +08:00
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}
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2008-02-27 11:04:06 +08:00
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void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
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2008-02-11 02:45:23 +08:00
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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2004-09-30 10:15:18 +08:00
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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2004-09-30 09:54:45 +08:00
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"attempt to assign stack slot to already spilled register");
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2008-02-27 11:04:06 +08:00
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assert((SS >= 0 ||
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(SS >= MF.getFrameInfo()->getObjectIndexBegin())) &&
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2007-04-04 15:40:01 +08:00
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"illegal fixed frame index");
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2008-02-27 11:04:06 +08:00
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Virt2StackSlotMap[virtReg] = SS;
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2004-05-30 04:38:05 +08:00
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}
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2007-03-20 16:13:50 +08:00
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int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
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2008-02-11 02:45:23 +08:00
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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2007-08-14 07:45:17 +08:00
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assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
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2007-03-20 16:13:50 +08:00
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"attempt to assign re-mat id to already spilled register");
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2007-08-14 07:45:17 +08:00
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Virt2ReMatIdMap[virtReg] = ReMatId;
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2007-03-20 16:13:50 +08:00
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return ReMatId++;
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}
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2007-08-14 07:45:17 +08:00
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void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
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2008-02-11 02:45:23 +08:00
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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2007-08-14 07:45:17 +08:00
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assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign re-mat id to already spilled register");
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Virt2ReMatIdMap[virtReg] = id;
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}
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2008-03-11 15:19:34 +08:00
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int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
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std::map<const TargetRegisterClass*, int>::iterator I =
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EmergencySpillSlots.find(RC);
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if (I != EmergencySpillSlots.end())
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return I->second;
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int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment());
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if (LowSpillSlot == NO_STACK_SLOT)
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LowSpillSlot = SS;
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if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
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HighSpillSlot = SS;
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I->second = SS;
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return SS;
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}
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2008-02-27 11:04:06 +08:00
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void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
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if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) {
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assert(FI >= 0 && "Spill slot index should not be negative!");
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SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
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}
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}
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2004-10-02 07:15:36 +08:00
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void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
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2007-12-02 16:30:39 +08:00
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MachineInstr *NewMI, ModRef MRInfo) {
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2004-10-02 07:15:36 +08:00
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// Move previous memory references folded to new instruction.
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MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
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2005-04-22 06:36:52 +08:00
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for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
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2004-10-02 07:15:36 +08:00
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E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
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MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
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2004-10-01 00:35:08 +08:00
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MI2VirtMap.erase(I++);
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2004-09-30 09:54:45 +08:00
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}
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2004-10-01 00:35:08 +08:00
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2004-09-30 09:54:45 +08:00
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// add new memory reference
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2004-10-02 07:15:36 +08:00
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MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
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2004-09-30 09:54:45 +08:00
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}
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2004-03-02 04:05:10 +08:00
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2007-10-13 10:50:24 +08:00
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void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
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MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
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MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
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}
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2008-02-27 11:04:06 +08:00
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void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isFrameIndex())
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continue;
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int FI = MO.getIndex();
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if (MF.getFrameInfo()->isFixedObjectIndex(FI))
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continue;
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SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
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}
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MI2VirtMap.erase(MI);
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SpillPt2VirtMap.erase(MI);
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RestorePt2VirtMap.erase(MI);
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2008-03-11 15:19:34 +08:00
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EmergencySpillMap.erase(MI);
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2008-02-27 11:04:06 +08:00
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}
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2004-09-30 10:15:18 +08:00
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void VirtRegMap::print(std::ostream &OS) const {
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2008-02-11 02:45:23 +08:00
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const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo();
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2004-09-30 09:54:45 +08:00
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2004-09-30 10:15:18 +08:00
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OS << "********** REGISTER MAP **********\n";
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2008-02-11 02:45:23 +08:00
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for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
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2007-12-31 12:13:23 +08:00
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e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
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2004-09-30 10:15:18 +08:00
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if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
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2008-02-27 05:47:57 +08:00
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OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
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2008-02-27 05:11:01 +08:00
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<< "]\n";
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2004-09-30 09:54:45 +08:00
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}
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2008-02-11 02:45:23 +08:00
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for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
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2007-12-31 12:13:23 +08:00
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e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i)
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2004-09-30 10:15:18 +08:00
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if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
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OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
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OS << '\n';
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2004-03-02 04:05:10 +08:00
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}
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2006-11-17 10:09:07 +08:00
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void VirtRegMap::dump() const {
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2008-03-13 04:52:10 +08:00
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print(cerr);
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2006-11-17 10:09:07 +08:00
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}
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2004-02-24 07:08:11 +08:00
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2004-02-24 16:58:30 +08:00
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2004-09-30 09:54:45 +08:00
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//===----------------------------------------------------------------------===//
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// Simple Spiller Implementation
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//===----------------------------------------------------------------------===//
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2004-03-02 07:18:15 +08:00
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2004-09-30 09:54:45 +08:00
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Spiller::~Spiller() {}
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2004-03-02 07:18:15 +08:00
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2004-02-24 16:58:30 +08:00
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namespace {
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2006-06-29 06:17:39 +08:00
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struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
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2006-05-02 05:16:03 +08:00
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bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
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2004-09-30 09:54:45 +08:00
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};
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}
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2004-02-24 16:58:30 +08:00
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2006-05-02 05:16:03 +08:00
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bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
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2006-11-17 10:09:07 +08:00
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DOUT << "********** REWRITE MACHINE CODE **********\n";
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DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
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2005-01-24 06:45:13 +08:00
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const TargetMachine &TM = MF.getTarget();
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2008-01-02 05:11:32 +08:00
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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2004-09-30 09:54:45 +08:00
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2004-09-30 10:33:48 +08:00
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// LoadedRegs - Keep track of which vregs are loaded, so that we only load
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// each vreg once (in the case where a spilled vreg is used by multiple
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// operands). This is always smaller than the number of operands to the
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// current machine instr, so it should be small.
|
|
|
|
std::vector<unsigned> LoadedRegs;
|
2004-09-30 09:54:45 +08:00
|
|
|
|
2004-09-30 10:59:33 +08:00
|
|
|
for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
|
|
|
|
MBBI != E; ++MBBI) {
|
2006-11-17 10:09:07 +08:00
|
|
|
DOUT << MBBI->getBasicBlock()->getName() << ":\n";
|
2004-09-30 10:59:33 +08:00
|
|
|
MachineBasicBlock &MBB = *MBBI;
|
|
|
|
for (MachineBasicBlock::iterator MII = MBB.begin(),
|
|
|
|
E = MBB.end(); MII != E; ++MII) {
|
|
|
|
MachineInstr &MI = *MII;
|
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
MachineOperand &MO = MI.getOperand(i);
|
2008-02-20 19:10:28 +08:00
|
|
|
if (MO.isRegister() && MO.getReg()) {
|
2008-02-11 02:45:23 +08:00
|
|
|
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
|
2005-04-05 05:35:34 +08:00
|
|
|
unsigned VirtReg = MO.getReg();
|
|
|
|
unsigned PhysReg = VRM.getPhys(VirtReg);
|
2007-08-14 07:45:17 +08:00
|
|
|
if (!VRM.isAssignedReg(VirtReg)) {
|
2005-04-05 05:35:34 +08:00
|
|
|
int StackSlot = VRM.getStackSlot(VirtReg);
|
2005-09-30 09:29:00 +08:00
|
|
|
const TargetRegisterClass* RC =
|
2007-12-31 12:13:23 +08:00
|
|
|
MF.getRegInfo().getRegClass(VirtReg);
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2005-04-05 05:35:34 +08:00
|
|
|
if (MO.isUse() &&
|
|
|
|
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
|
|
|
|
== LoadedRegs.end()) {
|
2008-01-02 05:11:32 +08:00
|
|
|
TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
|
2008-02-27 11:04:06 +08:00
|
|
|
MachineInstr *LoadMI = prior(MII);
|
|
|
|
VRM.addSpillSlotUse(StackSlot, LoadMI);
|
2005-04-05 05:35:34 +08:00
|
|
|
LoadedRegs.push_back(VirtReg);
|
|
|
|
++NumLoads;
|
2008-02-27 11:04:06 +08:00
|
|
|
DOUT << '\t' << *LoadMI;
|
2005-04-05 05:35:34 +08:00
|
|
|
}
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2005-04-05 05:35:34 +08:00
|
|
|
if (MO.isDef()) {
|
2008-01-02 05:11:32 +08:00
|
|
|
TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
|
2007-12-05 11:14:33 +08:00
|
|
|
StackSlot, RC);
|
2008-02-27 11:04:06 +08:00
|
|
|
MachineInstr *StoreMI = next(MII);
|
|
|
|
VRM.addSpillSlotUse(StackSlot, StoreMI);
|
2005-04-05 05:35:34 +08:00
|
|
|
++NumStores;
|
|
|
|
}
|
2004-09-30 10:59:33 +08:00
|
|
|
}
|
2007-12-31 12:13:23 +08:00
|
|
|
MF.getRegInfo().setPhysRegUsed(PhysReg);
|
2006-05-05 01:52:23 +08:00
|
|
|
MI.getOperand(i).setReg(PhysReg);
|
2005-04-05 05:35:34 +08:00
|
|
|
} else {
|
2007-12-31 12:13:23 +08:00
|
|
|
MF.getRegInfo().setPhysRegUsed(MO.getReg());
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
2008-02-20 19:10:28 +08:00
|
|
|
}
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
2005-04-05 05:35:34 +08:00
|
|
|
|
2006-11-17 10:09:07 +08:00
|
|
|
DOUT << '\t' << MI;
|
2004-09-30 10:33:48 +08:00
|
|
|
LoadedRegs.clear();
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
2004-02-24 16:58:30 +08:00
|
|
|
|
2004-09-30 09:54:45 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Local Spiller Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
2004-02-24 16:58:30 +08:00
|
|
|
|
2004-09-30 09:54:45 +08:00
|
|
|
namespace {
|
2007-10-20 05:23:22 +08:00
|
|
|
class AvailableSpills;
|
|
|
|
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
/// LocalSpiller - This spiller does a simple pass over the machine basic
|
|
|
|
/// block to attempt to keep spills in registers as much as possible for
|
|
|
|
/// blocks that have low register pressure (the vreg may be spilled due to
|
|
|
|
/// register pressure in other blocks).
|
2006-06-29 06:17:39 +08:00
|
|
|
class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
|
2007-12-31 12:13:23 +08:00
|
|
|
MachineRegisterInfo *RegInfo;
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetRegisterInfo *TRI;
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
const TargetInstrInfo *TII;
|
2008-05-20 16:13:21 +08:00
|
|
|
DenseMap<MachineInstr*, unsigned> DistanceMap;
|
2004-09-30 09:54:45 +08:00
|
|
|
public:
|
2006-05-02 05:16:03 +08:00
|
|
|
bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
|
2007-12-31 12:13:23 +08:00
|
|
|
RegInfo = &MF.getRegInfo();
|
2008-02-11 02:45:23 +08:00
|
|
|
TRI = MF.getTarget().getRegisterInfo();
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
TII = MF.getTarget().getInstrInfo();
|
2006-11-17 10:09:07 +08:00
|
|
|
DOUT << "\n**** Local spiller rewriting function '"
|
|
|
|
<< MF.getFunction()->getName() << "':\n";
|
2007-12-31 12:13:23 +08:00
|
|
|
DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)"
|
|
|
|
" ****\n";
|
2007-09-07 00:36:39 +08:00
|
|
|
DEBUG(MF.dump());
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
|
|
|
|
for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
|
|
|
|
MBB != E; ++MBB)
|
2007-08-14 07:45:17 +08:00
|
|
|
RewriteMBB(*MBB, VRM);
|
2007-09-07 00:36:39 +08:00
|
|
|
|
2008-02-27 11:04:06 +08:00
|
|
|
// Mark unused spill slots.
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
int SS = VRM.getLowSpillSlot();
|
|
|
|
if (SS != VirtRegMap::NO_STACK_SLOT)
|
|
|
|
for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS)
|
|
|
|
if (!VRM.isSpillSlotUsed(SS)) {
|
|
|
|
MFI->RemoveStackObject(SS);
|
|
|
|
++NumDSS;
|
|
|
|
}
|
|
|
|
|
2007-09-07 00:36:39 +08:00
|
|
|
DOUT << "**** Post Machine Instrs ****\n";
|
|
|
|
DEBUG(MF.dump());
|
|
|
|
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
return true;
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
private:
|
2008-05-20 16:13:21 +08:00
|
|
|
void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
|
|
|
|
unsigned Reg, BitVector &RegKills,
|
|
|
|
std::vector<MachineOperand*> &KillOps);
|
2007-10-20 05:23:22 +08:00
|
|
|
bool PrepForUnfoldOpti(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MII,
|
|
|
|
std::vector<MachineInstr*> &MaybeDeadStores,
|
|
|
|
AvailableSpills &Spills, BitVector &RegKills,
|
|
|
|
std::vector<MachineOperand*> &KillOps,
|
|
|
|
VirtRegMap &VRM);
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
void SpillRegToStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MII,
|
|
|
|
int Idx, unsigned PhysReg, int StackSlot,
|
|
|
|
const TargetRegisterClass *RC,
|
2007-12-05 03:19:45 +08:00
|
|
|
bool isAvailable, MachineInstr *&LastStore,
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
AvailableSpills &Spills,
|
|
|
|
SmallSet<MachineInstr*, 4> &ReMatDefs,
|
|
|
|
BitVector &RegKills,
|
|
|
|
std::vector<MachineOperand*> &KillOps,
|
2007-12-04 05:31:55 +08:00
|
|
|
VirtRegMap &VRM);
|
2007-08-14 07:45:17 +08:00
|
|
|
void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
|
2004-09-30 09:54:45 +08:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2006-02-04 07:13:58 +08:00
|
|
|
/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
|
2007-08-14 07:45:17 +08:00
|
|
|
/// top down, keep track of which spills slots or remat are available in each
|
|
|
|
/// register.
|
2006-02-04 07:28:46 +08:00
|
|
|
///
|
|
|
|
/// Note that not all physregs are created equal here. In particular, some
|
|
|
|
/// physregs are reloads that we are allowed to clobber or ignore at any time.
|
|
|
|
/// Other physregs are values that the register allocated program is using that
|
|
|
|
/// we cannot CHANGE, but we can read if we like. We keep track of this on a
|
2007-08-14 07:45:17 +08:00
|
|
|
/// per-stack-slot / remat id basis as the low bit in the value of the
|
|
|
|
/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
|
|
|
|
/// this bit and addAvailable sets it if.
|
2006-06-29 06:17:39 +08:00
|
|
|
namespace {
|
|
|
|
class VISIBILITY_HIDDEN AvailableSpills {
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetRegisterInfo *TRI;
|
2006-02-04 07:13:58 +08:00
|
|
|
const TargetInstrInfo *TII;
|
|
|
|
|
2007-08-14 07:45:17 +08:00
|
|
|
// SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
|
|
|
|
// or remat'ed virtual register values that are still available, due to being
|
|
|
|
// loaded or stored to, but not invalidated yet.
|
|
|
|
std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
|
2006-02-04 07:13:58 +08:00
|
|
|
|
2007-08-14 07:45:17 +08:00
|
|
|
// PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
|
|
|
|
// indicating which stack slot values are currently held by a physreg. This
|
|
|
|
// is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
|
|
|
|
// physreg is modified.
|
2006-02-04 07:13:58 +08:00
|
|
|
std::multimap<unsigned, int> PhysRegsAvailable;
|
|
|
|
|
2006-12-14 15:54:05 +08:00
|
|
|
void disallowClobberPhysRegOnly(unsigned PhysReg);
|
|
|
|
|
2006-02-04 07:13:58 +08:00
|
|
|
void ClobberPhysRegOnly(unsigned PhysReg);
|
|
|
|
public:
|
2008-02-11 02:45:23 +08:00
|
|
|
AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
|
|
|
|
: TRI(tri), TII(tii) {
|
2006-02-04 07:13:58 +08:00
|
|
|
}
|
|
|
|
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetRegisterInfo *getRegInfo() const { return TRI; }
|
2007-02-23 09:13:26 +08:00
|
|
|
|
2007-08-14 07:45:17 +08:00
|
|
|
/// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
|
|
|
|
/// available in a physical register, return that PhysReg, otherwise
|
|
|
|
/// return 0.
|
|
|
|
unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
|
|
|
|
std::map<int, unsigned>::const_iterator I =
|
|
|
|
SpillSlotsOrReMatsAvailable.find(Slot);
|
|
|
|
if (I != SpillSlotsOrReMatsAvailable.end()) {
|
2007-07-11 16:47:44 +08:00
|
|
|
return I->second >> 1; // Remove the CanClobber bit.
|
2007-02-23 09:13:26 +08:00
|
|
|
}
|
2006-02-04 07:13:58 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2007-02-25 17:51:27 +08:00
|
|
|
|
2007-08-14 07:45:17 +08:00
|
|
|
/// addAvailable - Mark that the specified stack slot / remat is available in
|
|
|
|
/// the specified physreg. If CanClobber is true, the physreg can be modified
|
|
|
|
/// at any time without changing the semantics of the program.
|
|
|
|
void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
|
2007-02-23 09:13:26 +08:00
|
|
|
bool CanClobber = true) {
|
2006-02-04 07:50:46 +08:00
|
|
|
// If this stack slot is thought to be available in some other physreg,
|
|
|
|
// remove its record.
|
2007-08-14 07:45:17 +08:00
|
|
|
ModifyStackSlotOrReMat(SlotOrReMat);
|
2006-02-04 07:50:46 +08:00
|
|
|
|
2007-08-14 07:45:17 +08:00
|
|
|
PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
|
2007-08-16 04:20:34 +08:00
|
|
|
SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber;
|
2006-02-04 07:13:58 +08:00
|
|
|
|
2007-08-14 07:45:17 +08:00
|
|
|
if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
|
|
|
|
DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
|
2007-03-20 16:13:50 +08:00
|
|
|
else
|
2007-08-14 07:45:17 +08:00
|
|
|
DOUT << "Remembering SS#" << SlotOrReMat;
|
2008-02-27 05:47:57 +08:00
|
|
|
DOUT << " in physreg " << TRI->getName(Reg) << "\n";
|
2006-02-04 07:13:58 +08:00
|
|
|
}
|
2006-12-14 15:54:05 +08:00
|
|
|
|
2006-02-04 07:28:46 +08:00
|
|
|
/// canClobberPhysReg - Return true if the spiller is allowed to change the
|
|
|
|
/// value of the specified stackslot register if it desires. The specified
|
|
|
|
/// stack slot must be available in a physreg for this query to make sense.
|
2007-08-14 07:45:17 +08:00
|
|
|
bool canClobberPhysReg(int SlotOrReMat) const {
|
2007-08-16 04:20:34 +08:00
|
|
|
assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
|
|
|
|
"Value not available!");
|
2007-08-14 07:45:17 +08:00
|
|
|
return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
|
2006-02-04 07:28:46 +08:00
|
|
|
}
|
2007-12-05 03:19:45 +08:00
|
|
|
|
2006-12-14 15:54:05 +08:00
|
|
|
/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
|
|
|
|
/// stackslot register. The register is still available but is no longer
|
|
|
|
/// allowed to be modifed.
|
|
|
|
void disallowClobberPhysReg(unsigned PhysReg);
|
|
|
|
|
2006-02-04 07:13:58 +08:00
|
|
|
/// ClobberPhysReg - This is called when the specified physreg changes
|
2007-10-20 05:23:22 +08:00
|
|
|
/// value. We use this to invalidate any info about stuff that lives in
|
2006-02-04 07:13:58 +08:00
|
|
|
/// it and any of its aliases.
|
|
|
|
void ClobberPhysReg(unsigned PhysReg);
|
|
|
|
|
2007-08-16 04:20:34 +08:00
|
|
|
/// ModifyStackSlotOrReMat - This method is called when the value in a stack
|
|
|
|
/// slot changes. This removes information about which register the previous
|
|
|
|
/// value for this slot lives in (as the previous value is dead now).
|
2007-08-14 07:45:17 +08:00
|
|
|
void ModifyStackSlotOrReMat(int SlotOrReMat);
|
2006-02-04 07:13:58 +08:00
|
|
|
};
|
2006-06-29 06:17:39 +08:00
|
|
|
}
|
2006-02-04 07:13:58 +08:00
|
|
|
|
2006-12-14 15:54:05 +08:00
|
|
|
/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
|
|
|
|
/// stackslot register. The register is still available but is no longer
|
|
|
|
/// allowed to be modifed.
|
|
|
|
void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
|
|
|
|
std::multimap<unsigned, int>::iterator I =
|
|
|
|
PhysRegsAvailable.lower_bound(PhysReg);
|
|
|
|
while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
|
2007-08-14 07:45:17 +08:00
|
|
|
int SlotOrReMat = I->second;
|
2006-12-14 15:54:05 +08:00
|
|
|
I++;
|
2007-08-14 07:45:17 +08:00
|
|
|
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
|
2006-12-14 15:54:05 +08:00
|
|
|
"Bidirectional map mismatch!");
|
2007-08-14 07:45:17 +08:00
|
|
|
SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
|
2008-02-27 05:47:57 +08:00
|
|
|
DOUT << "PhysReg " << TRI->getName(PhysReg)
|
2006-12-14 15:54:05 +08:00
|
|
|
<< " copied, it is available for use but can no longer be modified\n";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
|
|
|
|
/// stackslot register and its aliases. The register and its aliases may
|
|
|
|
/// still available but is no longer allowed to be modifed.
|
|
|
|
void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
|
2008-02-11 02:45:23 +08:00
|
|
|
for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
|
2006-12-14 15:54:05 +08:00
|
|
|
disallowClobberPhysRegOnly(*AS);
|
|
|
|
disallowClobberPhysRegOnly(PhysReg);
|
|
|
|
}
|
|
|
|
|
2006-02-04 07:13:58 +08:00
|
|
|
/// ClobberPhysRegOnly - This is called when the specified physreg changes
|
|
|
|
/// value. We use this to invalidate any info about stuff we thing lives in it.
|
|
|
|
void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
|
|
|
|
std::multimap<unsigned, int>::iterator I =
|
|
|
|
PhysRegsAvailable.lower_bound(PhysReg);
|
Physregs may hold multiple stack slot values at the same time. Keep track
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 08:36:31 +08:00
|
|
|
while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
|
2007-08-14 07:45:17 +08:00
|
|
|
int SlotOrReMat = I->second;
|
Physregs may hold multiple stack slot values at the same time. Keep track
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 08:36:31 +08:00
|
|
|
PhysRegsAvailable.erase(I++);
|
2007-08-14 07:45:17 +08:00
|
|
|
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
|
2006-02-04 07:13:58 +08:00
|
|
|
"Bidirectional map mismatch!");
|
2007-08-14 07:45:17 +08:00
|
|
|
SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
|
2008-02-27 05:47:57 +08:00
|
|
|
DOUT << "PhysReg " << TRI->getName(PhysReg)
|
2007-03-20 16:13:50 +08:00
|
|
|
<< " clobbered, invalidating ";
|
2007-08-14 07:45:17 +08:00
|
|
|
if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
|
|
|
|
DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
|
2007-03-20 16:13:50 +08:00
|
|
|
else
|
2007-08-14 07:45:17 +08:00
|
|
|
DOUT << "SS#" << SlotOrReMat << "\n";
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
|
|
|
}
|
2004-02-24 16:58:30 +08:00
|
|
|
|
2006-02-04 07:13:58 +08:00
|
|
|
/// ClobberPhysReg - This is called when the specified physreg changes
|
|
|
|
/// value. We use this to invalidate any info about stuff we thing lives in
|
|
|
|
/// it and any of its aliases.
|
|
|
|
void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
|
2008-02-11 02:45:23 +08:00
|
|
|
for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
|
2006-02-04 07:13:58 +08:00
|
|
|
ClobberPhysRegOnly(*AS);
|
|
|
|
ClobberPhysRegOnly(PhysReg);
|
Physregs may hold multiple stack slot values at the same time. Keep track
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 08:36:31 +08:00
|
|
|
}
|
|
|
|
|
2007-08-16 04:20:34 +08:00
|
|
|
/// ModifyStackSlotOrReMat - This method is called when the value in a stack
|
|
|
|
/// slot changes. This removes information about which register the previous
|
|
|
|
/// value for this slot lives in (as the previous value is dead now).
|
2007-08-14 07:45:17 +08:00
|
|
|
void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
|
2007-08-16 04:20:34 +08:00
|
|
|
std::map<int, unsigned>::iterator It =
|
|
|
|
SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
|
2007-08-14 07:45:17 +08:00
|
|
|
if (It == SpillSlotsOrReMatsAvailable.end()) return;
|
2007-07-11 16:47:44 +08:00
|
|
|
unsigned Reg = It->second >> 1;
|
2007-08-14 07:45:17 +08:00
|
|
|
SpillSlotsOrReMatsAvailable.erase(It);
|
Physregs may hold multiple stack slot values at the same time. Keep track
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 08:36:31 +08:00
|
|
|
|
|
|
|
// This register may hold the value of multiple stack slots, only remove this
|
|
|
|
// stack slot from the set of values the register contains.
|
|
|
|
std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
|
|
|
|
for (; ; ++I) {
|
|
|
|
assert(I != PhysRegsAvailable.end() && I->first == Reg &&
|
|
|
|
"Map inverse broken!");
|
2007-08-14 07:45:17 +08:00
|
|
|
if (I->second == SlotOrReMat) break;
|
Physregs may hold multiple stack slot values at the same time. Keep track
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 08:36:31 +08:00
|
|
|
}
|
|
|
|
PhysRegsAvailable.erase(I);
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
Physregs may hold multiple stack slot values at the same time. Keep track
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 08:36:31 +08:00
|
|
|
|
2007-07-12 03:17:18 +08:00
|
|
|
/// InvalidateKills - MI is going to be deleted. If any of its operands are
|
|
|
|
/// marked kill, then invalidate the information.
|
|
|
|
static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
|
2007-08-15 04:23:13 +08:00
|
|
|
std::vector<MachineOperand*> &KillOps,
|
2007-10-20 05:23:22 +08:00
|
|
|
SmallVector<unsigned, 2> *KillRegs = NULL) {
|
2007-07-12 03:17:18 +08:00
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI.getOperand(i);
|
2007-09-15 04:33:02 +08:00
|
|
|
if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
|
2007-07-12 03:17:18 +08:00
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
2007-08-15 07:25:37 +08:00
|
|
|
if (KillRegs)
|
|
|
|
KillRegs->push_back(Reg);
|
2007-07-12 03:17:18 +08:00
|
|
|
if (KillOps[Reg] == &MO) {
|
|
|
|
RegKills.reset(Reg);
|
|
|
|
KillOps[Reg] = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-12-12 07:36:57 +08:00
|
|
|
/// InvalidateKill - A MI that defines the specified register is being deleted,
|
|
|
|
/// invalidate the register kill information.
|
|
|
|
static void InvalidateKill(unsigned Reg, BitVector &RegKills,
|
|
|
|
std::vector<MachineOperand*> &KillOps) {
|
|
|
|
if (RegKills[Reg]) {
|
2007-12-31 05:56:09 +08:00
|
|
|
KillOps[Reg]->setIsKill(false);
|
2007-12-12 07:36:57 +08:00
|
|
|
KillOps[Reg] = NULL;
|
|
|
|
RegKills.reset(Reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-08-15 07:25:37 +08:00
|
|
|
/// InvalidateRegDef - If the def operand of the specified def MI is now dead
|
|
|
|
/// (since it's spill instruction is removed), mark it isDead. Also checks if
|
|
|
|
/// the def MI has other definition operands that are not dead. Returns it by
|
|
|
|
/// reference.
|
|
|
|
static bool InvalidateRegDef(MachineBasicBlock::iterator I,
|
|
|
|
MachineInstr &NewDef, unsigned Reg,
|
|
|
|
bool &HasLiveDef) {
|
|
|
|
// Due to remat, it's possible this reg isn't being reused. That is,
|
|
|
|
// the def of this reg (by prev MI) is now dead.
|
|
|
|
MachineInstr *DefMI = I;
|
|
|
|
MachineOperand *DefOp = NULL;
|
|
|
|
for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = DefMI->getOperand(i);
|
2007-09-15 04:33:02 +08:00
|
|
|
if (MO.isRegister() && MO.isDef()) {
|
2007-08-15 07:25:37 +08:00
|
|
|
if (MO.getReg() == Reg)
|
|
|
|
DefOp = &MO;
|
|
|
|
else if (!MO.isDead())
|
|
|
|
HasLiveDef = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!DefOp)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
bool FoundUse = false, Done = false;
|
|
|
|
MachineBasicBlock::iterator E = NewDef;
|
|
|
|
++I; ++E;
|
|
|
|
for (; !Done && I != E; ++I) {
|
|
|
|
MachineInstr *NMI = I;
|
|
|
|
for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
|
|
|
|
MachineOperand &MO = NMI->getOperand(j);
|
2007-09-15 04:33:02 +08:00
|
|
|
if (!MO.isRegister() || MO.getReg() != Reg)
|
2007-08-15 07:25:37 +08:00
|
|
|
continue;
|
|
|
|
if (MO.isUse())
|
|
|
|
FoundUse = true;
|
|
|
|
Done = true; // Stop after scanning all the operands of this MI.
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!FoundUse) {
|
|
|
|
// Def is dead!
|
|
|
|
DefOp->setIsDead();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-07-12 03:17:18 +08:00
|
|
|
/// UpdateKills - Track and update kill info. If a MI reads a register that is
|
|
|
|
/// marked kill, then it must be due to register reuse. Transfer the kill info
|
|
|
|
/// over.
|
|
|
|
static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
|
|
|
|
std::vector<MachineOperand*> &KillOps) {
|
2008-01-07 15:27:27 +08:00
|
|
|
const TargetInstrDesc &TID = MI.getDesc();
|
2007-07-12 03:17:18 +08:00
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI.getOperand(i);
|
2007-09-15 04:33:02 +08:00
|
|
|
if (!MO.isRegister() || !MO.isUse())
|
2007-07-12 03:17:18 +08:00
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (Reg == 0)
|
|
|
|
continue;
|
|
|
|
|
2008-03-22 03:09:30 +08:00
|
|
|
if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) {
|
2007-07-12 03:17:18 +08:00
|
|
|
// That can't be right. Register is killed but not re-defined and it's
|
|
|
|
// being reused. Let's fix that.
|
2007-12-31 05:56:09 +08:00
|
|
|
KillOps[Reg]->setIsKill(false);
|
2007-12-12 07:36:57 +08:00
|
|
|
KillOps[Reg] = NULL;
|
|
|
|
RegKills.reset(Reg);
|
2008-01-07 15:27:27 +08:00
|
|
|
if (i < TID.getNumOperands() &&
|
|
|
|
TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
|
2007-07-12 03:17:18 +08:00
|
|
|
// Unless it's a two-address operand, this is the new kill.
|
|
|
|
MO.setIsKill();
|
|
|
|
}
|
|
|
|
if (MO.isKill()) {
|
|
|
|
RegKills.set(Reg);
|
|
|
|
KillOps[Reg] = &MO;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = MI.getOperand(i);
|
2007-09-15 04:33:02 +08:00
|
|
|
if (!MO.isRegister() || !MO.isDef())
|
2007-07-12 03:17:18 +08:00
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
RegKills.reset(Reg);
|
|
|
|
KillOps[Reg] = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-02-22 17:24:50 +08:00
|
|
|
/// ReMaterialize - Re-materialize definition for Reg targetting DestReg.
|
|
|
|
///
|
|
|
|
static void ReMaterialize(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MII,
|
|
|
|
unsigned DestReg, unsigned Reg,
|
2008-04-01 04:40:39 +08:00
|
|
|
const TargetInstrInfo *TII,
|
2008-02-22 17:24:50 +08:00
|
|
|
const TargetRegisterInfo *TRI,
|
|
|
|
VirtRegMap &VRM) {
|
2008-04-01 04:40:39 +08:00
|
|
|
TII->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg));
|
2008-02-22 17:24:50 +08:00
|
|
|
MachineInstr *NewMI = prior(MII);
|
|
|
|
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = NewMI->getOperand(i);
|
|
|
|
if (!MO.isRegister() || MO.getReg() == 0)
|
|
|
|
continue;
|
|
|
|
unsigned VirtReg = MO.getReg();
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
|
|
|
|
continue;
|
|
|
|
assert(MO.isUse());
|
|
|
|
unsigned SubIdx = MO.getSubReg();
|
|
|
|
unsigned Phys = VRM.getPhys(VirtReg);
|
|
|
|
assert(Phys);
|
|
|
|
unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
|
|
|
|
MO.setReg(RReg);
|
|
|
|
}
|
|
|
|
++NumReMats;
|
|
|
|
}
|
|
|
|
|
2007-07-12 03:17:18 +08:00
|
|
|
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
// ReusedOp - For each reused operand, we keep track of a bit of information, in
|
|
|
|
// case we need to rollback upon processing a new operand. See comments below.
|
|
|
|
namespace {
|
|
|
|
struct ReusedOp {
|
|
|
|
// The MachineInstr operand that reused an available value.
|
|
|
|
unsigned Operand;
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2007-08-14 07:45:17 +08:00
|
|
|
// StackSlotOrReMat - The spill slot or remat id of the value being reused.
|
|
|
|
unsigned StackSlotOrReMat;
|
2005-04-22 06:36:52 +08:00
|
|
|
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
// PhysRegReused - The physical register the value was available in.
|
|
|
|
unsigned PhysRegReused;
|
2005-04-22 06:36:52 +08:00
|
|
|
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
// AssignedPhysReg - The physreg that was assigned for use by the reload.
|
|
|
|
unsigned AssignedPhysReg;
|
2005-10-07 01:19:06 +08:00
|
|
|
|
|
|
|
// VirtReg - The virtual register itself.
|
|
|
|
unsigned VirtReg;
|
|
|
|
|
|
|
|
ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
|
|
|
|
unsigned vreg)
|
2007-08-16 04:20:34 +08:00
|
|
|
: Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
|
|
|
|
AssignedPhysReg(apr), VirtReg(vreg) {}
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
};
|
2006-02-25 09:51:33 +08:00
|
|
|
|
|
|
|
/// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
|
|
|
|
/// is reused instead of reloaded.
|
2006-06-29 06:17:39 +08:00
|
|
|
class VISIBILITY_HIDDEN ReuseInfo {
|
2006-02-25 09:51:33 +08:00
|
|
|
MachineInstr &MI;
|
|
|
|
std::vector<ReusedOp> Reuses;
|
2007-02-21 10:22:03 +08:00
|
|
|
BitVector PhysRegsClobbered;
|
2006-02-25 09:51:33 +08:00
|
|
|
public:
|
2008-02-11 02:45:23 +08:00
|
|
|
ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
|
|
|
|
PhysRegsClobbered.resize(tri->getNumRegs());
|
2006-11-04 08:21:55 +08:00
|
|
|
}
|
2006-02-25 09:51:33 +08:00
|
|
|
|
|
|
|
bool hasReuses() const {
|
|
|
|
return !Reuses.empty();
|
|
|
|
}
|
|
|
|
|
|
|
|
/// addReuse - If we choose to reuse a virtual register that is already
|
|
|
|
/// available instead of reloading it, remember that we did so.
|
2007-08-14 07:45:17 +08:00
|
|
|
void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
|
2006-02-25 09:51:33 +08:00
|
|
|
unsigned PhysRegReused, unsigned AssignedPhysReg,
|
|
|
|
unsigned VirtReg) {
|
|
|
|
// If the reload is to the assigned register anyway, no undo will be
|
|
|
|
// required.
|
|
|
|
if (PhysRegReused == AssignedPhysReg) return;
|
|
|
|
|
|
|
|
// Otherwise, remember this.
|
2007-08-14 07:45:17 +08:00
|
|
|
Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
|
2006-02-25 09:51:33 +08:00
|
|
|
AssignedPhysReg, VirtReg));
|
|
|
|
}
|
2006-11-04 08:21:55 +08:00
|
|
|
|
|
|
|
void markClobbered(unsigned PhysReg) {
|
2007-02-21 10:22:03 +08:00
|
|
|
PhysRegsClobbered.set(PhysReg);
|
2006-11-04 08:21:55 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool isClobbered(unsigned PhysReg) const {
|
2007-02-21 10:22:03 +08:00
|
|
|
return PhysRegsClobbered.test(PhysReg);
|
2006-11-04 08:21:55 +08:00
|
|
|
}
|
2006-02-25 09:51:33 +08:00
|
|
|
|
|
|
|
/// GetRegForReload - We are about to emit a reload into PhysReg. If there
|
|
|
|
/// is some other operand that is using the specified register, either pick
|
|
|
|
/// a new register to use, or evict the previous reload and use this reg.
|
|
|
|
unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
|
|
|
|
AvailableSpills &Spills,
|
2007-08-14 17:11:18 +08:00
|
|
|
std::vector<MachineInstr*> &MaybeDeadStores,
|
2007-07-12 03:17:18 +08:00
|
|
|
SmallSet<unsigned, 8> &Rejected,
|
|
|
|
BitVector &RegKills,
|
2007-08-14 07:45:17 +08:00
|
|
|
std::vector<MachineOperand*> &KillOps,
|
|
|
|
VirtRegMap &VRM) {
|
2008-01-02 05:11:32 +08:00
|
|
|
const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget()
|
|
|
|
.getInstrInfo();
|
|
|
|
|
2006-02-25 09:51:33 +08:00
|
|
|
if (Reuses.empty()) return PhysReg; // This is most often empty.
|
|
|
|
|
|
|
|
for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
|
|
|
|
ReusedOp &Op = Reuses[ro];
|
|
|
|
// If we find some other reuse that was supposed to use this register
|
|
|
|
// exactly for its reload, we can change this reload to use ITS reload
|
2007-01-20 06:40:14 +08:00
|
|
|
// register. That is, unless its reload register has already been
|
|
|
|
// considered and subsequently rejected because it has also been reused
|
|
|
|
// by another operand.
|
|
|
|
if (Op.PhysRegReused == PhysReg &&
|
|
|
|
Rejected.count(Op.AssignedPhysReg) == 0) {
|
2006-02-25 09:51:33 +08:00
|
|
|
// Yup, use the reload register that we didn't use before.
|
2007-01-20 06:40:14 +08:00
|
|
|
unsigned NewReg = Op.AssignedPhysReg;
|
|
|
|
Rejected.insert(PhysReg);
|
2007-07-12 03:17:18 +08:00
|
|
|
return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
|
2007-08-14 07:45:17 +08:00
|
|
|
RegKills, KillOps, VRM);
|
2006-02-25 09:51:33 +08:00
|
|
|
} else {
|
|
|
|
// Otherwise, we might also have a problem if a previously reused
|
|
|
|
// value aliases the new register. If so, codegen the previous reload
|
|
|
|
// and use this one.
|
|
|
|
unsigned PRRU = Op.PhysRegReused;
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetRegisterInfo *TRI = Spills.getRegInfo();
|
|
|
|
if (TRI->areAliases(PRRU, PhysReg)) {
|
2006-02-25 09:51:33 +08:00
|
|
|
// Okay, we found out that an alias of a reused register
|
|
|
|
// was used. This isn't good because it means we have
|
|
|
|
// to undo a previous reuse.
|
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
const TargetRegisterClass *AliasRC =
|
2007-12-31 12:13:23 +08:00
|
|
|
MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
|
2006-02-25 10:17:31 +08:00
|
|
|
|
|
|
|
// Copy Op out of the vector and remove it, we're going to insert an
|
|
|
|
// explicit load for it.
|
|
|
|
ReusedOp NewOp = Op;
|
|
|
|
Reuses.erase(Reuses.begin()+ro);
|
|
|
|
|
|
|
|
// Ok, we're going to try to reload the assigned physreg into the
|
|
|
|
// slot that we were supposed to in the first place. However, that
|
|
|
|
// register could hold a reuse. Check to see if it conflicts or
|
|
|
|
// would prefer us to use a different register.
|
|
|
|
unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
|
2007-07-12 03:17:18 +08:00
|
|
|
MI, Spills, MaybeDeadStores,
|
2007-08-14 07:45:17 +08:00
|
|
|
Rejected, RegKills, KillOps, VRM);
|
2006-02-25 10:17:31 +08:00
|
|
|
|
2008-02-22 17:24:50 +08:00
|
|
|
MachineBasicBlock::iterator MII = MI;
|
2007-08-14 07:45:17 +08:00
|
|
|
if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
|
2008-04-01 04:40:39 +08:00
|
|
|
ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TII, TRI,VRM);
|
2007-08-14 07:45:17 +08:00
|
|
|
} else {
|
2008-02-22 17:24:50 +08:00
|
|
|
TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg,
|
2007-08-14 07:45:17 +08:00
|
|
|
NewOp.StackSlotOrReMat, AliasRC);
|
2008-02-27 11:04:06 +08:00
|
|
|
MachineInstr *LoadMI = prior(MII);
|
|
|
|
VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI);
|
2007-08-14 17:11:18 +08:00
|
|
|
// Any stores to this stack slot are not dead anymore.
|
|
|
|
MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
|
2007-08-14 07:45:17 +08:00
|
|
|
++NumLoads;
|
|
|
|
}
|
2006-02-25 10:17:31 +08:00
|
|
|
Spills.ClobberPhysReg(NewPhysReg);
|
|
|
|
Spills.ClobberPhysReg(NewOp.PhysRegReused);
|
2006-02-25 09:51:33 +08:00
|
|
|
|
2006-05-05 01:52:23 +08:00
|
|
|
MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
|
2006-02-25 09:51:33 +08:00
|
|
|
|
2007-08-14 07:45:17 +08:00
|
|
|
Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
|
2007-07-12 03:17:18 +08:00
|
|
|
--MII;
|
|
|
|
UpdateKills(*MII, RegKills, KillOps);
|
|
|
|
DOUT << '\t' << *MII;
|
2006-02-25 09:51:33 +08:00
|
|
|
|
2006-11-17 10:09:07 +08:00
|
|
|
DOUT << "Reuse undone!\n";
|
2006-02-25 09:51:33 +08:00
|
|
|
--NumReused;
|
2006-02-25 10:17:31 +08:00
|
|
|
|
|
|
|
// Finally, PhysReg is now available, go ahead and use it.
|
2006-02-25 09:51:33 +08:00
|
|
|
return PhysReg;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return PhysReg;
|
|
|
|
}
|
2007-01-20 06:40:14 +08:00
|
|
|
|
|
|
|
/// GetRegForReload - Helper for the above GetRegForReload(). Add a
|
|
|
|
/// 'Rejected' set to remember which registers have been considered and
|
|
|
|
/// rejected for the reload. This avoids infinite looping in case like
|
|
|
|
/// this:
|
|
|
|
/// t1 := op t2, t3
|
|
|
|
/// t2 <- assigned r0 for use by the reload but ended up reuse r1
|
|
|
|
/// t3 <- assigned r1 for use by the reload but ended up reuse r0
|
|
|
|
/// t1 <- desires r1
|
|
|
|
/// sees r1 is taken by t2, tries t2's reload register r0
|
|
|
|
/// sees r0 is taken by t3, tries t3's reload register r1
|
|
|
|
/// sees r1 is taken by t2, tries t2's reload register r0 ...
|
|
|
|
unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
|
|
|
|
AvailableSpills &Spills,
|
2007-08-14 17:11:18 +08:00
|
|
|
std::vector<MachineInstr*> &MaybeDeadStores,
|
2007-07-12 03:17:18 +08:00
|
|
|
BitVector &RegKills,
|
2007-08-14 07:45:17 +08:00
|
|
|
std::vector<MachineOperand*> &KillOps,
|
|
|
|
VirtRegMap &VRM) {
|
2007-01-23 08:59:48 +08:00
|
|
|
SmallSet<unsigned, 8> Rejected;
|
2007-07-12 03:17:18 +08:00
|
|
|
return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
|
2007-08-14 07:45:17 +08:00
|
|
|
RegKills, KillOps, VRM);
|
2007-01-20 06:40:14 +08:00
|
|
|
}
|
2006-02-25 09:51:33 +08:00
|
|
|
};
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
}
|
|
|
|
|
2007-10-20 05:23:22 +08:00
|
|
|
/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding
|
|
|
|
/// instruction. e.g.
|
|
|
|
/// xorl %edi, %eax
|
|
|
|
/// movl %eax, -32(%ebp)
|
|
|
|
/// movl -36(%ebp), %eax
|
2008-02-26 18:51:52 +08:00
|
|
|
/// orl %eax, -32(%ebp)
|
2007-10-20 05:23:22 +08:00
|
|
|
/// ==>
|
|
|
|
/// xorl %edi, %eax
|
|
|
|
/// orl -36(%ebp), %eax
|
|
|
|
/// mov %eax, -32(%ebp)
|
|
|
|
/// This enables unfolding optimization for a subsequent instruction which will
|
|
|
|
/// also eliminate the newly introduced store instruction.
|
|
|
|
bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MII,
|
|
|
|
std::vector<MachineInstr*> &MaybeDeadStores,
|
|
|
|
AvailableSpills &Spills,
|
|
|
|
BitVector &RegKills,
|
|
|
|
std::vector<MachineOperand*> &KillOps,
|
|
|
|
VirtRegMap &VRM) {
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
MachineInstr &MI = *MII;
|
|
|
|
unsigned UnfoldedOpc = 0;
|
|
|
|
unsigned UnfoldPR = 0;
|
|
|
|
unsigned UnfoldVR = 0;
|
|
|
|
int FoldedSS = VirtRegMap::NO_STACK_SLOT;
|
|
|
|
VirtRegMap::MI2VirtMapTy::const_iterator I, End;
|
2008-03-15 04:44:01 +08:00
|
|
|
for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
|
2007-10-20 05:23:22 +08:00
|
|
|
// Only transform a MI that folds a single register.
|
|
|
|
if (UnfoldedOpc)
|
|
|
|
return false;
|
|
|
|
UnfoldVR = I->second.first;
|
|
|
|
VirtRegMap::ModRef MR = I->second.second;
|
2008-03-15 04:44:01 +08:00
|
|
|
// MI2VirtMap be can updated which invalidate the iterator.
|
|
|
|
// Increment the iterator first.
|
|
|
|
++I;
|
2007-10-20 05:23:22 +08:00
|
|
|
if (VRM.isAssignedReg(UnfoldVR))
|
|
|
|
continue;
|
|
|
|
// If this reference is not a use, any previous store is now dead.
|
|
|
|
// Otherwise, the store to this stack slot is not dead anymore.
|
|
|
|
FoldedSS = VRM.getStackSlot(UnfoldVR);
|
|
|
|
MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
|
|
|
|
if (DeadStore && (MR & VirtRegMap::isModRef)) {
|
|
|
|
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
|
2008-03-05 08:59:57 +08:00
|
|
|
if (!PhysReg || !DeadStore->readsRegister(PhysReg))
|
2007-10-20 05:23:22 +08:00
|
|
|
continue;
|
|
|
|
UnfoldPR = PhysReg;
|
2008-01-07 09:35:56 +08:00
|
|
|
UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
|
2007-10-20 05:23:22 +08:00
|
|
|
false, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!UnfoldedOpc)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI.getOperand(i);
|
|
|
|
if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse())
|
|
|
|
continue;
|
|
|
|
unsigned VirtReg = MO.getReg();
|
2008-02-11 02:45:23 +08:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
|
2007-10-20 05:23:22 +08:00
|
|
|
continue;
|
|
|
|
if (VRM.isAssignedReg(VirtReg)) {
|
|
|
|
unsigned PhysReg = VRM.getPhys(VirtReg);
|
2008-02-11 02:45:23 +08:00
|
|
|
if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
|
2007-10-20 05:23:22 +08:00
|
|
|
return false;
|
|
|
|
} else if (VRM.isReMaterialized(VirtReg))
|
|
|
|
continue;
|
|
|
|
int SS = VRM.getStackSlot(VirtReg);
|
|
|
|
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
|
|
|
|
if (PhysReg) {
|
2008-02-11 02:45:23 +08:00
|
|
|
if (TRI->regsOverlap(PhysReg, UnfoldPR))
|
2007-10-20 05:23:22 +08:00
|
|
|
return false;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
PhysReg = VRM.getPhys(VirtReg);
|
2008-02-11 02:45:23 +08:00
|
|
|
if (!TRI->regsOverlap(PhysReg, UnfoldPR))
|
2007-10-20 05:23:22 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Ok, we'll need to reload the value into a register which makes
|
|
|
|
// it impossible to perform the store unfolding optimization later.
|
|
|
|
// Let's see if it is possible to fold the load if the store is
|
|
|
|
// unfolded. This allows us to perform the store unfolding
|
|
|
|
// optimization.
|
|
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
2008-01-07 09:35:56 +08:00
|
|
|
if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
|
2007-10-20 05:23:22 +08:00
|
|
|
assert(NewMIs.size() == 1);
|
|
|
|
MachineInstr *NewMI = NewMIs.back();
|
|
|
|
NewMIs.clear();
|
2008-03-05 08:59:57 +08:00
|
|
|
int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false);
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
assert(Idx != -1);
|
2007-12-02 16:30:39 +08:00
|
|
|
SmallVector<unsigned, 2> Ops;
|
|
|
|
Ops.push_back(Idx);
|
2008-02-09 06:05:27 +08:00
|
|
|
MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
|
2007-10-20 05:23:22 +08:00
|
|
|
if (FoldedMI) {
|
2008-02-28 03:57:11 +08:00
|
|
|
VRM.addSpillSlotUse(SS, FoldedMI);
|
2007-10-22 11:01:44 +08:00
|
|
|
if (!VRM.hasPhys(UnfoldVR))
|
2007-10-20 05:23:22 +08:00
|
|
|
VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
|
|
|
|
VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
|
|
|
|
MII = MBB.insert(MII, FoldedMI);
|
2008-05-20 16:13:21 +08:00
|
|
|
InvalidateKills(MI, RegKills, KillOps);
|
2007-11-28 09:28:46 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(&MI);
|
2007-10-20 05:23:22 +08:00
|
|
|
MBB.erase(&MI);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
delete NewMI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
|
2007-11-03 01:35:08 +08:00
|
|
|
/// findSuperReg - Find the SubReg's super-register of given register class
|
|
|
|
/// where its SubIdx sub-register is SubReg.
|
|
|
|
static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
|
2008-02-11 02:45:23 +08:00
|
|
|
unsigned SubIdx, const TargetRegisterInfo *TRI) {
|
2007-11-03 01:35:08 +08:00
|
|
|
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
|
|
|
|
I != E; ++I) {
|
|
|
|
unsigned Reg = *I;
|
2008-02-11 02:45:23 +08:00
|
|
|
if (TRI->getSubReg(Reg, SubIdx) == SubReg)
|
2007-11-03 01:35:08 +08:00
|
|
|
return Reg;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
|
|
|
|
/// the last store to the same slot is now dead. If so, remove the last store.
|
|
|
|
void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MII,
|
|
|
|
int Idx, unsigned PhysReg, int StackSlot,
|
|
|
|
const TargetRegisterClass *RC,
|
2007-12-05 03:19:45 +08:00
|
|
|
bool isAvailable, MachineInstr *&LastStore,
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
AvailableSpills &Spills,
|
|
|
|
SmallSet<MachineInstr*, 4> &ReMatDefs,
|
|
|
|
BitVector &RegKills,
|
|
|
|
std::vector<MachineOperand*> &KillOps,
|
2007-12-04 05:31:55 +08:00
|
|
|
VirtRegMap &VRM) {
|
2008-01-02 05:11:32 +08:00
|
|
|
TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
|
2008-02-27 11:04:06 +08:00
|
|
|
MachineInstr *StoreMI = next(MII);
|
|
|
|
VRM.addSpillSlotUse(StackSlot, StoreMI);
|
|
|
|
DOUT << "Store:\t" << *StoreMI;
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
|
|
|
|
// If there is a dead store to this stack slot, nuke it now.
|
|
|
|
if (LastStore) {
|
|
|
|
DOUT << "Removed dead store:\t" << *LastStore;
|
|
|
|
++NumDSE;
|
|
|
|
SmallVector<unsigned, 2> KillRegs;
|
|
|
|
InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
|
|
|
|
MachineBasicBlock::iterator PrevMII = LastStore;
|
|
|
|
bool CheckDef = PrevMII != MBB.begin();
|
|
|
|
if (CheckDef)
|
|
|
|
--PrevMII;
|
2007-11-28 09:28:46 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(LastStore);
|
2008-02-27 11:04:06 +08:00
|
|
|
MBB.erase(LastStore);
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
if (CheckDef) {
|
|
|
|
// Look at defs of killed registers on the store. Mark the defs
|
|
|
|
// as dead since the store has been deleted and they aren't
|
|
|
|
// being reused.
|
|
|
|
for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
|
|
|
|
bool HasOtherDef = false;
|
|
|
|
if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) {
|
|
|
|
MachineInstr *DeadDef = PrevMII;
|
|
|
|
if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
|
|
|
|
// FIXME: This assumes a remat def does not have side
|
|
|
|
// effects.
|
2007-11-28 09:28:46 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(DeadDef);
|
2008-02-27 11:04:06 +08:00
|
|
|
MBB.erase(DeadDef);
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
++NumDRM;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-12-04 05:31:55 +08:00
|
|
|
LastStore = next(MII);
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
|
|
|
|
// If the stack slot value was previously available in some other
|
|
|
|
// register, change it now. Otherwise, make the register available,
|
|
|
|
// in PhysReg.
|
|
|
|
Spills.ModifyStackSlotOrReMat(StackSlot);
|
|
|
|
Spills.ClobberPhysReg(PhysReg);
|
2007-12-05 03:19:45 +08:00
|
|
|
Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable);
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
++NumStores;
|
|
|
|
}
|
|
|
|
|
2008-05-20 16:13:21 +08:00
|
|
|
/// TransferDeadness - A identity copy definition is dead and it's being
|
|
|
|
/// removed. Find the last def or use and mark it as dead / kill.
|
|
|
|
void LocalSpiller::TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
|
|
|
|
unsigned Reg, BitVector &RegKills,
|
|
|
|
std::vector<MachineOperand*> &KillOps) {
|
|
|
|
int LastUDDist = -1;
|
|
|
|
MachineInstr *LastUDMI = NULL;
|
|
|
|
for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg),
|
|
|
|
RE = RegInfo->reg_end(); RI != RE; ++RI) {
|
|
|
|
MachineInstr *UDMI = &*RI;
|
|
|
|
if (UDMI->getParent() != MBB)
|
|
|
|
continue;
|
|
|
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
|
|
|
|
if (DI == DistanceMap.end() || DI->second > CurDist)
|
|
|
|
continue;
|
|
|
|
if ((int)DI->second < LastUDDist)
|
|
|
|
continue;
|
|
|
|
LastUDDist = DI->second;
|
|
|
|
LastUDMI = UDMI;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (LastUDMI) {
|
|
|
|
const TargetInstrDesc &TID = LastUDMI->getDesc();
|
|
|
|
MachineOperand *LastUD = NULL;
|
|
|
|
for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = LastUDMI->getOperand(i);
|
|
|
|
if (!MO.isRegister() || MO.getReg() != Reg)
|
|
|
|
continue;
|
|
|
|
if (!LastUD || (LastUD->isUse() && MO.isDef()))
|
|
|
|
LastUD = &MO;
|
|
|
|
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1)
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (LastUD->isDef())
|
|
|
|
LastUD->setIsDead();
|
|
|
|
else {
|
|
|
|
LastUD->setIsKill();
|
|
|
|
RegKills.set(Reg);
|
|
|
|
KillOps[Reg] = LastUD;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
/// rewriteMBB - Keep track of which spills are available even after the
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
/// register allocator is done with them. If possible, avid reloading vregs.
|
2007-08-14 07:45:17 +08:00
|
|
|
void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
2006-11-17 10:09:07 +08:00
|
|
|
DOUT << MBB.getBasicBlock()->getName() << ":\n";
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
|
2007-08-14 17:11:18 +08:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2007-12-31 14:32:00 +08:00
|
|
|
|
2006-02-04 07:13:58 +08:00
|
|
|
// Spills - Keep track of which spilled values are available in physregs so
|
|
|
|
// that we can choose to reuse the physregs instead of emitting reloads.
|
2008-02-11 02:45:23 +08:00
|
|
|
AvailableSpills Spills(TRI, TII);
|
2006-02-04 07:13:58 +08:00
|
|
|
|
2004-10-02 03:47:12 +08:00
|
|
|
// MaybeDeadStores - When we need to write a value back into a stack slot,
|
|
|
|
// keep track of the inserted store. If the stack slot value is never read
|
|
|
|
// (because the value was used from some available register, for example), and
|
|
|
|
// subsequently stored to, the original store is dead. This map keeps track
|
|
|
|
// of inserted stores that are not used. If we see a subsequent store to the
|
|
|
|
// same stack slot, the original store is deleted.
|
2007-08-14 17:11:18 +08:00
|
|
|
std::vector<MachineInstr*> MaybeDeadStores;
|
|
|
|
MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
|
2004-10-02 03:47:12 +08:00
|
|
|
|
2007-08-15 07:25:37 +08:00
|
|
|
// ReMatDefs - These are rematerializable def MIs which are not deleted.
|
|
|
|
SmallSet<MachineInstr*, 4> ReMatDefs;
|
|
|
|
|
2007-07-11 13:28:39 +08:00
|
|
|
// Keep track of kill information.
|
2008-02-11 02:45:23 +08:00
|
|
|
BitVector RegKills(TRI->getNumRegs());
|
2007-07-11 13:28:39 +08:00
|
|
|
std::vector<MachineOperand*> KillOps;
|
2008-02-11 02:45:23 +08:00
|
|
|
KillOps.resize(TRI->getNumRegs(), NULL);
|
2007-07-11 13:28:39 +08:00
|
|
|
|
2008-05-20 16:13:21 +08:00
|
|
|
unsigned Dist = 0;
|
|
|
|
DistanceMap.clear();
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
|
|
|
|
MII != E; ) {
|
|
|
|
MachineBasicBlock::iterator NextMII = MII; ++NextMII;
|
2007-07-11 13:28:39 +08:00
|
|
|
|
2007-10-20 05:23:22 +08:00
|
|
|
VirtRegMap::MI2VirtMapTy::const_iterator I, End;
|
2007-07-11 13:28:39 +08:00
|
|
|
bool Erased = false;
|
|
|
|
bool BackTracked = false;
|
2007-10-20 05:23:22 +08:00
|
|
|
if (PrepForUnfoldOpti(MBB, MII,
|
|
|
|
MaybeDeadStores, Spills, RegKills, KillOps, VRM))
|
|
|
|
NextMII = next(MII);
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
|
2007-10-20 05:23:22 +08:00
|
|
|
MachineInstr &MI = *MII;
|
2008-01-07 15:27:27 +08:00
|
|
|
const TargetInstrDesc &TID = MI.getDesc();
|
2006-11-04 08:21:55 +08:00
|
|
|
|
2008-03-11 15:19:34 +08:00
|
|
|
if (VRM.hasEmergencySpills(&MI)) {
|
|
|
|
// Spill physical register(s) in the rare case the allocator has run out
|
|
|
|
// of registers to allocate.
|
|
|
|
SmallSet<int, 4> UsedSS;
|
|
|
|
std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI);
|
|
|
|
for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
|
|
|
|
unsigned PhysReg = EmSpills[i];
|
|
|
|
const TargetRegisterClass *RC =
|
|
|
|
TRI->getPhysicalRegisterRegClass(PhysReg);
|
|
|
|
assert(RC && "Unable to determine register class!");
|
|
|
|
int SS = VRM.getEmergencySpillSlot(RC);
|
|
|
|
if (UsedSS.count(SS))
|
|
|
|
assert(0 && "Need to spill more than one physical registers!");
|
|
|
|
UsedSS.insert(SS);
|
|
|
|
TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
|
|
|
|
MachineInstr *StoreMI = prior(MII);
|
|
|
|
VRM.addSpillSlotUse(SS, StoreMI);
|
|
|
|
TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC);
|
|
|
|
MachineInstr *LoadMI = next(MII);
|
|
|
|
VRM.addSpillSlotUse(SS, LoadMI);
|
2008-03-12 05:34:46 +08:00
|
|
|
++NumPSpills;
|
2008-03-11 15:19:34 +08:00
|
|
|
}
|
2008-03-12 08:14:07 +08:00
|
|
|
NextMII = next(MII);
|
2008-03-11 15:19:34 +08:00
|
|
|
}
|
|
|
|
|
2007-11-29 09:06:25 +08:00
|
|
|
// Insert restores here if asked to.
|
|
|
|
if (VRM.isRestorePt(&MI)) {
|
|
|
|
std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
|
|
|
|
for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
|
2008-02-22 17:24:50 +08:00
|
|
|
unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order.
|
2007-11-29 09:06:25 +08:00
|
|
|
if (!VRM.getPreSplitReg(VirtReg))
|
|
|
|
continue; // Split interval spilled again.
|
|
|
|
unsigned Phys = VRM.getPhys(VirtReg);
|
2007-12-31 12:13:23 +08:00
|
|
|
RegInfo->setPhysRegUsed(Phys);
|
2007-11-29 09:06:25 +08:00
|
|
|
if (VRM.isReMaterialized(VirtReg)) {
|
2008-04-01 04:40:39 +08:00
|
|
|
ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM);
|
2007-11-29 09:06:25 +08:00
|
|
|
} else {
|
2007-12-31 12:13:23 +08:00
|
|
|
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
2008-02-27 11:04:06 +08:00
|
|
|
int SS = VRM.getStackSlot(VirtReg);
|
|
|
|
TII->loadRegFromStackSlot(MBB, &MI, Phys, SS, RC);
|
|
|
|
MachineInstr *LoadMI = prior(MII);
|
|
|
|
VRM.addSpillSlotUse(SS, LoadMI);
|
2007-11-29 09:06:25 +08:00
|
|
|
++NumLoads;
|
|
|
|
}
|
|
|
|
// This invalidates Phys.
|
|
|
|
Spills.ClobberPhysReg(Phys);
|
|
|
|
UpdateKills(*prior(MII), RegKills, KillOps);
|
|
|
|
DOUT << '\t' << *prior(MII);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
// Insert spills here if asked to.
|
2007-11-28 09:28:46 +08:00
|
|
|
if (VRM.isSpillPt(&MI)) {
|
2007-12-05 16:16:32 +08:00
|
|
|
std::vector<std::pair<unsigned,bool> > &SpillRegs =
|
|
|
|
VRM.getSpillPtSpills(&MI);
|
2007-11-28 09:28:46 +08:00
|
|
|
for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
|
2007-12-05 16:16:32 +08:00
|
|
|
unsigned VirtReg = SpillRegs[i].first;
|
|
|
|
bool isKill = SpillRegs[i].second;
|
2007-11-28 09:28:46 +08:00
|
|
|
if (!VRM.getPreSplitReg(VirtReg))
|
|
|
|
continue; // Split interval spilled again.
|
2007-12-31 12:13:23 +08:00
|
|
|
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
|
2007-11-28 09:28:46 +08:00
|
|
|
unsigned Phys = VRM.getPhys(VirtReg);
|
|
|
|
int StackSlot = VRM.getStackSlot(VirtReg);
|
2008-01-02 05:11:32 +08:00
|
|
|
TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
|
2007-12-05 11:14:33 +08:00
|
|
|
MachineInstr *StoreMI = next(MII);
|
2008-02-27 11:04:06 +08:00
|
|
|
VRM.addSpillSlotUse(StackSlot, StoreMI);
|
2008-03-12 08:02:46 +08:00
|
|
|
DOUT << "Store:\t" << *StoreMI;
|
2007-12-05 11:14:33 +08:00
|
|
|
VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
|
2007-11-28 09:28:46 +08:00
|
|
|
}
|
2007-12-04 05:31:55 +08:00
|
|
|
NextMII = next(MII);
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// ReusedOperands - Keep track of operand reuse in case we need to undo
|
|
|
|
/// reuse.
|
2008-02-11 02:45:23 +08:00
|
|
|
ReuseInfo ReusedOperands(MI, TRI);
|
2008-02-23 03:22:06 +08:00
|
|
|
SmallVector<unsigned, 4> VirtUseOps;
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI.getOperand(i);
|
2005-09-10 04:29:51 +08:00
|
|
|
if (!MO.isRegister() || MO.getReg() == 0)
|
|
|
|
continue; // Ignore non-register operands.
|
|
|
|
|
2007-10-12 16:50:34 +08:00
|
|
|
unsigned VirtReg = MO.getReg();
|
2008-02-11 02:45:23 +08:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
|
2005-09-10 04:29:51 +08:00
|
|
|
// Ignore physregs for spilling, but remember that it is used by this
|
|
|
|
// function.
|
2007-12-31 12:13:23 +08:00
|
|
|
RegInfo->setPhysRegUsed(VirtReg);
|
2005-09-10 04:29:51 +08:00
|
|
|
continue;
|
|
|
|
}
|
2008-02-23 03:22:06 +08:00
|
|
|
|
|
|
|
// We want to process implicit virtual register uses first.
|
|
|
|
if (MO.isImplicit())
|
2008-04-12 01:53:36 +08:00
|
|
|
// If the virtual register is implicitly defined, emit a implicit_def
|
|
|
|
// before so scavenger knows it's "defined".
|
2008-02-23 03:22:06 +08:00
|
|
|
VirtUseOps.insert(VirtUseOps.begin(), i);
|
|
|
|
else
|
|
|
|
VirtUseOps.push_back(i);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Process all of the spilled uses and all non spilled reg references.
|
|
|
|
for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
|
|
|
|
unsigned i = VirtUseOps[j];
|
|
|
|
MachineOperand &MO = MI.getOperand(i);
|
|
|
|
unsigned VirtReg = MO.getReg();
|
2008-02-11 02:45:23 +08:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
|
2008-02-23 03:22:06 +08:00
|
|
|
"Not a virtual register?");
|
2007-12-03 17:58:48 +08:00
|
|
|
|
2007-11-14 15:59:08 +08:00
|
|
|
unsigned SubIdx = MO.getSubReg();
|
2007-08-14 07:45:17 +08:00
|
|
|
if (VRM.isAssignedReg(VirtReg)) {
|
2005-09-10 04:29:51 +08:00
|
|
|
// This virtual register was assigned a physreg!
|
|
|
|
unsigned Phys = VRM.getPhys(VirtReg);
|
2007-12-31 12:13:23 +08:00
|
|
|
RegInfo->setPhysRegUsed(Phys);
|
2006-11-04 08:21:55 +08:00
|
|
|
if (MO.isDef())
|
|
|
|
ReusedOperands.markClobbered(Phys);
|
2008-02-11 02:45:23 +08:00
|
|
|
unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
|
2007-10-12 16:50:34 +08:00
|
|
|
MI.getOperand(i).setReg(RReg);
|
2008-04-12 01:53:36 +08:00
|
|
|
if (VRM.isImplicitlyDefined(VirtReg))
|
|
|
|
BuildMI(MBB, MI, TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
|
2005-09-10 04:29:51 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// This virtual register is now known to be a spilled value.
|
|
|
|
if (!MO.isUse())
|
|
|
|
continue; // Handle defs in the loop below (handle use&def here though)
|
|
|
|
|
2007-08-14 07:45:17 +08:00
|
|
|
bool DoReMat = VRM.isReMaterialized(VirtReg);
|
|
|
|
int SSorRMId = DoReMat
|
|
|
|
? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
|
2007-08-14 13:42:54 +08:00
|
|
|
int ReuseSlot = SSorRMId;
|
2005-09-10 04:29:51 +08:00
|
|
|
|
|
|
|
// Check to see if this stack slot is available.
|
2007-08-14 13:42:54 +08:00
|
|
|
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
|
2007-10-12 16:50:34 +08:00
|
|
|
|
|
|
|
// If this is a sub-register use, make sure the reuse register is in the
|
|
|
|
// right register class. For example, for x86 not all of the 32-bit
|
|
|
|
// registers have accessible sub-registers.
|
|
|
|
// Similarly so for EXTRACT_SUBREG. Consider this:
|
|
|
|
// EDI = op
|
|
|
|
// MOV32_mr fi#1, EDI
|
|
|
|
// ...
|
|
|
|
// = EXTRACT_SUBREG fi#1
|
|
|
|
// fi#1 is available in EDI, but it cannot be reused because it's not in
|
|
|
|
// the right register file.
|
|
|
|
if (PhysReg &&
|
2007-11-14 15:59:08 +08:00
|
|
|
(SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
|
2007-12-31 12:13:23 +08:00
|
|
|
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
2007-10-12 16:50:34 +08:00
|
|
|
if (!RC->contains(PhysReg))
|
|
|
|
PhysReg = 0;
|
|
|
|
}
|
|
|
|
|
2007-08-14 13:42:54 +08:00
|
|
|
if (PhysReg) {
|
2006-09-05 10:12:02 +08:00
|
|
|
// This spilled operand might be part of a two-address operand. If this
|
|
|
|
// is the case, then changing it will necessarily require changing the
|
|
|
|
// def part of the instruction as well. However, in some cases, we
|
|
|
|
// aren't allowed to modify the reused register. If none of these cases
|
|
|
|
// apply, reuse it.
|
|
|
|
bool CanReuse = true;
|
2008-01-07 15:27:27 +08:00
|
|
|
int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
|
2006-11-02 07:06:55 +08:00
|
|
|
if (ti != -1 &&
|
2007-09-15 04:33:02 +08:00
|
|
|
MI.getOperand(ti).isRegister() &&
|
2006-11-02 07:06:55 +08:00
|
|
|
MI.getOperand(ti).getReg() == VirtReg) {
|
2006-09-05 10:12:02 +08:00
|
|
|
// Okay, we have a two address operand. We can reuse this physreg as
|
2007-01-20 06:40:14 +08:00
|
|
|
// long as we are allowed to clobber the value and there isn't an
|
|
|
|
// earlier def that has already clobbered the physreg.
|
2007-08-14 13:42:54 +08:00
|
|
|
CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
|
2006-11-04 08:21:55 +08:00
|
|
|
!ReusedOperands.isClobbered(PhysReg);
|
2006-09-05 10:12:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (CanReuse) {
|
When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 09:46:50 +08:00
|
|
|
// If this stack slot value is already available, reuse it!
|
2007-08-14 13:42:54 +08:00
|
|
|
if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
|
|
|
|
DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
|
2007-03-20 16:13:50 +08:00
|
|
|
else
|
2007-08-14 13:42:54 +08:00
|
|
|
DOUT << "Reusing SS#" << ReuseSlot;
|
2007-03-20 16:13:50 +08:00
|
|
|
DOUT << " from physreg "
|
2008-02-27 05:47:57 +08:00
|
|
|
<< TRI->getName(PhysReg) << " for vreg"
|
2006-11-17 10:09:07 +08:00
|
|
|
<< VirtReg <<" instead of reloading into physreg "
|
2008-02-27 05:47:57 +08:00
|
|
|
<< TRI->getName(VRM.getPhys(VirtReg)) << "\n";
|
2008-02-11 02:45:23 +08:00
|
|
|
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
2007-10-12 16:50:34 +08:00
|
|
|
MI.getOperand(i).setReg(RReg);
|
When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 09:46:50 +08:00
|
|
|
|
|
|
|
// The only technical detail we have is that we don't know that
|
|
|
|
// PhysReg won't be clobbered by a reloaded stack slot that occurs
|
|
|
|
// later in the instruction. In particular, consider 'op V1, V2'.
|
|
|
|
// If V1 is available in physreg R0, we would choose to reuse it
|
|
|
|
// here, instead of reloading it into the register the allocator
|
|
|
|
// indicated (say R1). However, V2 might have to be reloaded
|
|
|
|
// later, and it might indicate that it needs to live in R0. When
|
|
|
|
// this occurs, we need to have information available that
|
|
|
|
// indicates it is safe to use R1 for the reload instead of R0.
|
|
|
|
//
|
|
|
|
// To further complicate matters, we might conflict with an alias,
|
|
|
|
// or R0 and R1 might not be compatible with each other. In this
|
|
|
|
// case, we actually insert a reload for V1 in R1, ensuring that
|
|
|
|
// we can get at R0 or its alias.
|
2007-08-14 13:42:54 +08:00
|
|
|
ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
|
When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 09:46:50 +08:00
|
|
|
VRM.getPhys(VirtReg), VirtReg);
|
2006-11-04 08:21:55 +08:00
|
|
|
if (ti != -1)
|
|
|
|
// Only mark it clobbered if this is a use&def operand.
|
|
|
|
ReusedOperands.markClobbered(PhysReg);
|
When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 09:46:50 +08:00
|
|
|
++NumReused;
|
2007-08-14 17:11:18 +08:00
|
|
|
|
|
|
|
if (MI.getOperand(i).isKill() &&
|
|
|
|
ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
|
|
|
|
// This was the last use and the spilled value is still available
|
|
|
|
// for reuse. That means the spill was unnecessary!
|
|
|
|
MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
|
|
|
|
if (DeadStore) {
|
|
|
|
DOUT << "Removed dead store:\t" << *DeadStore;
|
|
|
|
InvalidateKills(*DeadStore, RegKills, KillOps);
|
2007-11-28 09:28:46 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(DeadStore);
|
2007-10-20 05:23:22 +08:00
|
|
|
MBB.erase(DeadStore);
|
2007-08-14 17:11:18 +08:00
|
|
|
MaybeDeadStores[ReuseSlot] = NULL;
|
|
|
|
++NumDSE;
|
|
|
|
}
|
|
|
|
}
|
When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 09:46:50 +08:00
|
|
|
continue;
|
2007-10-12 16:50:34 +08:00
|
|
|
} // CanReuse
|
When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 09:46:50 +08:00
|
|
|
|
|
|
|
// Otherwise we have a situation where we have a two-address instruction
|
|
|
|
// whose mod/ref operand needs to be reloaded. This reload is already
|
|
|
|
// available in some register "PhysReg", but if we used PhysReg as the
|
|
|
|
// operand to our 2-addr instruction, the instruction would modify
|
|
|
|
// PhysReg. This isn't cool if something later uses PhysReg and expects
|
|
|
|
// to get its initial value.
|
2005-09-10 04:29:51 +08:00
|
|
|
//
|
When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 09:46:50 +08:00
|
|
|
// To avoid this problem, and to avoid doing a load right after a store,
|
|
|
|
// we emit a copy from PhysReg into the designated register for this
|
|
|
|
// operand.
|
|
|
|
unsigned DesignatedReg = VRM.getPhys(VirtReg);
|
|
|
|
assert(DesignatedReg && "Must map virtreg to physreg!");
|
|
|
|
|
|
|
|
// Note that, if we reused a register for a previous operand, the
|
|
|
|
// register we want to reload into might not actually be
|
|
|
|
// available. If this occurs, use the register indicated by the
|
|
|
|
// reuser.
|
|
|
|
if (ReusedOperands.hasReuses())
|
|
|
|
DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
|
2007-08-14 07:45:17 +08:00
|
|
|
Spills, MaybeDeadStores, RegKills, KillOps, VRM);
|
When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 09:46:50 +08:00
|
|
|
|
2006-04-28 12:43:18 +08:00
|
|
|
// If the mapped designated register is actually the physreg we have
|
|
|
|
// incoming, we don't need to inserted a dead copy.
|
|
|
|
if (DesignatedReg == PhysReg) {
|
|
|
|
// If this stack slot value is already available, reuse it!
|
2007-08-14 13:42:54 +08:00
|
|
|
if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
|
|
|
|
DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
|
2007-03-20 16:13:50 +08:00
|
|
|
else
|
2007-08-14 13:42:54 +08:00
|
|
|
DOUT << "Reusing SS#" << ReuseSlot;
|
2008-02-27 05:47:57 +08:00
|
|
|
DOUT << " from physreg " << TRI->getName(PhysReg)
|
2008-02-27 14:33:05 +08:00
|
|
|
<< " for vreg" << VirtReg
|
2006-11-17 10:09:07 +08:00
|
|
|
<< " instead of reloading into same physreg.\n";
|
2008-02-11 02:45:23 +08:00
|
|
|
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
2007-10-12 16:50:34 +08:00
|
|
|
MI.getOperand(i).setReg(RReg);
|
2007-11-03 01:35:08 +08:00
|
|
|
ReusedOperands.markClobbered(RReg);
|
2006-04-28 12:43:18 +08:00
|
|
|
++NumReused;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2007-12-31 12:13:23 +08:00
|
|
|
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
|
|
|
RegInfo->setPhysRegUsed(DesignatedReg);
|
2006-11-04 08:21:55 +08:00
|
|
|
ReusedOperands.markClobbered(DesignatedReg);
|
2007-12-31 14:32:00 +08:00
|
|
|
TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
|
2007-02-25 17:51:27 +08:00
|
|
|
|
2007-03-02 16:52:00 +08:00
|
|
|
MachineInstr *CopyMI = prior(MII);
|
2007-07-11 13:28:39 +08:00
|
|
|
UpdateKills(*CopyMI, RegKills, KillOps);
|
2007-02-25 17:51:27 +08:00
|
|
|
|
When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 09:46:50 +08:00
|
|
|
// This invalidates DesignatedReg.
|
|
|
|
Spills.ClobberPhysReg(DesignatedReg);
|
|
|
|
|
2007-08-14 13:42:54 +08:00
|
|
|
Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
|
2007-10-12 16:50:34 +08:00
|
|
|
unsigned RReg =
|
2008-02-11 02:45:23 +08:00
|
|
|
SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
|
2007-10-12 16:50:34 +08:00
|
|
|
MI.getOperand(i).setReg(RReg);
|
2006-11-17 10:09:07 +08:00
|
|
|
DOUT << '\t' << *prior(MII);
|
2005-09-10 04:29:51 +08:00
|
|
|
++NumReused;
|
|
|
|
continue;
|
2007-10-20 05:23:22 +08:00
|
|
|
} // if (PhysReg)
|
2005-09-10 04:29:51 +08:00
|
|
|
|
|
|
|
// Otherwise, reload it and remember that we have it.
|
|
|
|
PhysReg = VRM.getPhys(VirtReg);
|
2006-01-04 14:47:48 +08:00
|
|
|
assert(PhysReg && "Must map virtreg to physreg!");
|
2005-09-10 04:29:51 +08:00
|
|
|
|
|
|
|
// Note that, if we reused a register for a previous operand, the
|
|
|
|
// register we want to reload into might not actually be
|
|
|
|
// available. If this occurs, use the register indicated by the
|
|
|
|
// reuser.
|
2006-02-25 09:51:33 +08:00
|
|
|
if (ReusedOperands.hasReuses())
|
|
|
|
PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
|
2007-08-14 07:45:17 +08:00
|
|
|
Spills, MaybeDeadStores, RegKills, KillOps, VRM);
|
2006-02-25 09:51:33 +08:00
|
|
|
|
2007-12-31 12:13:23 +08:00
|
|
|
RegInfo->setPhysRegUsed(PhysReg);
|
2006-11-04 08:21:55 +08:00
|
|
|
ReusedOperands.markClobbered(PhysReg);
|
2007-08-14 07:45:17 +08:00
|
|
|
if (DoReMat) {
|
2008-04-01 04:40:39 +08:00
|
|
|
ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM);
|
2007-04-04 15:40:01 +08:00
|
|
|
} else {
|
2007-12-31 12:13:23 +08:00
|
|
|
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
2008-01-02 05:11:32 +08:00
|
|
|
TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
|
2008-02-27 11:04:06 +08:00
|
|
|
MachineInstr *LoadMI = prior(MII);
|
|
|
|
VRM.addSpillSlotUse(SSorRMId, LoadMI);
|
2007-04-04 15:40:01 +08:00
|
|
|
++NumLoads;
|
|
|
|
}
|
2005-09-10 04:29:51 +08:00
|
|
|
// This invalidates PhysReg.
|
2006-02-04 07:13:58 +08:00
|
|
|
Spills.ClobberPhysReg(PhysReg);
|
2005-09-10 04:29:51 +08:00
|
|
|
|
|
|
|
// Any stores to this stack slot are not dead anymore.
|
2007-08-14 07:45:17 +08:00
|
|
|
if (!DoReMat)
|
2007-08-14 17:11:18 +08:00
|
|
|
MaybeDeadStores[SSorRMId] = NULL;
|
2007-08-14 07:45:17 +08:00
|
|
|
Spills.addAvailable(SSorRMId, &MI, PhysReg);
|
2007-02-25 17:51:27 +08:00
|
|
|
// Assumes this is the last use. IsKill will be unset if reg is reused
|
|
|
|
// unless it's a two-address operand.
|
2008-01-07 15:27:27 +08:00
|
|
|
if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
|
2007-02-25 17:51:27 +08:00
|
|
|
MI.getOperand(i).setIsKill();
|
2008-02-11 02:45:23 +08:00
|
|
|
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
2007-10-12 16:50:34 +08:00
|
|
|
MI.getOperand(i).setReg(RReg);
|
2007-07-11 13:28:39 +08:00
|
|
|
UpdateKills(*prior(MII), RegKills, KillOps);
|
2006-11-17 10:09:07 +08:00
|
|
|
DOUT << '\t' << *prior(MII);
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
2004-02-24 16:58:30 +08:00
|
|
|
|
2006-11-17 10:09:07 +08:00
|
|
|
DOUT << '\t' << MI;
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
// If we have folded references to memory operands, make sure we clear all
|
|
|
|
// physical registers that may contain the value of the spilled virtual
|
|
|
|
// register
|
2007-10-20 05:23:22 +08:00
|
|
|
SmallSet<int, 2> FoldedSS;
|
2008-03-15 04:44:01 +08:00
|
|
|
for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
|
2004-10-02 07:15:36 +08:00
|
|
|
unsigned VirtReg = I->second.first;
|
|
|
|
VirtRegMap::ModRef MR = I->second.second;
|
2007-10-20 05:23:22 +08:00
|
|
|
DOUT << "Folded vreg: " << VirtReg << " MR: " << MR;
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
|
2008-03-15 04:44:01 +08:00
|
|
|
// MI2VirtMap be can updated which invalidate the iterator.
|
|
|
|
// Increment the iterator first.
|
|
|
|
++I;
|
Teach the local spiller to turn stack slot loads into register-register copies
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).
This patch came about when I noticed code like the following being generated:
store R17 -> [SS1]
...blah...
R4 = load [SS1]
This was causing an LSU reject on the G5. This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register. In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.
This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).
Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.
llvm-svn: 23388
2005-09-19 14:56:21 +08:00
|
|
|
int SS = VRM.getStackSlot(VirtReg);
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 08:40:40 +08:00
|
|
|
if (SS == VirtRegMap::NO_STACK_SLOT)
|
|
|
|
continue;
|
2007-08-16 04:20:34 +08:00
|
|
|
FoldedSS.insert(SS);
|
2006-11-17 10:09:07 +08:00
|
|
|
DOUT << " - StackSlot: " << SS << "\n";
|
Teach the local spiller to turn stack slot loads into register-register copies
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).
This patch came about when I noticed code like the following being generated:
store R17 -> [SS1]
...blah...
R4 = load [SS1]
This was causing an LSU reject on the G5. This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register. In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.
This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).
Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.
llvm-svn: 23388
2005-09-19 14:56:21 +08:00
|
|
|
|
|
|
|
// If this folded instruction is just a use, check to see if it's a
|
|
|
|
// straight load from the virt reg slot.
|
|
|
|
if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
|
|
|
|
int FrameIdx;
|
2007-10-12 16:50:34 +08:00
|
|
|
unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
|
|
|
|
if (DestReg && FrameIdx == SS) {
|
|
|
|
// If this spill slot is available, turn it into a copy (or nothing)
|
|
|
|
// instead of leaving it as a load!
|
|
|
|
if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
|
|
|
|
DOUT << "Promoted Load To Copy: " << MI;
|
|
|
|
if (DestReg != InReg) {
|
2007-12-31 12:13:23 +08:00
|
|
|
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
|
2007-12-31 14:32:00 +08:00
|
|
|
TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
|
2007-10-12 16:50:34 +08:00
|
|
|
// Revisit the copy so we make sure to notice the effects of the
|
|
|
|
// operation on the destreg (either needing to RA it if it's
|
|
|
|
// virtual or needing to clobber any values if it's physical).
|
|
|
|
NextMII = &MI;
|
|
|
|
--NextMII; // backtrack to the copy.
|
|
|
|
BackTracked = true;
|
2007-12-12 07:36:57 +08:00
|
|
|
} else {
|
2007-10-12 16:50:34 +08:00
|
|
|
DOUT << "Removing now-noop copy: " << MI;
|
2007-12-12 07:36:57 +08:00
|
|
|
// Unset last kill since it's being reused.
|
|
|
|
InvalidateKill(InReg, RegKills, KillOps);
|
|
|
|
}
|
2007-10-12 16:50:34 +08:00
|
|
|
|
2008-05-20 16:13:21 +08:00
|
|
|
InvalidateKills(MI, RegKills, KillOps);
|
2007-11-28 09:28:46 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(&MI);
|
2007-10-12 16:50:34 +08:00
|
|
|
MBB.erase(&MI);
|
|
|
|
Erased = true;
|
|
|
|
goto ProcessNextInst;
|
2004-10-02 07:15:36 +08:00
|
|
|
}
|
2007-10-13 10:50:24 +08:00
|
|
|
} else {
|
|
|
|
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
|
|
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
|
|
|
if (PhysReg &&
|
2008-01-07 09:35:56 +08:00
|
|
|
TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
|
2007-10-13 10:50:24 +08:00
|
|
|
MBB.insert(MII, NewMIs[0]);
|
2008-05-20 16:13:21 +08:00
|
|
|
InvalidateKills(MI, RegKills, KillOps);
|
2007-11-28 09:28:46 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(&MI);
|
2007-10-13 10:50:24 +08:00
|
|
|
MBB.erase(&MI);
|
|
|
|
Erased = true;
|
|
|
|
--NextMII; // backtrack to the unfolded instruction.
|
|
|
|
BackTracked = true;
|
|
|
|
goto ProcessNextInst;
|
|
|
|
}
|
2004-10-02 07:15:36 +08:00
|
|
|
}
|
Teach the local spiller to turn stack slot loads into register-register copies
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).
This patch came about when I noticed code like the following being generated:
store R17 -> [SS1]
...blah...
R4 = load [SS1]
This was causing an LSU reject on the G5. This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register. In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.
This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).
Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.
llvm-svn: 23388
2005-09-19 14:56:21 +08:00
|
|
|
}
|
2004-10-02 03:47:12 +08:00
|
|
|
|
Teach the local spiller to turn stack slot loads into register-register copies
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).
This patch came about when I noticed code like the following being generated:
store R17 -> [SS1]
...blah...
R4 = load [SS1]
This was causing an LSU reject on the G5. This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register. In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.
This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).
Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.
llvm-svn: 23388
2005-09-19 14:56:21 +08:00
|
|
|
// If this reference is not a use, any previous store is now dead.
|
|
|
|
// Otherwise, the store to this stack slot is not dead anymore.
|
2007-08-14 17:11:18 +08:00
|
|
|
MachineInstr* DeadStore = MaybeDeadStores[SS];
|
|
|
|
if (DeadStore) {
|
2007-10-20 05:23:22 +08:00
|
|
|
bool isDead = !(MR & VirtRegMap::isRef);
|
2007-10-13 10:50:24 +08:00
|
|
|
MachineInstr *NewStore = NULL;
|
2007-10-22 11:01:44 +08:00
|
|
|
if (MR & VirtRegMap::isModRef) {
|
2007-10-13 10:50:24 +08:00
|
|
|
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
|
|
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
2007-12-05 03:19:45 +08:00
|
|
|
// We can reuse this physreg as long as we are allowed to clobber
|
2007-12-31 12:13:23 +08:00
|
|
|
// the value and there isn't an earlier def that has already clobbered
|
|
|
|
// the physreg.
|
2007-10-13 10:50:24 +08:00
|
|
|
if (PhysReg &&
|
2008-05-07 08:49:28 +08:00
|
|
|
!TII->isStoreToStackSlot(&MI, SS)) { // Not profitable!
|
|
|
|
MachineOperand *KillOpnd =
|
|
|
|
DeadStore->findRegisterUseOperand(PhysReg, true);
|
|
|
|
// Note, if the store is storing a sub-register, it's possible the
|
|
|
|
// super-register is needed below.
|
|
|
|
if (KillOpnd && !KillOpnd->getSubReg() &&
|
|
|
|
TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){
|
|
|
|
MBB.insert(MII, NewMIs[0]);
|
|
|
|
NewStore = NewMIs[1];
|
|
|
|
MBB.insert(MII, NewStore);
|
|
|
|
VRM.addSpillSlotUse(SS, NewStore);
|
2008-05-20 16:13:21 +08:00
|
|
|
InvalidateKills(MI, RegKills, KillOps);
|
2008-05-07 08:49:28 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(&MI);
|
|
|
|
MBB.erase(&MI);
|
|
|
|
Erased = true;
|
|
|
|
--NextMII;
|
|
|
|
--NextMII; // backtrack to the unfolded instruction.
|
|
|
|
BackTracked = true;
|
|
|
|
isDead = true;
|
|
|
|
}
|
2007-10-20 05:23:22 +08:00
|
|
|
}
|
2007-10-13 10:50:24 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (isDead) { // Previous store is dead.
|
Teach the local spiller to turn stack slot loads into register-register copies
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).
This patch came about when I noticed code like the following being generated:
store R17 -> [SS1]
...blah...
R4 = load [SS1]
This was causing an LSU reject on the G5. This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register. In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.
This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).
Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.
llvm-svn: 23388
2005-09-19 14:56:21 +08:00
|
|
|
// If we get here, the store is dead, nuke it now.
|
2007-08-14 17:11:18 +08:00
|
|
|
DOUT << "Removed dead store:\t" << *DeadStore;
|
|
|
|
InvalidateKills(*DeadStore, RegKills, KillOps);
|
2007-11-28 09:28:46 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(DeadStore);
|
2007-10-13 10:50:24 +08:00
|
|
|
MBB.erase(DeadStore);
|
|
|
|
if (!NewStore)
|
|
|
|
++NumDSE;
|
Teach the local spiller to turn stack slot loads into register-register copies
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).
This patch came about when I noticed code like the following being generated:
store R17 -> [SS1]
...blah...
R4 = load [SS1]
This was causing an LSU reject on the G5. This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register. In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.
This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).
Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.
llvm-svn: 23388
2005-09-19 14:56:21 +08:00
|
|
|
}
|
2007-10-13 10:50:24 +08:00
|
|
|
|
2007-08-14 17:11:18 +08:00
|
|
|
MaybeDeadStores[SS] = NULL;
|
2007-10-13 10:50:24 +08:00
|
|
|
if (NewStore) {
|
|
|
|
// Treat this store as a spill merged into a copy. That makes the
|
|
|
|
// stack slot value available.
|
|
|
|
VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
|
|
|
|
goto ProcessNextInst;
|
|
|
|
}
|
Teach the local spiller to turn stack slot loads into register-register copies
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).
This patch came about when I noticed code like the following being generated:
store R17 -> [SS1]
...blah...
R4 = load [SS1]
This was causing an LSU reject on the G5. This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register. In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.
This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).
Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.
llvm-svn: 23388
2005-09-19 14:56:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// If the spill slot value is available, and this is a new definition of
|
|
|
|
// the value, the value is not available anymore.
|
|
|
|
if (MR & VirtRegMap::isMod) {
|
Physregs may hold multiple stack slot values at the same time. Keep track
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 08:36:31 +08:00
|
|
|
// Notice that the value in this stack slot has been modified.
|
2007-08-14 07:45:17 +08:00
|
|
|
Spills.ModifyStackSlotOrReMat(SS);
|
Fix a deficiency in the spiller that Evan noticed. In particular, consider
this code:
store [stack slot #0], R10
= add R14, [stack slot #0]
The spiller didn't know that the store made the value of [stackslot#0] available
in R10 *IF* the store came from a copy instruction with the store folded into it.
This patch teaches VirtRegMap to look at these stores and recognize the values
they make available. In one case Evan provided, this code:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
1) movsd QWORD PTR [%ESP + 48], %XMM1
2) movsd %XMM1, QWORD PTR [%ESP + 48]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
turns into:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
In this case, instruction #2 was removed because of the value made
available by #1, and inst #1 was later deleted because it is now
never used before the stack slot is redefined by #3.
This occurs here and there in a lot of code with high spilling, on PPC
most of the removed loads/stores are LSU-reject-causing loads, which is
nice.
On X86, things are much better (because it spills more), where we nuke
about 1% of the instructions from SMG2000 and several hundred from eon.
More improvements to come...
llvm-svn: 25917
2006-02-03 07:29:36 +08:00
|
|
|
|
|
|
|
// If this is *just* a mod of the value, check to see if this is just a
|
|
|
|
// store to the spill slot (i.e. the spill got merged into the copy). If
|
|
|
|
// so, realize that the vreg is available now, and add the store to the
|
|
|
|
// MaybeDeadStore info.
|
|
|
|
int StackSlot;
|
|
|
|
if (!(MR & VirtRegMap::isRef)) {
|
|
|
|
if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
|
2008-02-11 02:45:23 +08:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
|
Fix a deficiency in the spiller that Evan noticed. In particular, consider
this code:
store [stack slot #0], R10
= add R14, [stack slot #0]
The spiller didn't know that the store made the value of [stackslot#0] available
in R10 *IF* the store came from a copy instruction with the store folded into it.
This patch teaches VirtRegMap to look at these stores and recognize the values
they make available. In one case Evan provided, this code:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
1) movsd QWORD PTR [%ESP + 48], %XMM1
2) movsd %XMM1, QWORD PTR [%ESP + 48]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
turns into:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
In this case, instruction #2 was removed because of the value made
available by #1, and inst #1 was later deleted because it is now
never used before the stack slot is redefined by #3.
This occurs here and there in a lot of code with high spilling, on PPC
most of the removed loads/stores are LSU-reject-causing loads, which is
nice.
On X86, things are much better (because it spills more), where we nuke
about 1% of the instructions from SMG2000 and several hundred from eon.
More improvements to come...
llvm-svn: 25917
2006-02-03 07:29:36 +08:00
|
|
|
"Src hasn't been allocated yet?");
|
Physregs may hold multiple stack slot values at the same time. Keep track
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 08:36:31 +08:00
|
|
|
// Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
|
Fix a deficiency in the spiller that Evan noticed. In particular, consider
this code:
store [stack slot #0], R10
= add R14, [stack slot #0]
The spiller didn't know that the store made the value of [stackslot#0] available
in R10 *IF* the store came from a copy instruction with the store folded into it.
This patch teaches VirtRegMap to look at these stores and recognize the values
they make available. In one case Evan provided, this code:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
1) movsd QWORD PTR [%ESP + 48], %XMM1
2) movsd %XMM1, QWORD PTR [%ESP + 48]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
turns into:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
In this case, instruction #2 was removed because of the value made
available by #1, and inst #1 was later deleted because it is now
never used before the stack slot is redefined by #3.
This occurs here and there in a lot of code with high spilling, on PPC
most of the removed loads/stores are LSU-reject-causing loads, which is
nice.
On X86, things are much better (because it spills more), where we nuke
about 1% of the instructions from SMG2000 and several hundred from eon.
More improvements to come...
llvm-svn: 25917
2006-02-03 07:29:36 +08:00
|
|
|
// this as a potentially dead store in case there is a subsequent
|
|
|
|
// store into the stack slot without a read from it.
|
|
|
|
MaybeDeadStores[StackSlot] = &MI;
|
|
|
|
|
|
|
|
// If the stack slot value was previously available in some other
|
|
|
|
// register, change it now. Otherwise, make the register available,
|
|
|
|
// in PhysReg.
|
2007-02-23 09:13:26 +08:00
|
|
|
Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
|
Fix a deficiency in the spiller that Evan noticed. In particular, consider
this code:
store [stack slot #0], R10
= add R14, [stack slot #0]
The spiller didn't know that the store made the value of [stackslot#0] available
in R10 *IF* the store came from a copy instruction with the store folded into it.
This patch teaches VirtRegMap to look at these stores and recognize the values
they make available. In one case Evan provided, this code:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
1) movsd QWORD PTR [%ESP + 48], %XMM1
2) movsd %XMM1, QWORD PTR [%ESP + 48]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
turns into:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
In this case, instruction #2 was removed because of the value made
available by #1, and inst #1 was later deleted because it is now
never used before the stack slot is redefined by #3.
This occurs here and there in a lot of code with high spilling, on PPC
most of the removed loads/stores are LSU-reject-causing loads, which is
nice.
On X86, things are much better (because it spills more), where we nuke
about 1% of the instructions from SMG2000 and several hundred from eon.
More improvements to come...
llvm-svn: 25917
2006-02-03 07:29:36 +08:00
|
|
|
}
|
|
|
|
}
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
}
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
2004-02-24 16:58:30 +08:00
|
|
|
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
// Process all of the spilled defs.
|
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI.getOperand(i);
|
2007-10-20 05:23:22 +08:00
|
|
|
if (!(MO.isRegister() && MO.getReg() && MO.isDef()))
|
|
|
|
continue;
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
|
2007-10-20 05:23:22 +08:00
|
|
|
unsigned VirtReg = MO.getReg();
|
2008-02-11 02:45:23 +08:00
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
|
2007-10-20 05:23:22 +08:00
|
|
|
// Check to see if this is a noop copy. If so, eliminate the
|
|
|
|
// instruction before considering the dest reg to be changed.
|
|
|
|
unsigned Src, Dst;
|
|
|
|
if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
|
|
|
|
++NumDCE;
|
|
|
|
DOUT << "Removing now-noop copy: " << MI;
|
2008-05-20 16:13:21 +08:00
|
|
|
SmallVector<unsigned, 2> KillRegs;
|
|
|
|
InvalidateKills(MI, RegKills, KillOps, &KillRegs);
|
|
|
|
if (MO.isDead() && !KillRegs.empty()) {
|
|
|
|
assert(KillRegs[0] == Dst);
|
|
|
|
// Last def is now dead.
|
|
|
|
TransferDeadness(&MBB, Dist, Src, RegKills, KillOps);
|
|
|
|
}
|
2008-02-27 11:04:06 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(&MI);
|
2007-10-20 05:23:22 +08:00
|
|
|
MBB.erase(&MI);
|
|
|
|
Erased = true;
|
|
|
|
Spills.disallowClobberPhysReg(VirtReg);
|
|
|
|
goto ProcessNextInst;
|
|
|
|
}
|
2006-10-13 01:45:38 +08:00
|
|
|
|
2007-10-20 05:23:22 +08:00
|
|
|
// If it's not a no-op copy, it clobbers the value in the destreg.
|
|
|
|
Spills.ClobberPhysReg(VirtReg);
|
|
|
|
ReusedOperands.markClobbered(VirtReg);
|
2006-10-13 01:45:38 +08:00
|
|
|
|
2007-10-20 05:23:22 +08:00
|
|
|
// Check to see if this instruction is a load from a stack slot into
|
|
|
|
// a register. If so, this provides the stack slot value in the reg.
|
|
|
|
int FrameIdx;
|
|
|
|
if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
|
|
|
|
assert(DestReg == VirtReg && "Unknown load situation!");
|
|
|
|
|
|
|
|
// If it is a folded reference, then it's not safe to clobber.
|
|
|
|
bool Folded = FoldedSS.count(FrameIdx);
|
|
|
|
// Otherwise, if it wasn't available, remember that it is now!
|
|
|
|
Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded);
|
|
|
|
goto ProcessNextInst;
|
2005-04-22 06:36:52 +08:00
|
|
|
}
|
2007-10-20 05:23:22 +08:00
|
|
|
|
|
|
|
continue;
|
|
|
|
}
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
|
2007-11-14 15:59:08 +08:00
|
|
|
unsigned SubIdx = MO.getSubReg();
|
2007-10-20 05:23:22 +08:00
|
|
|
bool DoReMat = VRM.isReMaterialized(VirtReg);
|
|
|
|
if (DoReMat)
|
|
|
|
ReMatDefs.insert(&MI);
|
|
|
|
|
|
|
|
// The only vregs left are stack slot definitions.
|
|
|
|
int StackSlot = VRM.getStackSlot(VirtReg);
|
2007-12-31 12:13:23 +08:00
|
|
|
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
|
2007-10-20 05:23:22 +08:00
|
|
|
|
|
|
|
// If this def is part of a two-address operand, make sure to execute
|
|
|
|
// the store from the correct physical register.
|
|
|
|
unsigned PhysReg;
|
2008-01-07 15:27:27 +08:00
|
|
|
int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
|
2007-11-03 01:35:08 +08:00
|
|
|
if (TiedOp != -1) {
|
2007-10-20 05:23:22 +08:00
|
|
|
PhysReg = MI.getOperand(TiedOp).getReg();
|
2007-11-14 15:59:08 +08:00
|
|
|
if (SubIdx) {
|
2008-02-11 02:45:23 +08:00
|
|
|
unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
|
|
|
|
assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
|
2007-11-03 01:35:08 +08:00
|
|
|
"Can't find corresponding super-register!");
|
|
|
|
PhysReg = SuperReg;
|
|
|
|
}
|
|
|
|
} else {
|
2007-10-20 05:23:22 +08:00
|
|
|
PhysReg = VRM.getPhys(VirtReg);
|
|
|
|
if (ReusedOperands.isClobbered(PhysReg)) {
|
|
|
|
// Another def has taken the assigned physreg. It must have been a
|
|
|
|
// use&def which got it due to reuse. Undo the reuse!
|
|
|
|
PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
|
2007-08-14 07:45:17 +08:00
|
|
|
Spills, MaybeDeadStores, RegKills, KillOps, VRM);
|
2006-11-04 08:21:55 +08:00
|
|
|
}
|
2007-10-20 05:23:22 +08:00
|
|
|
}
|
2006-02-03 11:06:49 +08:00
|
|
|
|
2008-03-27 03:03:01 +08:00
|
|
|
assert(PhysReg && "VR not assigned a physical register?");
|
2007-12-31 12:13:23 +08:00
|
|
|
RegInfo->setPhysRegUsed(PhysReg);
|
2008-02-11 02:45:23 +08:00
|
|
|
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
2007-11-03 01:35:08 +08:00
|
|
|
ReusedOperands.markClobbered(RReg);
|
|
|
|
MI.getOperand(i).setReg(RReg);
|
|
|
|
|
2007-10-20 05:23:22 +08:00
|
|
|
if (!MO.isDead()) {
|
|
|
|
MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
|
2007-12-05 03:19:45 +08:00
|
|
|
SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
|
|
|
|
LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
|
2007-12-04 05:31:55 +08:00
|
|
|
NextMII = next(MII);
|
2007-10-20 05:23:22 +08:00
|
|
|
|
|
|
|
// Check to see if this is a noop copy. If so, eliminate the
|
|
|
|
// instruction before considering the dest reg to be changed.
|
|
|
|
{
|
|
|
|
unsigned Src, Dst;
|
|
|
|
if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
|
|
|
|
++NumDCE;
|
|
|
|
DOUT << "Removing now-noop copy: " << MI;
|
2008-05-20 16:13:21 +08:00
|
|
|
InvalidateKills(MI, RegKills, KillOps);
|
2008-02-27 11:04:06 +08:00
|
|
|
VRM.RemoveMachineInstrFromMaps(&MI);
|
2007-10-20 05:23:22 +08:00
|
|
|
MBB.erase(&MI);
|
|
|
|
Erased = true;
|
|
|
|
UpdateKills(*LastStore, RegKills, KillOps);
|
|
|
|
goto ProcessNextInst;
|
Fixed a long standing spiller bug that's exposed by Thumb:
The code sequence before the spiller is something like:
= tMOVrr
%reg1117 = tMOVrr
%reg1078 = tLSLri %reg1117, 2
The it starts spilling:
%r0 = tRestore <fi#5>, 0
%r1 = tRestore <fi#7>, 0
%r1 = tMOVrr %r1<kill>
tSpill %r1, <fi#5>, 0
%reg1078 = tLSLri %reg1117, 2
It restores the value while processing the first tMOVrr. At this point, the
spiller remembers fi#5 is available in %r0. Next it processes the second move.
It restores the source before the move and spills the result afterwards. The
move becomes a noop and is deleted. However, a spill has been inserted and that
should invalidate reuse of %r0 for fi#5 and add reuse of %r1 for fi#5.
Therefore, %reg1117 (which is also assigned fi#5) should get %r1, not %r0.
llvm-svn: 34039
2007-02-08 14:04:54 +08:00
|
|
|
}
|
2007-10-20 05:23:22 +08:00
|
|
|
}
|
|
|
|
}
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
Teach the local spiller to turn stack slot loads into register-register copies
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).
This patch came about when I noticed code like the following being generated:
store R17 -> [SS1]
...blah...
R4 = load [SS1]
This was causing an LSU reject on the G5. This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register. In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.
This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).
Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.
llvm-svn: 23388
2005-09-19 14:56:21 +08:00
|
|
|
ProcessNextInst:
|
2008-05-20 16:13:21 +08:00
|
|
|
DistanceMap.insert(std::make_pair(&MI, Dist++));
|
2007-12-05 03:19:45 +08:00
|
|
|
if (!Erased && !BackTracked) {
|
2007-07-11 13:28:39 +08:00
|
|
|
for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
|
|
|
|
UpdateKills(*II, RegKills, KillOps);
|
2007-12-05 03:19:45 +08:00
|
|
|
}
|
Substantially revamp the local spiller, causing it to actually improve the
generated code over the simple spiller. The new local spiller generates
substantially better code than the simple one in some cases, by reusing
values that are loaded out of stack slots and kept available in registers.
This primarily helps programs that are spilling a lot, and there is still
stuff that can be done to improve it. This patch makes the local spiller
the default, as it's only a tiny bit slower than the simple spiller (it
increases the runtime of llc by < 1%).
Here are some numbers with speedups.
Program #reuse old(s) new(s) Speedup
Povray: 3452, 16.87 -> 15.93 (5.5%)
177.mesa: 2176, 2.77 -> 2.76 (0%)
179.art: 35, 28.43 -> 28.01 (1.5%)
183.equake: 55, 61.44 -> 61.41 (0%)
188.ammp: 869, 174 -> 149 (15%)
164.gzip: 43, 40.73 -> 40.71 (0%)
175.vpr: 351, 18.54 -> 17.34 (6.5%)
176.gcc: 2471, 5.01 -> 4.92 (1.8%)
181.mcf 42, 79.30 -> 75.20 (5.2%)
186.crafty: 484, 29.73 -> 30.04 (-1%)
197.parser: 251, 10.47 -> 10.67 (-1%)
252.eon: 1501, 1.98 -> 1.75 (12%)
253.perlbm: 1183, 14.83 -> 14.42 (2.8%)
254.gap: 825, 7.46 -> 7.29 (2.3%)
255.vortex: 285, 10.51 -> 10.27 (2.3%)
256.bzip2: 63, 55.70 -> 55.20 (0.9%)
300.twolf: 830, 21.63 -> 22.00 (-1%)
PtrDist/ks 14, 32.75 -> 17.53 (46.5%)
Olden/tsp 46, 8.71 -> 8.24 (5.4%)
Free/distray 70, 1.09 -> 0.99 (9.2%)
llvm-svn: 16629
2004-10-02 03:04:51 +08:00
|
|
|
MII = NextMII;
|
2004-09-30 09:54:45 +08:00
|
|
|
}
|
2004-02-24 16:58:30 +08:00
|
|
|
}
|
|
|
|
|
2004-09-30 09:54:45 +08:00
|
|
|
llvm::Spiller* llvm::createSpiller() {
|
|
|
|
switch (SpillerOpt) {
|
|
|
|
default: assert(0 && "Unreachable!");
|
|
|
|
case local:
|
|
|
|
return new LocalSpiller();
|
|
|
|
case simple:
|
|
|
|
return new SimpleSpiller();
|
|
|
|
}
|
2004-02-24 16:58:30 +08:00
|
|
|
}
|