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llvm-project/llvm/test/CodeGen/RISCV/imm-cse.ll

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[RISCV] Add imm-cse.ll test case This test case demonstrates that common subexpression elimination takes place between code sequences for materialising constants. In particular, it demonstrates that redundant lui aren't generated. This would capture a regression if applying a patch such as D41949. llvm-svn: 330291
2018-04-19 04:25:07 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
@src = global i32 0
@dst = global i32 0
; Tests that the common hi20 value (1) for the constants is used rather than
; redundantly re-materialised.
define void @imm32_cse() nounwind {
; RV32I-LABEL: imm32_cse:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 1
[RISCV] Add RISCV-specific TargetTransformInfo Summary: LLVM Allows Targets to provide information that guides optimisations made to LLVM IR. This is done with callbacks on a TargetTransformInfo object. This patch adds a TargetTransformInfo class for RISC-V. This will allow us to implement RISC-V specific callbacks as they become necessary. This commit also adds the getIntImmCost callbacks, and tests them with a simple constant hoisting test. Our immediate costs are on the conservative side, for the moment, but we prevent hoisting in most circumstances anyway. Previous review was on D63007 Reviewers: asb, luismarques Reviewed By: asb Subscribers: ributzka, MaskRay, llvm-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya, mgorny Tags: #llvm Differential Revision: https://reviews.llvm.org/D63433 llvm-svn: 364046
2019-06-21 21:36:09 +08:00
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: lui a1, %hi(src)
; RV32I-NEXT: lw a2, %lo(src)(a1)
; RV32I-NEXT: add a2, a2, a0
[RISCV] Add imm-cse.ll test case This test case demonstrates that common subexpression elimination takes place between code sequences for materialising constants. In particular, it demonstrates that redundant lui aren't generated. This would capture a regression if applying a patch such as D41949. llvm-svn: 330291
2018-04-19 04:25:07 +08:00
; RV32I-NEXT: lui a3, %hi(dst)
[RISCV] Add RISCV-specific TargetTransformInfo Summary: LLVM Allows Targets to provide information that guides optimisations made to LLVM IR. This is done with callbacks on a TargetTransformInfo object. This patch adds a TargetTransformInfo class for RISC-V. This will allow us to implement RISC-V specific callbacks as they become necessary. This commit also adds the getIntImmCost callbacks, and tests them with a simple constant hoisting test. Our immediate costs are on the conservative side, for the moment, but we prevent hoisting in most circumstances anyway. Previous review was on D63007 Reviewers: asb, luismarques Reviewed By: asb Subscribers: ributzka, MaskRay, llvm-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya, mgorny Tags: #llvm Differential Revision: https://reviews.llvm.org/D63433 llvm-svn: 364046
2019-06-21 21:36:09 +08:00
; RV32I-NEXT: sw a2, %lo(dst)(a3)
; RV32I-NEXT: lw a2, %lo(src)(a1)
; RV32I-NEXT: add a2, a2, a0
; RV32I-NEXT: addi a2, a2, 1
; RV32I-NEXT: sw a2, %lo(dst)(a3)
; RV32I-NEXT: lw a1, %lo(src)(a1)
[RISCV] Add imm-cse.ll test case This test case demonstrates that common subexpression elimination takes place between code sequences for materialising constants. In particular, it demonstrates that redundant lui aren't generated. This would capture a regression if applying a patch such as D41949. llvm-svn: 330291
2018-04-19 04:25:07 +08:00
; RV32I-NEXT: add a0, a1, a0
[RISCV] Add RISCV-specific TargetTransformInfo Summary: LLVM Allows Targets to provide information that guides optimisations made to LLVM IR. This is done with callbacks on a TargetTransformInfo object. This patch adds a TargetTransformInfo class for RISC-V. This will allow us to implement RISC-V specific callbacks as they become necessary. This commit also adds the getIntImmCost callbacks, and tests them with a simple constant hoisting test. Our immediate costs are on the conservative side, for the moment, but we prevent hoisting in most circumstances anyway. Previous review was on D63007 Reviewers: asb, luismarques Reviewed By: asb Subscribers: ributzka, MaskRay, llvm-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya, mgorny Tags: #llvm Differential Revision: https://reviews.llvm.org/D63433 llvm-svn: 364046
2019-06-21 21:36:09 +08:00
; RV32I-NEXT: addi a0, a0, 2
[RISCV] Add imm-cse.ll test case This test case demonstrates that common subexpression elimination takes place between code sequences for materialising constants. In particular, it demonstrates that redundant lui aren't generated. This would capture a regression if applying a patch such as D41949. llvm-svn: 330291
2018-04-19 04:25:07 +08:00
; RV32I-NEXT: sw a0, %lo(dst)(a3)
; RV32I-NEXT: ret
%1 = load volatile i32, i32* @src
%2 = add i32 %1, 4097
store volatile i32 %2, i32* @dst
%3 = load volatile i32, i32* @src
%4 = add i32 %3, 4098
store volatile i32 %4, i32* @dst
%5 = load volatile i32, i32* @src
%6 = add i32 %5, 4099
store volatile i32 %6, i32* @dst
ret void
}