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llvm-project/llvm/test/CodeGen/RISCV/branch-relaxation.ll

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[RISCV] Implement support for the BranchRelaxation pass Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field. Differential Revision: https://reviews.llvm.org/D40830 llvm-svn: 322224
2018-01-11 05:05:07 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -filetype=obj < %s \
; RUN: -o /dev/null 2>&1
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives. llvm-svn: 361493
2019-05-23 20:43:13 +08:00
define void @relax_bcc(i1 %a) nounwind {
[RISCV] Implement support for the BranchRelaxation pass Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field. Differential Revision: https://reviews.llvm.org/D40830 llvm-svn: 322224
2018-01-11 05:05:07 +08:00
; CHECK-LABEL: relax_bcc:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: bnez a0, .LBB0_1
; CHECK-NEXT: j .LBB0_2
; CHECK-NEXT: .LBB0_1: # %iftrue
; CHECK-NEXT: #APP
; CHECK-NEXT: .space 4096
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB0_2: # %tail
; CHECK-NEXT: ret
br i1 %a, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 4096", ""()
br label %tail
tail:
ret void
}
[RISCV] Match GNU tools canonical JALR and add aliases The canonical GNU form of JALR resembles a load/store instruction rather than placing the immediate offset as a separate argument, so match this behaviour. Also add parser-only aliases for the three-operand form, and add other shorter aliases also emitted by GNU tools. Differential Revision: https://reviews.llvm.org/D55277 Patch by James Clarke. llvm-svn: 366179
2019-07-16 12:56:43 +08:00
; TODO: Extend simm12's MCOperandPredicate so the jalr zero is printed as a jr.
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives. llvm-svn: 361493
2019-05-23 20:43:13 +08:00
define i32 @relax_jal(i1 %a) nounwind {
[RISCV] Implement support for the BranchRelaxation pass Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field. Differential Revision: https://reviews.llvm.org/D40830 llvm-svn: 322224
2018-01-11 05:05:07 +08:00
; CHECK-LABEL: relax_jal:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: bnez a0, .LBB1_1
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; CHECK-NEXT: # %bb.3:
[RISCV] Implement support for the BranchRelaxation pass Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field. Differential Revision: https://reviews.llvm.org/D40830 llvm-svn: 322224
2018-01-11 05:05:07 +08:00
; CHECK-NEXT: lui a0, %hi(.LBB1_2)
[RISCV] Match GNU tools canonical JALR and add aliases The canonical GNU form of JALR resembles a load/store instruction rather than placing the immediate offset as a separate argument, so match this behaviour. Also add parser-only aliases for the three-operand form, and add other shorter aliases also emitted by GNU tools. Differential Revision: https://reviews.llvm.org/D55277 Patch by James Clarke. llvm-svn: 366179
2019-07-16 12:56:43 +08:00
; CHECK-NEXT: jalr zero, %lo(.LBB1_2)(a0)
[RISCV] Implement support for the BranchRelaxation pass Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field. Differential Revision: https://reviews.llvm.org/D40830 llvm-svn: 322224
2018-01-11 05:05:07 +08:00
; CHECK-NEXT: .LBB1_1: # %iftrue
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: .space 1048576
; CHECK-NEXT: #NO_APP
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; CHECK-NEXT: addi a0, zero, 1
; CHECK-NEXT: ret
[RISCV] Implement support for the BranchRelaxation pass Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field. Differential Revision: https://reviews.llvm.org/D40830 llvm-svn: 322224
2018-01-11 05:05:07 +08:00
; CHECK-NEXT: .LBB1_2: # %jmp
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: addi a0, zero, 1
; CHECK-NEXT: ret
br i1 %a, label %iftrue, label %jmp
jmp:
call void asm sideeffect "", ""()
br label %tail
iftrue:
call void asm sideeffect "", ""()
br label %space
space:
call void asm sideeffect ".space 1048576", ""()
br label %tail
tail:
ret i32 1
}