llvm-project/polly/test/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop.transformed

{
   "context" : "[arg] -> {  : arg >= -9223372036854775808 and arg <= 9223372036854775807 }",
   "name" : "loop1 => exit",
   "statements" : [
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "[arg] -> { Stmt_loop1[i0] -> MemRef_A[5 * i0 - 10]  }"
            }
         ],
         "domain" : "[arg] -> { Stmt_loop1[i0] : i0 >= 0 and i0 <= -2 + arg }",
         "name" : "Stmt_loop1",
         "schedule" : "[arg] -> { Stmt_loop1[i0] -> [0, i0] }"
      },
      {
         "accesses" : [
            {
               "kind" : "read",
               "relation" : "[arg] -> { Stmt_loop2[i0] -> MemRef_A[42] }"
            },
            {
               "kind" : "write",
               "relation" : "[arg] -> { Stmt_loop2[i0] -> MemRef_val[] }"
            }
         ],
         "domain" : "[arg] -> { Stmt_loop2[i0] : i0 >= 0 and i0 <= -2 + arg }",
         "name" : "Stmt_loop2",
         "schedule" : "[arg] -> { Stmt_loop2[i0] -> [1, i0] }"
      },
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_A[13 * i0 + 5] }"
            },
            {
               "kind" : "read",
               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_val[] }"
            }
         ],
         "domain" : "[arg] -> { Stmt_loop3[i0] : i0 >= 0 and i0 <= -2 + arg }",
         "name" : "Stmt_loop3",
         "schedule" : "[arg] -> { Stmt_loop3[i0] -> [2, i0] }"
      }
   ]
}