[x86, InstCombine] transform x86 AVX masked stores to LLVM intrinsics
The intended effect of this patch in conjunction with:
http://reviews.llvm.org/rL259392
http://reviews.llvm.org/rL260145
is that customers using the AVX intrinsics in C will benefit from combines when
the store mask is constant:
void mstore_zero_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set1_epi32(0), v);
}
void mstore_fake_ones_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set1_epi32(1), v);
}
void mstore_ones_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set1_epi32(0x80000000), v);
}
void mstore_one_set_elt_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set_epi32(0x80000000, 0, 0, 0), v);
}
...so none of the above will actually generate a masked store for optimized code.
Differential Revision: http://reviews.llvm.org/D17485
llvm-svn: 262064
2016-02-27 05:04:14 +08:00
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; If the mask isn't constant, do nothing.
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define void @mstore(i8* %f, <4 x i32> %mask, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> %mask, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore(
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; CHECK-NEXT: tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> %mask, <4 x float> %v)
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; CHECK-NEXT: ret void
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}
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; Zero mask is a nop.
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define void @mstore_zeros(i8* %f, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> zeroinitializer, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_zeros(
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; CHECK-NEXT: ret void
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}
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; Only the sign bit matters.
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define void @mstore_fake_ones(i8* %f, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> <i32 1, i32 2, i32 3, i32 2147483647>, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_fake_ones(
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; CHECK-NEXT: ret void
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}
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; All mask bits are set, so this is just a vector store.
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define void @mstore_real_ones(i8* %f, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> <i32 -1, i32 -2, i32 -3, i32 -2147483648>, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_real_ones(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x float>*
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; CHECK-NEXT: store <4 x float> %v, <4 x float>* %castvec
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; CHECK-NEXT: ret void
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}
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; It's a constant mask, so convert to an LLVM intrinsic. The backend should optimize further.
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define void @mstore_one_one(i8* %f, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> <i32 0, i32 0, i32 0, i32 -1>, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_one_one(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x float>*
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; CHECK-NEXT: call void @llvm.masked.store.v4f32(<4 x float> %v, <4 x float>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>)
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; CHECK-NEXT: ret void
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}
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; Try doubles.
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define void @mstore_one_one_double(i8* %f, <2 x double> %v) {
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tail call void @llvm.x86.avx.maskstore.pd(i8* %f, <2 x i64> <i64 -1, i64 0>, <2 x double> %v)
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ret void
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; CHECK-LABEL: @mstore_one_one_double(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x double>*
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; CHECK-NEXT: call void @llvm.masked.store.v2f64(<2 x double> %v, <2 x double>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>)
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; CHECK-NEXT: ret void
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}
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2016-02-27 05:51:44 +08:00
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; Try 256-bit FP ops.
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[x86, InstCombine] transform x86 AVX masked stores to LLVM intrinsics
The intended effect of this patch in conjunction with:
http://reviews.llvm.org/rL259392
http://reviews.llvm.org/rL260145
is that customers using the AVX intrinsics in C will benefit from combines when
the store mask is constant:
void mstore_zero_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set1_epi32(0), v);
}
void mstore_fake_ones_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set1_epi32(1), v);
}
void mstore_ones_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set1_epi32(0x80000000), v);
}
void mstore_one_set_elt_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set_epi32(0x80000000, 0, 0, 0), v);
}
...so none of the above will actually generate a masked store for optimized code.
Differential Revision: http://reviews.llvm.org/D17485
llvm-svn: 262064
2016-02-27 05:04:14 +08:00
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define void @mstore_v8f32(i8* %f, <8 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps.256(i8* %f, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 -1, i32 -2, i32 -3, i32 -4>, <8 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_v8f32(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x float>*
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; CHECK-NEXT: call void @llvm.masked.store.v8f32(<8 x float> %v, <8 x float>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>)
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; CHECK-NEXT: ret void
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}
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define void @mstore_v4f64(i8* %f, <4 x double> %v) {
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tail call void @llvm.x86.avx.maskstore.pd.256(i8* %f, <4 x i64> <i64 -1, i64 0, i64 1, i64 2>, <4 x double> %v)
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ret void
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; CHECK-LABEL: @mstore_v4f64(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x double>*
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; CHECK-NEXT: call void @llvm.masked.store.v4f64(<4 x double> %v, <4 x double>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)
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; CHECK-NEXT: ret void
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}
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2016-02-27 05:51:44 +08:00
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; Try the AVX2 variants.
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define void @mstore_v4i32(i8* %f, <4 x i32> %v) {
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tail call void @llvm.x86.avx2.maskstore.d(i8* %f, <4 x i32> <i32 0, i32 1, i32 -1, i32 -2>, <4 x i32> %v)
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ret void
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; CHECK-LABEL: @mstore_v4i32(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i32>*
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; CHECK-NEXT: call void @llvm.masked.store.v4i32(<4 x i32> %v, <4 x i32>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 true, i1 true>)
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; CHECK-NEXT: ret void
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}
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define void @mstore_v2i64(i8* %f, <2 x i64> %v) {
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tail call void @llvm.x86.avx2.maskstore.q(i8* %f, <2 x i64> <i64 -1, i64 0>, <2 x i64> %v)
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ret void
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; CHECK-LABEL: @mstore_v2i64(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x i64>*
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; CHECK-NEXT: call void @llvm.masked.store.v2i64(<2 x i64> %v, <2 x i64>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>)
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; CHECK-NEXT: ret void
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}
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define void @mstore_v8i32(i8* %f, <8 x i32> %v) {
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tail call void @llvm.x86.avx2.maskstore.d.256(i8* %f, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 -1, i32 -2, i32 -3, i32 -4>, <8 x i32> %v)
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ret void
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; CHECK-LABEL: @mstore_v8i32(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x i32>*
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; CHECK-NEXT: call void @llvm.masked.store.v8i32(<8 x i32> %v, <8 x i32>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>)
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; CHECK-NEXT: ret void
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}
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define void @mstore_v4i64(i8* %f, <4 x i64> %v) {
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tail call void @llvm.x86.avx2.maskstore.q.256(i8* %f, <4 x i64> <i64 -1, i64 0, i64 1, i64 2>, <4 x i64> %v)
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ret void
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; CHECK-LABEL: @mstore_v4i64(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i64>*
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; CHECK-NEXT: call void @llvm.masked.store.v4i64(<4 x i64> %v, <4 x i64>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)
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; CHECK-NEXT: ret void
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}
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[x86, InstCombine] transform x86 AVX masked stores to LLVM intrinsics
The intended effect of this patch in conjunction with:
http://reviews.llvm.org/rL259392
http://reviews.llvm.org/rL260145
is that customers using the AVX intrinsics in C will benefit from combines when
the store mask is constant:
void mstore_zero_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set1_epi32(0), v);
}
void mstore_fake_ones_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set1_epi32(1), v);
}
void mstore_ones_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set1_epi32(0x80000000), v);
}
void mstore_one_set_elt_mask(float *f, __m128 v) {
_mm_maskstore_ps(f, _mm_set_epi32(0x80000000, 0, 0, 0), v);
}
...so none of the above will actually generate a masked store for optimized code.
Differential Revision: http://reviews.llvm.org/D17485
llvm-svn: 262064
2016-02-27 05:04:14 +08:00
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declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x i32>, <4 x float>)
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declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x i64>, <2 x double>)
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declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>)
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declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x i64>, <4 x double>)
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2016-02-27 05:51:44 +08:00
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declare void @llvm.x86.avx2.maskstore.d(i8*, <4 x i32>, <4 x i32>)
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declare void @llvm.x86.avx2.maskstore.q(i8*, <2 x i64>, <2 x i64>)
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declare void @llvm.x86.avx2.maskstore.d.256(i8*, <8 x i32>, <8 x i32>)
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declare void @llvm.x86.avx2.maskstore.q.256(i8*, <4 x i64>, <4 x i64>)
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