2017-07-05 01:32:00 +08:00
|
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI %s
|
|
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=CI %s
|
|
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI --check-prefix=GCN-HSA %s
|
2015-09-29 04:54:32 +08:00
|
|
|
|
2016-02-11 14:02:01 +08:00
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.y() #0
|
2014-03-21 23:51:54 +08:00
|
|
|
|
|
|
|
; In this test both the pointer and the offset operands to the
|
|
|
|
; BUFFER_LOAD instructions end up being stored in vgprs. This
|
|
|
|
; requires us to add the pointer and offset together, store the
|
|
|
|
; result in the offset operand (vaddr), and then store 0 in an
|
|
|
|
; sgpr register pair and use that for the pointer operand
|
|
|
|
; (low 64-bits of srsrc).
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}mubuf:
|
2014-03-21 23:51:57 +08:00
|
|
|
|
2014-11-05 22:50:53 +08:00
|
|
|
; Make sure we aren't using VGPRs for the source operand of s_mov_b64
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
|
2014-03-21 23:51:57 +08:00
|
|
|
|
|
|
|
; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
|
|
|
|
; instructions
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
|
|
|
|
; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
|
|
|
|
; GCN-HSA: flat_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}
|
|
|
|
; GCN-HSA: flat_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}
|
2015-09-29 04:54:32 +08:00
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #1 {
|
2014-03-21 23:51:54 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
|
%tmp1 = call i32 @llvm.amdgcn.workitem.id.y()
|
2015-09-29 04:54:32 +08:00
|
|
|
%tmp2 = sext i32 %tmp to i64
|
|
|
|
%tmp3 = sext i32 %tmp1 to i64
|
2014-03-21 23:51:54 +08:00
|
|
|
br label %loop
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
loop: ; preds = %loop, %entry
|
|
|
|
%tmp4 = phi i64 [ 0, %entry ], [ %tmp5, %loop ]
|
|
|
|
%tmp5 = add i64 %tmp2, %tmp4
|
|
|
|
%tmp6 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp5
|
|
|
|
%tmp7 = load i8, i8 addrspace(1)* %tmp6, align 1
|
|
|
|
%tmp8 = or i64 %tmp5, 1
|
|
|
|
%tmp9 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp8
|
|
|
|
%tmp10 = load i8, i8 addrspace(1)* %tmp9, align 1
|
|
|
|
%tmp11 = add i8 %tmp7, %tmp10
|
|
|
|
%tmp12 = sext i8 %tmp11 to i32
|
|
|
|
store i32 %tmp12, i32 addrspace(1)* %out
|
|
|
|
%tmp13 = icmp slt i64 %tmp5, 10
|
|
|
|
br i1 %tmp13, label %loop, label %done
|
|
|
|
|
|
|
|
done: ; preds = %loop
|
2014-03-21 23:51:54 +08:00
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2014-04-30 23:31:29 +08:00
|
|
|
; Test moving an SMRD instruction to the VALU
|
2016-05-21 11:55:07 +08:00
|
|
|
; FIXME: movs can be moved before nop to reduce count
|
2014-04-30 23:31:29 +08:00
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu:
|
2016-02-20 08:37:25 +08:00
|
|
|
; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0
|
2017-03-11 08:29:27 +08:00
|
|
|
; SI: s_mov_b32
|
2016-02-20 08:37:25 +08:00
|
|
|
; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
|
|
|
|
; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
|
2016-05-21 11:55:07 +08:00
|
|
|
; SI: s_nop 3
|
2016-02-20 08:37:25 +08:00
|
|
|
; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]]
|
2016-05-21 11:55:07 +08:00
|
|
|
|
2016-02-20 08:37:25 +08:00
|
|
|
; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8
|
|
|
|
; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]]
|
|
|
|
; GCN-NOHSA: buffer_store_dword [[V_OUT]]
|
|
|
|
; GCN-HSA: flat_store_dword {{.*}}, [[V_OUT]]
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu(i32 addrspace(4)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 {
|
2014-04-30 23:31:29 +08:00
|
|
|
entry:
|
2015-09-29 04:54:32 +08:00
|
|
|
%tmp = icmp ne i32 %a, 0
|
|
|
|
br i1 %tmp, label %if, label %else
|
2014-04-30 23:31:29 +08:00
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
if: ; preds = %entry
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp1 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(1)* %in
|
2014-04-30 23:31:29 +08:00
|
|
|
br label %endif
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
else: ; preds = %entry
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr i32 addrspace(4)*, i32 addrspace(4)* addrspace(1)* %in
|
|
|
|
%tmp3 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(1)* %tmp2
|
2014-04-30 23:31:29 +08:00
|
|
|
br label %endif
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
endif: ; preds = %else, %if
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp4 = phi i32 addrspace(4)* [ %tmp1, %if ], [ %tmp3, %else ]
|
|
|
|
%tmp5 = getelementptr i32, i32 addrspace(4)* %tmp4, i32 3000
|
|
|
|
%tmp6 = load i32, i32 addrspace(4)* %tmp5
|
2015-09-29 04:54:32 +08:00
|
|
|
store i32 %tmp6, i32 addrspace(1)* %out
|
2014-04-30 23:31:29 +08:00
|
|
|
ret void
|
|
|
|
}
|
2014-05-10 00:42:22 +08:00
|
|
|
|
2015-08-08 04:18:34 +08:00
|
|
|
; Test moving an SMRD with an immediate offset to the VALU
|
2014-05-10 00:42:22 +08:00
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu2:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16{{$}}
|
|
|
|
; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(4)* %in) #1 {
|
2014-05-10 00:42:22 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:32 +08:00
|
|
|
%tmp1 = add i32 %tmp, 4
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(4)* %in, i32 %tmp, i32 4
|
|
|
|
%tmp3 = load i32, i32 addrspace(4)* %tmp2
|
2015-09-29 04:54:32 +08:00
|
|
|
store i32 %tmp3, i32 addrspace(1)* %out
|
2014-05-10 00:42:22 +08:00
|
|
|
ret void
|
|
|
|
}
|
2014-08-22 04:41:00 +08:00
|
|
|
|
2015-09-29 04:54:46 +08:00
|
|
|
; Use a big offset that will use the SMRD literal offset on CI
|
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4e20{{$}}
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: buffer_store_dword
|
|
|
|
; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
|
2016-02-13 01:57:54 +08:00
|
|
|
; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu_ci_offset(i32 addrspace(1)* %out, i32 addrspace(4)* %in, i32 %c) #1 {
|
2015-09-29 04:54:46 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr i32, i32 addrspace(4)* %in, i32 %tmp
|
|
|
|
%tmp3 = getelementptr i32, i32 addrspace(4)* %tmp2, i32 5000
|
|
|
|
%tmp4 = load i32, i32 addrspace(4)* %tmp3
|
2015-09-29 04:54:46 +08:00
|
|
|
%tmp5 = add i32 %tmp4, %c
|
|
|
|
store i32 %tmp5, i32 addrspace(1)* %out
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x2:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
; GCN-NOHSA: s_mov_b32 [[OFFSET:s[0-9]+]], 0x9c40{{$}}
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx2
|
|
|
|
; GCN-HSA: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu_ci_offset_x2(i64 addrspace(1)* %out, i64 addrspace(4)* %in, i64 %c) #1 {
|
2015-09-29 04:54:46 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr i64, i64 addrspace(4)* %in, i32 %tmp
|
|
|
|
%tmp3 = getelementptr i64, i64 addrspace(4)* %tmp2, i32 5000
|
|
|
|
%tmp4 = load i64, i64 addrspace(4)* %tmp3
|
2015-09-29 04:54:46 +08:00
|
|
|
%tmp5 = or i64 %tmp4, %c
|
|
|
|
store i64 %tmp5, i64 addrspace(1)* %out
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x4:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4d20{{$}}
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu_ci_offset_x4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(4)* %in, <4 x i32> %c) #1 {
|
2015-09-29 04:54:46 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %in, i32 %tmp
|
|
|
|
%tmp3 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %tmp2, i32 1234
|
|
|
|
%tmp4 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp3
|
2015-09-29 04:54:46 +08:00
|
|
|
%tmp5 = or <4 x i32> %tmp4, %c
|
|
|
|
store <4 x i32> %tmp5, <4 x i32> addrspace(1)* %out
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
; Original scalar load uses SGPR offset on SI and 32-bit literal on
|
|
|
|
; CI.
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x8:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x9a40{{$}}
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
2017-09-20 04:54:38 +08:00
|
|
|
; GCN-NOHSA: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x9a50{{$}}
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
|
2016-08-30 03:42:52 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
|
2016-01-05 11:40:16 +08:00
|
|
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu_ci_offset_x8(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(4)* %in, <8 x i32> %c) #1 {
|
2015-09-29 04:54:46 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %in, i32 %tmp
|
|
|
|
%tmp3 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %tmp2, i32 1234
|
|
|
|
%tmp4 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp3
|
2015-09-29 04:54:46 +08:00
|
|
|
%tmp5 = or <8 x i32> %tmp4, %c
|
|
|
|
store <8 x i32> %tmp5, <8 x i32> addrspace(1)* %out
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2015-09-29 04:54:52 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16:
|
|
|
|
|
2016-04-14 00:18:41 +08:00
|
|
|
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
|
|
|
|
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
|
|
|
|
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}}
|
|
|
|
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
|
|
|
|
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}}
|
|
|
|
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}}
|
|
|
|
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}}
|
|
|
|
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}}
|
2016-01-05 11:40:16 +08:00
|
|
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2015-11-24 20:05:03 +08:00
|
|
|
|
|
|
|
; GCN: s_endpgm
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu_ci_offset_x16(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(4)* %in, <16 x i32> %c) #1 {
|
2015-09-29 04:54:52 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr <16 x i32>, <16 x i32> addrspace(4)* %in, i32 %tmp
|
|
|
|
%tmp3 = getelementptr <16 x i32>, <16 x i32> addrspace(4)* %tmp2, i32 1234
|
|
|
|
%tmp4 = load <16 x i32>, <16 x i32> addrspace(4)* %tmp3
|
2015-09-29 04:54:52 +08:00
|
|
|
%tmp5 = or <16 x i32> %tmp4, %c
|
|
|
|
store <16 x i32> %tmp5, <16 x i32> addrspace(1)* %out
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2015-09-29 04:54:38 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu2_salu_user:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dword [[MOVED:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
|
|
|
|
; GCN-HSA: flat_load_dword [[MOVED:v[0-9]+]], v[{{[0-9+:[0-9]+}}]
|
2015-09-29 04:54:38 +08:00
|
|
|
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]]
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_store_dword [[ADD]]
|
2016-02-13 01:57:54 +08:00
|
|
|
; GCN-HSA: flat_store_dword {{.*}}, [[ADD]]
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu2_salu_user(i32 addrspace(1)* %out, [8 x i32] addrspace(4)* %in, i32 %a) #1 {
|
2015-09-29 04:54:38 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:38 +08:00
|
|
|
%tmp1 = add i32 %tmp, 4
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(4)* %in, i32 %tmp, i32 4
|
|
|
|
%tmp3 = load i32, i32 addrspace(4)* %tmp2
|
2015-09-29 04:54:38 +08:00
|
|
|
%tmp4 = add i32 %tmp3, %a
|
|
|
|
store i32 %tmp4, i32 addrspace(1)* %out
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
|
|
|
|
; GCN-HSA flat_load_dword v{{[0-9]}}, v{{[0-9]+:[0-9]+}}
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(4)* %in) #1 {
|
2015-08-08 04:18:34 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:32 +08:00
|
|
|
%tmp1 = add i32 %tmp, 4
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(4)* %in, i32 %tmp, i32 255
|
|
|
|
%tmp3 = load i32, i32 addrspace(4)* %tmp2
|
2015-09-29 04:54:32 +08:00
|
|
|
store i32 %tmp3, i32 addrspace(1)* %out
|
2015-08-08 04:18:34 +08:00
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu2_mubuf_offset:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1024{{$}}
|
|
|
|
; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}]
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(4)* %in) #1 {
|
2015-08-08 04:18:34 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:32 +08:00
|
|
|
%tmp1 = add i32 %tmp, 4
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(4)* %in, i32 %tmp, i32 256
|
|
|
|
%tmp3 = load i32, i32 addrspace(4)* %tmp2
|
2015-09-29 04:54:32 +08:00
|
|
|
store i32 %tmp3, i32 addrspace(1)* %out
|
2015-08-08 04:18:34 +08:00
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}s_load_imm_v8i32:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
|
2014-08-22 04:41:00 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
|
|
|
|
%tmp2 = bitcast i32 addrspace(4)* %tmp1 to <8 x i32> addrspace(4)*
|
|
|
|
%tmp3 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp2, align 4
|
2014-08-22 04:41:00 +08:00
|
|
|
store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2015-09-29 04:54:38 +08:00
|
|
|
; GCN-LABEL: {{^}}s_load_imm_v8i32_salu_user:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: buffer_store_dword
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @s_load_imm_v8i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
|
2015-09-29 04:54:38 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
|
|
|
|
%tmp2 = bitcast i32 addrspace(4)* %tmp1 to <8 x i32> addrspace(4)*
|
|
|
|
%tmp3 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp2, align 4
|
2015-09-29 04:54:38 +08:00
|
|
|
|
|
|
|
%elt0 = extractelement <8 x i32> %tmp3, i32 0
|
|
|
|
%elt1 = extractelement <8 x i32> %tmp3, i32 1
|
|
|
|
%elt2 = extractelement <8 x i32> %tmp3, i32 2
|
|
|
|
%elt3 = extractelement <8 x i32> %tmp3, i32 3
|
|
|
|
%elt4 = extractelement <8 x i32> %tmp3, i32 4
|
|
|
|
%elt5 = extractelement <8 x i32> %tmp3, i32 5
|
|
|
|
%elt6 = extractelement <8 x i32> %tmp3, i32 6
|
|
|
|
%elt7 = extractelement <8 x i32> %tmp3, i32 7
|
|
|
|
|
|
|
|
%add0 = add i32 %elt0, %elt1
|
|
|
|
%add1 = add i32 %add0, %elt2
|
|
|
|
%add2 = add i32 %add1, %elt3
|
|
|
|
%add3 = add i32 %add2, %elt4
|
|
|
|
%add4 = add i32 %add3, %elt5
|
|
|
|
%add5 = add i32 %add4, %elt6
|
|
|
|
%add6 = add i32 %add5, %elt7
|
|
|
|
|
|
|
|
store i32 %add6, i32 addrspace(1)* %out
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}s_load_imm_v16i32:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
|
2014-08-22 04:41:00 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
|
|
|
|
%tmp2 = bitcast i32 addrspace(4)* %tmp1 to <16 x i32> addrspace(4)*
|
|
|
|
%tmp3 = load <16 x i32>, <16 x i32> addrspace(4)* %tmp2, align 4
|
2014-08-22 04:41:00 +08:00
|
|
|
store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
|
|
|
|
ret void
|
|
|
|
}
|
2015-09-29 04:54:32 +08:00
|
|
|
|
2015-09-29 04:54:38 +08:00
|
|
|
; GCN-LABEL: {{^}}s_load_imm_v16i32_salu_user:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
; GCN-NOHSA: buffer_store_dword
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_kernel void @s_load_imm_v16i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
|
2015-09-29 04:54:38 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
|
|
|
|
%tmp2 = bitcast i32 addrspace(4)* %tmp1 to <16 x i32> addrspace(4)*
|
|
|
|
%tmp3 = load <16 x i32>, <16 x i32> addrspace(4)* %tmp2, align 4
|
2015-09-29 04:54:38 +08:00
|
|
|
|
|
|
|
%elt0 = extractelement <16 x i32> %tmp3, i32 0
|
|
|
|
%elt1 = extractelement <16 x i32> %tmp3, i32 1
|
|
|
|
%elt2 = extractelement <16 x i32> %tmp3, i32 2
|
|
|
|
%elt3 = extractelement <16 x i32> %tmp3, i32 3
|
|
|
|
%elt4 = extractelement <16 x i32> %tmp3, i32 4
|
|
|
|
%elt5 = extractelement <16 x i32> %tmp3, i32 5
|
|
|
|
%elt6 = extractelement <16 x i32> %tmp3, i32 6
|
|
|
|
%elt7 = extractelement <16 x i32> %tmp3, i32 7
|
|
|
|
%elt8 = extractelement <16 x i32> %tmp3, i32 8
|
|
|
|
%elt9 = extractelement <16 x i32> %tmp3, i32 9
|
|
|
|
%elt10 = extractelement <16 x i32> %tmp3, i32 10
|
|
|
|
%elt11 = extractelement <16 x i32> %tmp3, i32 11
|
|
|
|
%elt12 = extractelement <16 x i32> %tmp3, i32 12
|
|
|
|
%elt13 = extractelement <16 x i32> %tmp3, i32 13
|
|
|
|
%elt14 = extractelement <16 x i32> %tmp3, i32 14
|
|
|
|
%elt15 = extractelement <16 x i32> %tmp3, i32 15
|
|
|
|
|
|
|
|
%add0 = add i32 %elt0, %elt1
|
|
|
|
%add1 = add i32 %add0, %elt2
|
|
|
|
%add2 = add i32 %add1, %elt3
|
|
|
|
%add3 = add i32 %add2, %elt4
|
|
|
|
%add4 = add i32 %add3, %elt5
|
|
|
|
%add5 = add i32 %add4, %elt6
|
|
|
|
%add6 = add i32 %add5, %elt7
|
|
|
|
%add7 = add i32 %add6, %elt8
|
|
|
|
%add8 = add i32 %add7, %elt9
|
|
|
|
%add9 = add i32 %add8, %elt10
|
|
|
|
%add10 = add i32 %add9, %elt11
|
|
|
|
%add11 = add i32 %add10, %elt12
|
|
|
|
%add12 = add i32 %add11, %elt13
|
|
|
|
%add13 = add i32 %add12, %elt14
|
|
|
|
%add14 = add i32 %add13, %elt15
|
|
|
|
|
|
|
|
store i32 %add14, i32 addrspace(1)* %out
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2016-02-13 07:45:29 +08:00
|
|
|
; Make sure we legalize vopc operands after moving an sopc to the value.
|
|
|
|
|
|
|
|
; {{^}}sopc_vopc_legalize_bug:
|
|
|
|
; GCN: s_load_dword [[SGPR:s[0-9]+]]
|
|
|
|
; GCN: v_cmp_le_u32_e32 vcc, [[SGPR]], v{{[0-9]+}}
|
|
|
|
; GCN: s_and_b64 vcc, exec, vcc
|
|
|
|
; GCN: s_cbranch_vccnz [[EXIT:[A-Z0-9_]+]]
|
|
|
|
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
|
|
|
; GCN-NOHSA: buffer_store_dword [[ONE]]
|
|
|
|
; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[ONE]]
|
Codegen: Make chains from trellis-shaped CFGs
Lay out trellis-shaped CFGs optimally.
A trellis of the shape below:
A B
|\ /|
| \ / |
| X |
| / \ |
|/ \|
C D
would be laid out A; B->C ; D by the current layout algorithm. Now we identify
trellises and lay them out either A->C; B->D or A->D; B->C. This scales with an
increasing number of predecessors. A trellis is a a group of 2 or more
predecessor blocks that all have the same successors.
because of this we can tail duplicate to extend existing trellises.
As an example consider the following CFG:
B D F H
/ \ / \ / \ / \
A---C---E---G---Ret
Where A,C,E,G are all small (Currently 2 instructions).
The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.
The current code will copy C into B, E into D and G into F and yield the layout
A,C,B(C),E,D(E),F(G),G,H,ret
define void @straight_test(i32 %tag) {
entry:
br label %test1
test1: ; A
%tagbit1 = and i32 %tag, 1
%tagbit1eq0 = icmp eq i32 %tagbit1, 0
br i1 %tagbit1eq0, label %test2, label %optional1
optional1: ; B
call void @a()
br label %test2
test2: ; C
%tagbit2 = and i32 %tag, 2
%tagbit2eq0 = icmp eq i32 %tagbit2, 0
br i1 %tagbit2eq0, label %test3, label %optional2
optional2: ; D
call void @b()
br label %test3
test3: ; E
%tagbit3 = and i32 %tag, 4
%tagbit3eq0 = icmp eq i32 %tagbit3, 0
br i1 %tagbit3eq0, label %test4, label %optional3
optional3: ; F
call void @c()
br label %test4
test4: ; G
%tagbit4 = and i32 %tag, 8
%tagbit4eq0 = icmp eq i32 %tagbit4, 0
br i1 %tagbit4eq0, label %exit, label %optional4
optional4: ; H
call void @d()
br label %exit
exit:
ret void
}
here is the layout after D27742:
straight_test: # @straight_test
; ... Prologue elided
; BB#0: # %entry ; A (merged with test1)
; ... More prologue elided
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_2
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_3
b .LBB0_4
.LBB0_2: # %optional1 ; B (copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_4
.LBB0_3: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_5
b .LBB0_6
.LBB0_4: # %optional2 ; D (copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_5: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
b .LBB0_7
.LBB0_6: # %optional3 ; F (copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit ; Ret
ld 30, 96(1) # 8-byte Folded Reload
addi 1, 1, 112
ld 0, 16(1)
mtlr 0
blr
The tail-duplication has produced some benefit, but it has also produced a
trellis which is not laid out optimally. With this patch, we improve the layouts
of such trellises, and decrease the cost calculation for tail-duplication
accordingly.
This patch produces the layout A,C,E,G,B,D,F,H,Ret. This layout does have
back edges, which is a negative, but it has a bigger compensating
positive, which is that it handles the case where there are long strings
of skipped blocks much better than the original layout. Both layouts
handle runs of executed blocks equally well. Branch prediction also
improves if there is any correlation between subsequent optional blocks.
Here is the resulting concrete layout:
straight_test: # @straight_test
; BB#0: # %entry ; A (merged with test1)
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_4
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_5
.LBB0_2: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_3: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
bne 0, .LBB0_7
b .LBB0_8
.LBB0_4: # %optional1 ; B (Copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_2
.LBB0_5: # %optional2 ; D (Copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_3
.LBB0_6: # %optional3 ; F (Copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit
Differential Revision: https://reviews.llvm.org/D28522
llvm-svn: 295223
2017-02-16 03:49:14 +08:00
|
|
|
; GCN: {{^}}[[EXIT]]:
|
2016-02-13 07:45:29 +08:00
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @sopc_vopc_legalize_bug(i32 %cond, i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
|
2016-02-13 07:45:29 +08:00
|
|
|
bb3: ; preds = %bb2
|
|
|
|
%tmp0 = bitcast i32 %cond to float
|
|
|
|
%tmp1 = fadd float %tmp0, 2.500000e-01
|
|
|
|
%tmp2 = bitcast float %tmp1 to i32
|
|
|
|
%tmp3 = icmp ult i32 %tmp2, %cond
|
|
|
|
br i1 %tmp3, label %bb6, label %bb7
|
|
|
|
|
|
|
|
bb6:
|
|
|
|
store i32 1, i32 addrspace(1)* %out
|
|
|
|
br label %bb7
|
|
|
|
|
|
|
|
bb7: ; preds = %bb3
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2016-11-12 07:35:42 +08:00
|
|
|
; GCN-LABEL: {{^}}phi_visit_order:
|
|
|
|
; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, 1, v{{[0-9]+}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @phi_visit_order() {
|
2016-11-12 07:35:42 +08:00
|
|
|
bb:
|
|
|
|
br label %bb1
|
|
|
|
|
|
|
|
bb1:
|
|
|
|
%tmp = phi i32 [ 0, %bb ], [ %tmp5, %bb4 ]
|
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
|
%cnd = icmp eq i32 %tid, 0
|
|
|
|
br i1 %cnd, label %bb4, label %bb2
|
|
|
|
|
|
|
|
bb2:
|
|
|
|
%tmp3 = add nsw i32 %tmp, 1
|
|
|
|
br label %bb4
|
|
|
|
|
|
|
|
bb4:
|
|
|
|
%tmp5 = phi i32 [ %tmp3, %bb2 ], [ %tmp, %bb1 ]
|
|
|
|
br label %bb1
|
|
|
|
}
|
|
|
|
|
2016-12-07 05:13:30 +08:00
|
|
|
; GCN-LABEL: {{^}}phi_imm_in_sgprs
|
|
|
|
; GCN: s_movk_i32 [[A:s[0-9]+]], 0x400
|
|
|
|
; GCN: s_movk_i32 [[B:s[0-9]+]], 0x400
|
|
|
|
; GCN: [[LOOP_LABEL:[0-9a-zA-Z_]+]]:
|
|
|
|
; GCN: s_xor_b32 [[B]], [[B]], [[A]]
|
|
|
|
; GCN: s_cbranch_scc{{[01]}} [[LOOP_LABEL]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @phi_imm_in_sgprs(i32 addrspace(3)* %out, i32 %cond) {
|
2016-12-07 05:13:30 +08:00
|
|
|
entry:
|
|
|
|
br label %loop
|
|
|
|
|
|
|
|
loop:
|
|
|
|
%i = phi i32 [0, %entry], [%i.add, %loop]
|
|
|
|
%offset = phi i32 [1024, %entry], [%offset.xor, %loop]
|
|
|
|
%offset.xor = xor i32 %offset, 1024
|
|
|
|
%offset.i = add i32 %offset.xor, %i
|
|
|
|
%ptr = getelementptr i32, i32 addrspace(3)* %out, i32 %offset.i
|
|
|
|
store i32 0, i32 addrspace(3)* %ptr
|
|
|
|
%i.add = add i32 %i, 1
|
|
|
|
%cmp = icmp ult i32 %i.add, %cond
|
|
|
|
br i1 %cmp, label %loop, label %exit
|
|
|
|
|
|
|
|
exit:
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
attributes #0 = { nounwind readnone }
|
|
|
|
attributes #1 = { nounwind }
|