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llvm-project/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll

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With the fix in r138164: "Add <imp-def> operands to QQ and QQQQ stack loads." -verify-machineinstrs can be enabled for this test case. llvm-svn: 138171
2011-08-20 08:34:45 +08:00
; RUN: llc %s -mtriple=thumbv7-apple-darwin -verify-machineinstrs -mcpu=cortex-a9 -O0 -o -
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. Therefore, rather then generate a pseudo instruction, which is later expanded, generate the necessary instructions in place. llvm-svn: 138163
2011-08-20 08:17:25 +08:00
; Make sure that the VMOVQQQQ pseudo instruction is handled properly
; by codegen.
Expand VMOVQQQQ pseudo instructions. Apparently we never added code to expand these pseudo instructions, and in over a year, no one has noticed. Our register allocator must be awesome! llvm-svn: 137551
2011-08-13 13:14:55 +08:00
define void @test_vmovqqqq_pseudo() nounwind ssp {
entry:
%vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2)
store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef
ret void
}
declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly