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llvm-project/llvm/test/MC/ARM/thumb-hints.s

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ARM: allow cortex-m0 to use hint instructions The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097
2013-10-07 19:10:47 +08:00
@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s
@ RUN: llvm-mc -triple=thumbv6-apple-darwin -mcpu=cortex-m0 -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s > %t 2> %t2
@ RUN: FileCheck %s --check-prefix=CHECK-EVIL-PRE-UAL < %t
@ RUN: FileCheck %s --check-prefix CHECK-ERROR < %t2
.syntax unified
nop
yield
wfe
wfi
sev
@ CHECK: nop @ encoding: [0x00,0xbf]
@ CHECK: yield @ encoding: [0x10,0xbf]
@ CHECK: wfe @ encoding: [0x20,0xbf]
@ CHECK: wfi @ encoding: [0x30,0xbf]
@ CHECK: sev @ encoding: [0x40,0xbf]
@ CHECK-EVIL-PRE-UAL: mov r8, r8 @ encoding: [0xc0,0x46]
ARM: permit bare dmb/dsb/isb aliases on Cortex-M0 Cortex-M0 supports these 32-bit instructions despite being Thumb1 only (mostly). We knew about that but not that the aliases without the default "sy" operand were also permitted. llvm-svn: 194094
2013-11-06 05:36:02 +08:00
dmb sy
dmb
dsb sy
dsb
isb sy
isb
@ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
@ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
@ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f]
@ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f]
@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
ARM: allow cortex-m0 to use hint instructions The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097
2013-10-07 19:10:47 +08:00
@ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
@ CHECK-ERROR-NEXT: yield
@ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
@ CHECK-ERROR-NEXT: wfe
@ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
@ CHECK-ERROR-NEXT: wfi
@ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
@ CHECK-ERROR-NEXT: sev
ARM: permit bare dmb/dsb/isb aliases on Cortex-M0 Cortex-M0 supports these 32-bit instructions despite being Thumb1 only (mostly). We knew about that but not that the aliases without the default "sy" operand were also permitted. llvm-svn: 194094
2013-11-06 05:36:02 +08:00
@ CHECK-ERROR: error:
@ CHECK-ERROR-NEXT: dmb sy
@ CHECK-ERROR: error: instruction requires: data-barriers
@ CHECK-ERROR-NEXT: dmb
@ CHECK-ERROR: error:
@ CHECK-ERROR-NEXT: dsb sy
@ CHECK-ERROR: error: instruction requires: data-barriers
@ CHECK-ERROR-NEXT: dsb
@ CHECK-ERROR: error:
@ CHECK-ERROR-NEXT: isb sy
@ CHECK-ERROR: error: instruction requires: data-barriers
@ CHECK-ERROR-NEXT: isb