2010-04-22 10:35:46 +08:00
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|
// RUN: %clang_cc1 -emit-llvm -triple x86_64 -O3 -o %t.opt.ll %s \
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// RUN: -fdump-record-layouts 2> %t.dump.txt
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// RUN: FileCheck -check-prefix=CHECK-RECORD < %t.dump.txt %s
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// RUN: FileCheck -check-prefix=CHECK-OPT < %t.opt.ll %s
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IRgen: (Reapply 101222, with fixes) Move EmitStoreThroughBitfieldLValue to use new CGBitfieldInfo::AccessInfo decomposition, instead of computing the access policy itself.
- Sadly, this doesn't seem to give any .ll size win so far. It is possible to make this routine significantly smarter & avoid various shifting, masking, and zext/sext, but I'm not really convinced it is worth it. It is tricky, and this is really instcombine's job.
- No intended functionality change; the test case is just to increase coverage & serves as a demo file, it worked before this commit.
The new fixes from r101222 are:
1. The shift to the target position needs to occur after the value is extended to the correct size. This broke Clang bootstrap, among other things no doubt.
2. Swap the order of arguments to OR, to get a tad more constant folding.
llvm-svn: 101339
2010-04-15 11:47:33 +08:00
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|
/****/
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2010-04-22 10:35:46 +08:00
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// Check that we don't read off the end a packed 24-bit structure.
|
IRgen: (Reapply 101222, with fixes) Move EmitStoreThroughBitfieldLValue to use new CGBitfieldInfo::AccessInfo decomposition, instead of computing the access policy itself.
- Sadly, this doesn't seem to give any .ll size win so far. It is possible to make this routine significantly smarter & avoid various shifting, masking, and zext/sext, but I'm not really convinced it is worth it. It is tricky, and this is really instcombine's job.
- No intended functionality change; the test case is just to increase coverage & serves as a demo file, it worked before this commit.
The new fixes from r101222 are:
1. The shift to the target position needs to occur after the value is extended to the correct size. This broke Clang bootstrap, among other things no doubt.
2. Swap the order of arguments to OR, to get a tad more constant folding.
llvm-svn: 101339
2010-04-15 11:47:33 +08:00
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|
|
// PR6176
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2010-04-22 10:35:46 +08:00
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// CHECK-RECORD: *** Dumping IRgen Record Layout
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// CHECK-RECORD: Record: struct s0
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// CHECK-RECORD: Layout: <CGRecordLayout
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// CHECK-RECORD: LLVMType:<{ [3 x i8] }>
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// CHECK-RECORD: ContainsPointerToDataMember:0
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// CHECK-RECORD: BitFields:[
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// CHECK-RECORD: <CGBitFieldInfo Size:24 IsSigned:1
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// CHECK-RECORD: NumComponents:2 Components: [
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// CHECK-RECORD: <AccessInfo FieldIndex:0 FieldByteOffset:0 FieldBitStart:0 AccessWidth:16
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2010-04-22 11:17:04 +08:00
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// CHECK-RECORD: AccessAlignment:1 TargetBitOffset:0 TargetBitWidth:16>
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2010-04-22 10:35:46 +08:00
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// CHECK-RECORD: <AccessInfo FieldIndex:0 FieldByteOffset:2 FieldBitStart:0 AccessWidth:8
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2010-04-22 11:17:04 +08:00
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|
// CHECK-RECORD: AccessAlignment:1 TargetBitOffset:16 TargetBitWidth:8>
|
IRgen: (Reapply 101222, with fixes) Move EmitStoreThroughBitfieldLValue to use new CGBitfieldInfo::AccessInfo decomposition, instead of computing the access policy itself.
- Sadly, this doesn't seem to give any .ll size win so far. It is possible to make this routine significantly smarter & avoid various shifting, masking, and zext/sext, but I'm not really convinced it is worth it. It is tricky, and this is really instcombine's job.
- No intended functionality change; the test case is just to increase coverage & serves as a demo file, it worked before this commit.
The new fixes from r101222 are:
1. The shift to the target position needs to occur after the value is extended to the correct size. This broke Clang bootstrap, among other things no doubt.
2. Swap the order of arguments to OR, to get a tad more constant folding.
llvm-svn: 101339
2010-04-15 11:47:33 +08:00
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struct __attribute((packed)) s0 {
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int f0 : 24;
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|
};
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|
|
struct s0 g0 = { 0xdeadbeef };
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int f0_load(struct s0 *a0) {
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int size_check[sizeof(struct s0) == 3 ? 1 : -1];
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return a0->f0;
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|
}
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int f0_store(struct s0 *a0) {
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return (a0->f0 = 1);
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|
}
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int f0_reload(struct s0 *a0) {
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return (a0->f0 += 1);
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}
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// CHECK-OPT: define i64 @test_0()
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// CHECK-OPT: ret i64 1
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// CHECK-OPT: }
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unsigned long long test_0() {
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struct s0 g0 = { 0xdeadbeef };
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unsigned long long res = 0;
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res ^= g0.f0;
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res ^= f0_load(&g0) ^ f0_store(&g0) ^ f0_reload(&g0);
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res ^= g0.f0;
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return res;
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}
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/****/
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// PR5591
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2010-04-22 10:35:46 +08:00
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// CHECK-RECORD: *** Dumping IRgen Record Layout
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// CHECK-RECORD: Record: struct s1
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// CHECK-RECORD: Layout: <CGRecordLayout
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// CHECK-RECORD: LLVMType:<{ [2 x i8], i8 }>
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// CHECK-RECORD: ContainsPointerToDataMember:0
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// CHECK-RECORD: BitFields:[
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// CHECK-RECORD: <CGBitFieldInfo Size:10 IsSigned:1
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// CHECK-RECORD: NumComponents:1 Components: [
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// CHECK-RECORD: <AccessInfo FieldIndex:0 FieldByteOffset:0 FieldBitStart:0 AccessWidth:16
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2010-04-22 11:17:04 +08:00
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// CHECK-RECORD: AccessAlignment:1 TargetBitOffset:0 TargetBitWidth:10>
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2010-04-22 10:35:46 +08:00
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// CHECK-RECORD: ]>
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// CHECK-RECORD: <CGBitFieldInfo Size:10 IsSigned:1
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// CHECK-RECORD: NumComponents:2 Components: [
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// CHECK-RECORD: <AccessInfo FieldIndex:0 FieldByteOffset:0 FieldBitStart:10 AccessWidth:16
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2010-04-22 11:17:04 +08:00
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// CHECK-RECORD: AccessAlignment:1 TargetBitOffset:0 TargetBitWidth:6>
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2010-04-22 10:35:46 +08:00
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// CHECK-RECORD: <AccessInfo FieldIndex:0 FieldByteOffset:2 FieldBitStart:0 AccessWidth:8
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2010-04-22 11:17:04 +08:00
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// CHECK-RECORD: AccessAlignment:1 TargetBitOffset:6 TargetBitWidth:4>
|
2010-04-22 10:35:46 +08:00
|
|
|
|
IRgen: (Reapply 101222, with fixes) Move EmitStoreThroughBitfieldLValue to use new CGBitfieldInfo::AccessInfo decomposition, instead of computing the access policy itself.
- Sadly, this doesn't seem to give any .ll size win so far. It is possible to make this routine significantly smarter & avoid various shifting, masking, and zext/sext, but I'm not really convinced it is worth it. It is tricky, and this is really instcombine's job.
- No intended functionality change; the test case is just to increase coverage & serves as a demo file, it worked before this commit.
The new fixes from r101222 are:
1. The shift to the target position needs to occur after the value is extended to the correct size. This broke Clang bootstrap, among other things no doubt.
2. Swap the order of arguments to OR, to get a tad more constant folding.
llvm-svn: 101339
2010-04-15 11:47:33 +08:00
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|
|
#pragma pack(push)
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#pragma pack(1)
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struct __attribute((packed)) s1 {
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signed f0 : 10;
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signed f1 : 10;
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};
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#pragma pack(pop)
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struct s1 g1 = { 0xdeadbeef, 0xdeadbeef };
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int f1_load(struct s1 *a0) {
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int size_check[sizeof(struct s1) == 3 ? 1 : -1];
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return a0->f1;
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}
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int f1_store(struct s1 *a0) {
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return (a0->f1 = 1234);
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}
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int f1_reload(struct s1 *a0) {
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return (a0->f1 += 1234);
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}
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// CHECK-OPT: define i64 @test_1()
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// CHECK-OPT: ret i64 210
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// CHECK-OPT: }
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unsigned long long test_1() {
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struct s1 g1 = { 0xdeadbeef, 0xdeadbeef };
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unsigned long long res = 0;
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res ^= g1.f0 ^ g1.f1;
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res ^= f1_load(&g1) ^ f1_store(&g1) ^ f1_reload(&g1);
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res ^= g1.f0 ^ g1.f1;
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return res;
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}
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/****/
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|
2010-04-22 10:35:46 +08:00
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|
// Check that we don't access beyond the bounds of a union.
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//
|
IRgen: (Reapply 101222, with fixes) Move EmitStoreThroughBitfieldLValue to use new CGBitfieldInfo::AccessInfo decomposition, instead of computing the access policy itself.
- Sadly, this doesn't seem to give any .ll size win so far. It is possible to make this routine significantly smarter & avoid various shifting, masking, and zext/sext, but I'm not really convinced it is worth it. It is tricky, and this is really instcombine's job.
- No intended functionality change; the test case is just to increase coverage & serves as a demo file, it worked before this commit.
The new fixes from r101222 are:
1. The shift to the target position needs to occur after the value is extended to the correct size. This broke Clang bootstrap, among other things no doubt.
2. Swap the order of arguments to OR, to get a tad more constant folding.
llvm-svn: 101339
2010-04-15 11:47:33 +08:00
|
|
|
// PR5567
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|
2010-04-22 10:35:46 +08:00
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|
// CHECK-RECORD: *** Dumping IRgen Record Layout
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|
// CHECK-RECORD: Record: union u2
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|
// CHECK-RECORD: Layout: <CGRecordLayout
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// CHECK-RECORD: LLVMType:<{ i8 }>
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// CHECK-RECORD: ContainsPointerToDataMember:0
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// CHECK-RECORD: BitFields:[
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// CHECK-RECORD: <CGBitFieldInfo Size:3 IsSigned:0
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// CHECK-RECORD: NumComponents:1 Components: [
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// CHECK-RECORD: <AccessInfo FieldIndex:0 FieldByteOffset:0 FieldBitStart:0 AccessWidth:8
|
2010-04-22 11:17:04 +08:00
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|
|
// CHECK-RECORD: AccessAlignment:1 TargetBitOffset:0 TargetBitWidth:3>
|
2010-04-22 10:35:46 +08:00
|
|
|
|
|
|
|
union __attribute__((packed)) u2 {
|
IRgen: (Reapply 101222, with fixes) Move EmitStoreThroughBitfieldLValue to use new CGBitfieldInfo::AccessInfo decomposition, instead of computing the access policy itself.
- Sadly, this doesn't seem to give any .ll size win so far. It is possible to make this routine significantly smarter & avoid various shifting, masking, and zext/sext, but I'm not really convinced it is worth it. It is tricky, and this is really instcombine's job.
- No intended functionality change; the test case is just to increase coverage & serves as a demo file, it worked before this commit.
The new fixes from r101222 are:
1. The shift to the target position needs to occur after the value is extended to the correct size. This broke Clang bootstrap, among other things no doubt.
2. Swap the order of arguments to OR, to get a tad more constant folding.
llvm-svn: 101339
2010-04-15 11:47:33 +08:00
|
|
|
unsigned long long f0 : 3;
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|
|
};
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|
|
union u2 g2 = { 0xdeadbeef };
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|
int f2_load(union u2 *a0) {
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|
|
return a0->f0;
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|
}
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int f2_store(union u2 *a0) {
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|
|
return (a0->f0 = 1234);
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|
|
}
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int f2_reload(union u2 *a0) {
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|
return (a0->f0 += 1234);
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}
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// CHECK-OPT: define i64 @test_2()
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// CHECK-OPT: ret i64 2
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// CHECK-OPT: }
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unsigned long long test_2() {
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union u2 g2 = { 0xdeadbeef };
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unsigned long long res = 0;
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res ^= g2.f0;
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res ^= f2_load(&g2) ^ f2_store(&g2) ^ f2_reload(&g2);
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|
res ^= g2.f0;
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|
return res;
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}
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/***/
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|
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// PR5039
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struct s3 {
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long long f0 : 32;
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long long f1 : 32;
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};
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struct s3 g3 = { 0xdeadbeef, 0xdeadbeef };
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int f3_load(struct s3 *a0) {
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a0->f0 = 1;
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|
|
return a0->f0;
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|
}
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|
int f3_store(struct s3 *a0) {
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|
a0->f0 = 1;
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|
return (a0->f0 = 1234);
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|
}
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|
int f3_reload(struct s3 *a0) {
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|
a0->f0 = 1;
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|
return (a0->f0 += 1234);
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}
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// CHECK-OPT: define i64 @test_3()
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// CHECK-OPT: ret i64 -559039940
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// CHECK-OPT: }
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unsigned long long test_3() {
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|
struct s3 g3 = { 0xdeadbeef, 0xdeadbeef };
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unsigned long long res = 0;
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res ^= g3.f0 ^ g3.f1;
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res ^= f3_load(&g3) ^ f3_store(&g3) ^ f3_reload(&g3);
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res ^= g3.f0 ^ g3.f1;
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return res;
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|
}
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|
/***/
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// This is a case where the bitfield access will straddle an alignment boundary
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|
// of its underlying type.
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|
struct s4 {
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unsigned f0 : 16;
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unsigned f1 : 28 __attribute__ ((packed));
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|
};
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|
struct s4 g4 = { 0xdeadbeef, 0xdeadbeef };
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int f4_load(struct s4 *a0) {
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|
return a0->f0 ^ a0->f1;
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|
}
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int f4_store(struct s4 *a0) {
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|
return (a0->f0 = 1234) ^ (a0->f1 = 5678);
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|
}
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|
int f4_reload(struct s4 *a0) {
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|
|
return (a0->f0 += 1234) ^ (a0->f1 += 5678);
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|
}
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|
|
// CHECK-OPT: define i64 @test_4()
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|
|
// CHECK-OPT: ret i64 4860
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|
// CHECK-OPT: }
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|
|
unsigned long long test_4() {
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|
|
|
struct s4 g4 = { 0xdeadbeef, 0xdeadbeef };
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|
|
unsigned long long res = 0;
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|
|
res ^= g4.f0 ^ g4.f1;
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|
|
res ^= f4_load(&g4) ^ f4_store(&g4) ^ f4_reload(&g4);
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|
|
res ^= g4.f0 ^ g4.f1;
|
|
|
|
return res;
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|
|
|
}
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|
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|
|
|
|
|
/***/
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|
|
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|
|
|
struct s5 {
|
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|
|
unsigned f0 : 2;
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|
|
_Bool f1 : 1;
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|
|
_Bool f2 : 1;
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|
|
|
};
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|
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|
|
struct s5 g5 = { 0xdeadbeef, 0xdeadbeef };
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|
|
|
|
|
|
int f5_load(struct s5 *a0) {
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|
|
|
return a0->f0 ^ a0->f1;
|
|
|
|
}
|
|
|
|
int f5_store(struct s5 *a0) {
|
|
|
|
return (a0->f0 = 0xF) ^ (a0->f1 = 0xF) ^ (a0->f2 = 0xF);
|
|
|
|
}
|
|
|
|
int f5_reload(struct s5 *a0) {
|
|
|
|
return (a0->f0 += 0xF) ^ (a0->f1 += 0xF) ^ (a0->f2 += 0xF);
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|
|
|
}
|
|
|
|
|
|
|
|
// CHECK-OPT: define i64 @test_5()
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|
|
|
// CHECK-OPT: ret i64 2
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|
|
|
// CHECK-OPT: }
|
|
|
|
unsigned long long test_5() {
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|
|
|
struct s5 g5 = { 0xdeadbeef, 0xdeadbeef, 0xdeadbeef };
|
|
|
|
unsigned long long res = 0;
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|
|
|
res ^= g5.f0 ^ g5.f1 ^ g5.f2;
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|
|
res ^= f5_load(&g5) ^ f5_store(&g5) ^ f5_reload(&g5);
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|
|
|
res ^= g5.f0 ^ g5.f1 ^ g5.f2;
|
|
|
|
return res;
|
|
|
|
}
|
2010-04-18 05:52:22 +08:00
|
|
|
|
2010-04-21 01:52:30 +08:00
|
|
|
/***/
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|
|
|
|
|
|
|
struct s6 {
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|
|
|
_Bool f0 : 2;
|
2010-04-18 05:52:22 +08:00
|
|
|
};
|
|
|
|
|
2010-04-21 01:52:30 +08:00
|
|
|
struct s6 g6 = { 0xF };
|
|
|
|
|
|
|
|
int f6_load(struct s6 *a0) {
|
|
|
|
return a0->f0;
|
|
|
|
}
|
|
|
|
int f6_store(struct s6 *a0) {
|
|
|
|
return a0->f0 = 0x0;
|
|
|
|
}
|
|
|
|
int f6_reload(struct s6 *a0) {
|
|
|
|
return (a0->f0 += 0xF);
|
|
|
|
}
|
|
|
|
|
2010-04-18 05:52:22 +08:00
|
|
|
// CHECK-OPT: define zeroext i1 @test_6()
|
2010-04-21 01:52:30 +08:00
|
|
|
// CHECK-OPT: ret i1 true
|
2010-04-18 05:52:22 +08:00
|
|
|
// CHECK-OPT: }
|
|
|
|
_Bool test_6() {
|
2010-04-21 01:52:30 +08:00
|
|
|
struct s6 g6 = { 0xF };
|
|
|
|
unsigned long long res = 0;
|
|
|
|
res ^= g6.f0;
|
|
|
|
res ^= f6_load(&g6);
|
|
|
|
res ^= g6.f0;
|
|
|
|
return res;
|
2010-04-18 05:52:22 +08:00
|
|
|
}
|
2010-04-22 11:17:04 +08:00
|
|
|
|
|
|
|
/***/
|
|
|
|
|
|
|
|
// Check that we compute the best alignment possible for each access.
|
|
|
|
//
|
|
|
|
// CHECK-RECORD: *** Dumping IRgen Record Layout
|
|
|
|
// CHECK-RECORD: Record: struct s7
|
|
|
|
// CHECK-RECORD: Layout: <CGRecordLayout
|
|
|
|
// CHECK-RECORD: LLVMType:{ i32, i32, i32, i8, [3 x i8], [4 x i8], [12 x i8] }
|
|
|
|
// CHECK-RECORD: ContainsPointerToDataMember:0
|
|
|
|
// CHECK-RECORD: BitFields:[
|
|
|
|
// CHECK-RECORD: <CGBitFieldInfo Size:5 IsSigned:1
|
|
|
|
// CHECK-RECORD: NumComponents:1 Components: [
|
|
|
|
// CHECK-RECORD: <AccessInfo FieldIndex:0 FieldByteOffset:12 FieldBitStart:0 AccessWidth:32
|
|
|
|
// CHECK-RECORD: AccessAlignment:4 TargetBitOffset:0 TargetBitWidth:5>
|
|
|
|
// CHECK-RECORD: ]>
|
|
|
|
// CHECK-RECORD: <CGBitFieldInfo Size:29 IsSigned:1
|
|
|
|
// CHECK-RECORD: NumComponents:1 Components: [
|
|
|
|
// CHECK-RECORD: <AccessInfo FieldIndex:0 FieldByteOffset:16 FieldBitStart:0 AccessWidth:32
|
|
|
|
// CHECK-RECORD: AccessAlignment:16 TargetBitOffset:0 TargetBitWidth:29>
|
|
|
|
|
|
|
|
struct __attribute__((aligned(16))) s7 {
|
|
|
|
int a, b, c;
|
|
|
|
int f0 : 5;
|
|
|
|
int f1 : 29;
|
|
|
|
};
|
|
|
|
|
|
|
|
int f7_load(struct s7 *a0) {
|
|
|
|
return a0->f0;
|
|
|
|
}
|