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llvm-project/llvm/test/CodeGen/Thumb2/mve-ctlz.ll

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[ARM] Add patterns for CTLZ on MVE CTLZ intrinsic can use the VCLS instruction on MVE, which produces better results than expanding. llvm-svn: 371999
2019-09-16 23:19:49 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[ARM] Replace arm vendor with none. NFC
2020-04-22 23:33:11 +08:00
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
[ARM] Add patterns for CTLZ on MVE CTLZ intrinsic can use the VCLS instruction on MVE, which produces better results than expanding. llvm-svn: 371999
2019-09-16 23:19:49 +08:00
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){
; CHECK-LABEL: ctlz_2i64_0_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: add.w r1, r1, #32
; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov s6, r1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: add.w r1, r1, #32
; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov s4, r1
; CHECK-NEXT: vldr s5, .LCPI0_0
; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0:
[AsmPrinter] Print FP constant in hexadecimal form instead Printing floating point number in decimal is inconvenient for humans. Verbose asm output will print out floating point values in comments, it helps. But in lots of cases, users still need additional work to covert the decimal back to hex or binary to check the bit patterns, especially when there are small precision difference. Hexadecimal form is one of the supported form in LLVM IR, and easier for debugging. This patch try to print all FP constant in hex form instead. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D73566
2020-02-07 00:12:10 +08:00
; CHECK-NEXT: .long 0x00000000 @ float 0
[ARM] Add patterns for CTLZ on MVE CTLZ intrinsic can use the VCLS instruction on MVE, which produces better results than expanding. llvm-svn: 371999
2019-09-16 23:19:49 +08:00
entry:
%0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0)
ret <2 x i64> %0
}
define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_0_t(<4 x i32> %src){
; CHECK-LABEL: ctlz_4i32_0_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i32 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 0)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_0_t(<8 x i16> %src){
; CHECK-LABEL: ctlz_8i16_0_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 0)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_0_t(<16 x i8> %src){
; CHECK-LABEL: ctlz_16i8_0_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i8 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 0)
ret <16 x i8> %0
}
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_1_t(<2 x i64> %src){
; CHECK-LABEL: ctlz_2i64_1_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: add.w r1, r1, #32
; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov s6, r1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: add.w r1, r1, #32
; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov s4, r1
; CHECK-NEXT: vldr s5, .LCPI4_0
; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI4_0:
[AsmPrinter] Print FP constant in hexadecimal form instead Printing floating point number in decimal is inconvenient for humans. Verbose asm output will print out floating point values in comments, it helps. But in lots of cases, users still need additional work to covert the decimal back to hex or binary to check the bit patterns, especially when there are small precision difference. Hexadecimal form is one of the supported form in LLVM IR, and easier for debugging. This patch try to print all FP constant in hex form instead. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D73566
2020-02-07 00:12:10 +08:00
; CHECK-NEXT: .long 0x00000000 @ float 0
[ARM] Add patterns for CTLZ on MVE CTLZ intrinsic can use the VCLS instruction on MVE, which produces better results than expanding. llvm-svn: 371999
2019-09-16 23:19:49 +08:00
entry:
%0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1)
ret <2 x i64> %0
}
define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_1_t(<4 x i32> %src){
; CHECK-LABEL: ctlz_4i32_1_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i32 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 1)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_1_t(<8 x i16> %src){
; CHECK-LABEL: ctlz_8i16_1_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 1)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_1_t(<16 x i8> %src){
; CHECK-LABEL: ctlz_16i8_1_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i8 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 1)
ret <16 x i8> %0
}
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1)
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1)
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1)