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RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-coalescing -run-pass=simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
---
name: couldnt_join_subrange_implicit_def_pred_block
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: couldnt_join_subrange_implicit_def_pred_block
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: undef %0.sub0:sreg_64_xexec = IMPLICIT_DEF
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: %0.sub1:sreg_64_xexec = COPY %0.sub0
; CHECK: S_BRANCH %bb.2
; CHECK: bb.2:
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
; CHECK: S_ENDPGM 0, implicit %0
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
bb.0:
successors: %bb.1
undef %0.sub0:sreg_64_xexec = IMPLICIT_DEF
bb.1:
successors: %bb.2
%1:sreg_64 = COPY %0:sreg_64_xexec
%0.sub1:sreg_64_xexec = COPY %0.sub0:sreg_64_xexec
S_BRANCH %bb.2
bb.2:
dead %2:sreg_32_xm0 = COPY %0.sub0:sreg_64_xexec
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
S_ENDPGM 0, implicit killed %1
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
...
---
name: couldnt_join_subrange_no_implicit_def_inst
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: couldnt_join_subrange_no_implicit_def_inst
; CHECK: undef %0.sub0:sreg_64 = S_MOV_B32 0
; CHECK: %0.sub1:sreg_64 = COPY %0.sub0
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
; CHECK: S_ENDPGM 0, implicit %0.sub1
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
undef %0.sub0:sreg_64 = S_MOV_B32 0
%1:sreg_64 = COPY %0:sreg_64
%0.sub1:sreg_64 = COPY %0.sub0:sreg_64
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
S_ENDPGM 0, implicit %1.sub1:sreg_64
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
...
---
name: couldnt_join_subrange0
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: couldnt_join_subrange0
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: undef %0.sub1:sreg_64 = S_MOV_B32 -1
; CHECK: bb.1:
; CHECK: %0.sub0:sreg_64 = S_MOV_B32 0
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY %0
; CHECK: dead %0.sub1:sreg_64 = COPY %0.sub0
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
; CHECK: S_ENDPGM 0, implicit [[COPY]].sub1
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
bb.0:
successors: %bb.1
undef %0.sub1:sreg_64 = S_MOV_B32 -1
bb.1:
%0.sub0:sreg_64 = S_MOV_B32 0
%1:sreg_64 = COPY %0:sreg_64
dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
S_ENDPGM 0, implicit %1.sub1:sreg_64
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
...
---
name: lanes_not_tracked_subreg_join_couldnt_join_subrange
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: lanes_not_tracked_subreg_join_couldnt_join_subrange
; CHECK: undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
; CHECK: %0.sub1:sreg_64_xexec = S_MOV_B32 0
; CHECK: S_NOP 0, implicit %0.sub1
; CHECK: S_NOP 0, implicit %0
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
; CHECK: S_ENDPGM 0
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
%1:sreg_64 = COPY %0
%0.sub1:sreg_64_xexec = S_MOV_B32 0
S_NOP 0, implicit %0.sub1
S_NOP 0, implicit %1
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
S_ENDPGM 0
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
...
---
name: couldnt_join_subrange1
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: couldnt_join_subrange1
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
; CHECK: %0.sub1:sreg_64_xexec = COPY %0.sub0
; CHECK: bb.1:
; CHECK: S_NOP 0, implicit %0.sub1
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
; CHECK: S_ENDPGM 0, implicit %0
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
bb.0:
successors: %bb.1
undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
%1:sreg_64 = COPY %0
%0.sub1:sreg_64_xexec = COPY %0.sub0
bb.1:
S_NOP 0, implicit %0.sub1
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
S_ENDPGM 0, implicit %1
RegisterCoalescer: Assume CR_Replace for SubRangeJoin Currently it's possible for following check on V.WriteLanes (which is not really meaningful during SubRangeJoin) to pass for one half of the pair, and then fall through to to one of the impossible or unresolved states. This then fails as inconsistent on the other half. During the main range join, the check between V.WriteLanes and OtherV.ValidLanes must have passed, meaning this should be a CR_Replace. Fixes most of the testcases in bugs 39542 and 39602 llvm-svn: 350678
2019-01-09 07:22:18 +08:00
...