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llvm-project/llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAsse...

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enable PPC register scavenging by default (update tests and remove some FIXMEs) llvm-svn: 145819
2011-12-06 01:55:17 +08:00
; RUN: llc < %s -mtriple=powerpc-apple-darwin
Fix a coalescer bug wrt how dead copy interval is shortened. llvm-svn: 47966
2008-03-06 06:09:42 +08:00
declare i8* @bar(i32)
define void @foo(i8* %pp) nounwind {
entry:
%tmp2 = tail call i8* @bar( i32 14 ) nounwind ; <i8*> [#uses=0]
%tmp28 = bitcast i8* %pp to void ()** ; <void ()**> [#uses=1]
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp38 = load void ()*, void ()** %tmp28, align 4 ; <void ()*> [#uses=2]
Fix a coalescer bug wrt how dead copy interval is shortened. llvm-svn: 47966
2008-03-06 06:09:42 +08:00
br i1 false, label %bb34, label %bb25
bb25: ; preds = %entry
%tmp30 = bitcast void ()* %tmp38 to void (i8*)* ; <void (i8*)*> [#uses=1]
tail call void %tmp30( i8* null ) nounwind
ret void
bb34: ; preds = %entry
tail call void %tmp38( ) nounwind
ret void
}