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llvm-project/llvm/test/CodeGen/AArch64/combine-loads.ll

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[AArch64] Add combine-load test; NFC Problem discovered in https://reviews.llvm.org/D81343
2020-06-08 18:23:20 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O0 -mtriple=aarch64-unknown-unknown | FileCheck %s
define <2 x i64> @z(i64* nocapture nonnull readonly %p) {
; CHECK-LABEL: z:
; CHECK: // %bb.0:
[AArch64][GlobalISel][RegBankSelect] Improve rbs of G_BUILD_VECTOR when fed by fp values. This is actually two changes. One is to avoid copies when fp values are fed into a build_vector, without being able to tell from the opcode. The other is that build_vectors are also marked as only defining FP, since they produce vector results. Differential Revision: https://reviews.llvm.org/D97968
2021-03-05 02:18:31 +08:00
; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: ldr d2, [x0, #8]
[GISel]: Few InsertVecElt combines https://reviews.llvm.org/D88060 This adds the following combines 1) build_vector formation from insert_vec_elts 2) insert_vec_elts (build_vector) -> build_vector
2020-10-29 03:13:35 +08:00
; CHECK-NEXT: // implicit-def: $q0
[AArch64][GlobalISel][RegBankSelect] Improve rbs of G_BUILD_VECTOR when fed by fp values. This is actually two changes. One is to avoid copies when fp values are fed into a build_vector, without being able to tell from the opcode. The other is that build_vectors are also marked as only defining FP, since they produce vector results. Differential Revision: https://reviews.llvm.org/D97968
2021-03-05 02:18:31 +08:00
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: mov v1.16b, v2.16b
; CHECK-NEXT: mov v0.d[1], v1.d[0]
[AArch64] Add combine-load test; NFC Problem discovered in https://reviews.llvm.org/D81343
2020-06-08 18:23:20 +08:00
; CHECK-NEXT: ret
%b = load i64, i64* %p
%p2 = getelementptr i64, i64* %p, i64 1
%bb = load i64, i64* %p2
%r1 = insertelement <2 x i64> zeroinitializer, i64 %b, i32 0
%r2 = insertelement <2 x i64> %r1, i64 %bb, i32 1
ret <2 x i64> %r2
}