2015-01-31 19:17:59 +08:00
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//===-- PPCTargetTransformInfo.h - PPC specific TTI -------------*- C++ -*-===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2015-01-31 19:17:59 +08:00
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// PPC target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H
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#include "PPCTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetLowering.h"
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2015-01-31 19:17:59 +08:00
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namespace llvm {
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class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
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typedef BasicTTIImplBase<PPCTTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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2015-02-01 22:01:15 +08:00
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friend BaseT;
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2015-01-31 19:17:59 +08:00
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const PPCSubtarget *ST;
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const PPCTargetLowering *TLI;
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2015-02-01 22:22:17 +08:00
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const PPCSubtarget *getST() const { return ST; }
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2015-02-01 22:01:15 +08:00
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const PPCTargetLowering *getTLI() const { return TLI; }
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2019-06-07 15:35:30 +08:00
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bool mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo);
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2015-02-01 22:01:15 +08:00
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2015-01-31 19:17:59 +08:00
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public:
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2015-09-17 07:38:13 +08:00
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explicit PPCTTIImpl(const PPCTargetMachine *TM, const Function &F)
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2015-07-09 10:08:42 +08:00
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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2015-01-31 19:17:59 +08:00
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/// \name Scalar TTI Implementations
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/// @{
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using BaseT::getIntImmCost;
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2015-08-06 02:08:10 +08:00
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int getIntImmCost(const APInt &Imm, Type *Ty);
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2015-01-31 19:17:59 +08:00
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2019-12-12 03:54:58 +08:00
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int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty);
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int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty);
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2015-01-31 19:17:59 +08:00
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2017-10-20 02:16:31 +08:00
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unsigned getUserCost(const User *U, ArrayRef<const Value *> Operands);
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2015-01-31 19:17:59 +08:00
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
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2019-06-07 15:35:30 +08:00
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bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
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AssumptionCache &AC,
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TargetLibraryInfo *LibInfo,
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2019-06-19 09:26:31 +08:00
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HardwareLoopInfo &HWLoopInfo);
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2019-07-03 09:49:03 +08:00
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bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,
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DominatorTree *DT, AssumptionCache *AC,
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TargetLibraryInfo *LibInfo);
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[LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.
Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper
Subscribers: jholewinski, arsenm, mzolotukhin, nemanjai, nhaehnle, javed.absar, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D34531
llvm-svn: 306554
2017-06-28 23:53:17 +08:00
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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2015-01-31 19:17:59 +08:00
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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2018-01-31 00:17:22 +08:00
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bool useColdCCForColdCall(Function &F);
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2015-03-07 07:12:04 +08:00
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bool enableAggressiveInterleaving(bool LoopHasReductions);
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2019-06-25 16:04:13 +08:00
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TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
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bool IsZeroCmp) const;
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2015-09-04 08:10:41 +08:00
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bool enableInterleavedAccessVectorization();
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recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure separately in loop-vectorize
In loop-vectorize, interleave count and vector factor depend on target register number. Currently, it does not
estimate different register pressure for different register class separately(especially for scalar type,
float type should not be on the same position with int type), so it's not accurate. Specifically,
it causes too many times interleaving/unrolling, result in too many register spills in loop body and hurting performance.
So we need classify the register classes in IR level, and importantly these are abstract register classes,
and are not the target register class of backend provided in td file. It's used to establish the mapping between
the types of IR values and the number of simultaneous live ranges to which we'd like to limit for some set of those types.
For example, POWER target, register num is special when VSX is enabled. When VSX is enabled, the number of int scalar register is 32(GPR),
float is 64(VSR), but for int and float vector register both are 64(VSR). So there should be 2 kinds of register class when vsx is enabled,
and 3 kinds of register class when VSX is NOT enabled.
It runs on POWER target, it makes big(+~30%) performance improvement in one specific bmk(503.bwaves_r) of spec2017 and no other obvious degressions.
Differential revision: https://reviews.llvm.org/D67148
llvm-svn: 374634
2019-10-12 10:53:04 +08:00
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enum PPCRegisterClass {
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GPRRC, FPRRC, VRRC, VSXRC
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};
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unsigned getNumberOfRegisters(unsigned ClassID) const;
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unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const;
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const char* getRegisterClassName(unsigned ClassID) const;
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Const correctness for TTI::getRegisterBitWidth
Summary: The method TargetTransformInfo::getRegisterBitWidth() is declared const, but the type erasing implementation classes (TargetTransformInfo::Concept & TargetTransformInfo::Model) that were introduced by Chandler in https://reviews.llvm.org/D7293 do not have the method declared const. This is an NFC to tidy up the const consistency between TTI and its implementation.
Reviewers: chandlerc, rnk, reames
Reviewed By: reames
Subscribers: reames, jfb, arsenm, dschuff, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D33903
llvm-svn: 305189
2017-06-12 22:22:21 +08:00
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unsigned getRegisterBitWidth(bool Vector) const;
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2019-10-10 03:51:48 +08:00
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unsigned getCacheLineSize() const override;
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unsigned getPrefetchDistance() const override;
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2015-05-07 01:12:25 +08:00
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unsigned getMaxInterleaveFactor(unsigned VF);
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2019-01-26 09:18:48 +08:00
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int vectorCostAdjustment(int Cost, unsigned Opcode, Type *Ty1, Type *Ty2);
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2015-08-06 02:08:10 +08:00
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int getArithmeticInstrCost(
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2015-01-31 19:17:59 +08:00
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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[X86] updating TTI costs for arithmetic instructions on X86\SLM arch.
updated instructions:
pmulld, pmullw, pmulhw, mulsd, mulps, mulpd, divss, divps, divsd, divpd, addpd and subpd.
special optimization case which replaces pmulld with pmullw\pmulhw\pshuf seq.
In case if the real operands bitwidth <= 16.
Differential Revision: https://reviews.llvm.org/D28104
llvm-svn: 291657
2017-01-11 16:23:37 +08:00
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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[ARM] Teach the Arm cost model that a Shift can be folded into other instructions
This attempts to teach the cost model in Arm that code such as:
%s = shl i32 %a, 3
%a = and i32 %s, %b
Can under Arm or Thumb2 become:
and r0, r1, r2, lsl #3
So the cost of the shift can essentially be free. To do this without
trying to artificially adjust the cost of the "and" instruction, it
needs to get the users of the shl and check if they are a type of
instruction that the shift can be folded into. And so it needs to have
access to the actual instruction in getArithmeticInstrCost, which if
available is added as an extra parameter much like getCastInstrCost.
We otherwise limit it to shifts with a single user, which should
hopefully handle most of the cases. The list of instruction that the
shift can be folded into include ADC, ADD, AND, BIC, CMP, EOR, MVN, ORR,
ORN, RSB, SBC and SUB. This translates to Add, Sub, And, Or, Xor and
ICmp.
Differential Revision: https://reviews.llvm.org/D70966
2019-12-08 23:33:24 +08:00
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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2015-08-06 02:08:10 +08:00
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int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
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2017-04-12 19:49:08 +08:00
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int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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const Instruction *I = nullptr);
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int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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const Instruction *I = nullptr);
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2015-08-06 02:08:10 +08:00
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int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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2019-10-22 23:16:52 +08:00
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int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
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2017-04-12 19:49:08 +08:00
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unsigned AddressSpace, const Instruction *I = nullptr);
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2015-09-04 08:10:41 +08:00
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int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
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unsigned Factor,
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ArrayRef<unsigned> Indices,
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unsigned Alignment,
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2018-10-14 16:50:06 +08:00
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unsigned AddressSpace,
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2018-10-31 17:57:56 +08:00
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bool UseMaskForCond = false,
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bool UseMaskForGaps = false);
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2019-12-18 09:07:18 +08:00
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unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Value*> Args, FastMathFlags FMF, unsigned VF);
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unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Type*> Tys, FastMathFlags FMF,
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unsigned ScalarizationCostPassed = UINT_MAX);
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2015-01-31 19:17:59 +08:00
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/// @}
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};
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} // end namespace llvm
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#endif
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