2017-07-27 07:20:35 +08:00
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//===- HexagonExpandCondsets.cpp ------------------------------------------===//
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2015-07-09 23:40:25 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2015-07-09 23:40:25 +08:00
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//
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//===----------------------------------------------------------------------===//
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2015-03-31 21:35:12 +08:00
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// Replace mux instructions with the corresponding legal instructions.
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// It is meant to work post-SSA, but still on virtual registers. It was
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// originally placed between register coalescing and machine instruction
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// scheduler.
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// In this place in the optimization sequence, live interval analysis had
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// been performed, and the live intervals should be preserved. A large part
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// of the code deals with preserving the liveness information.
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//
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// Liveness tracking aside, the main functionality of this pass is divided
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// into two steps. The first step is to replace an instruction
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2017-11-30 20:12:19 +08:00
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// %0 = C2_mux %1, %2, %3
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2015-03-31 21:35:12 +08:00
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// with a pair of conditional transfers
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2017-11-30 20:12:19 +08:00
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// %0 = A2_tfrt %1, %2
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// %0 = A2_tfrf %1, %3
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2015-03-31 21:35:12 +08:00
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// It is the intention that the execution of this pass could be terminated
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// after this step, and the code generated would be functionally correct.
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//
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2017-11-30 20:12:19 +08:00
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// If the uses of the source values %1 and %2 are kills, and their
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2015-03-31 21:35:12 +08:00
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// definitions are predicable, then in the second step, the conditional
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// transfers will then be rewritten as predicated instructions. E.g.
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2017-11-30 20:12:19 +08:00
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// %0 = A2_or %1, %2
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2017-12-07 18:40:31 +08:00
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// %3 = A2_tfrt %99, killed %0
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2015-03-31 21:35:12 +08:00
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// will be rewritten as
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2017-11-30 20:12:19 +08:00
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// %3 = A2_port %99, %1, %2
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2015-03-31 21:35:12 +08:00
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//
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// This replacement has two variants: "up" and "down". Consider this case:
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2017-11-30 20:12:19 +08:00
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// %0 = A2_or %1, %2
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2015-03-31 21:35:12 +08:00
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// ... [intervening instructions] ...
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2017-12-07 18:40:31 +08:00
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// %3 = A2_tfrt %99, killed %0
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2015-03-31 21:35:12 +08:00
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// variant "up":
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// %3 = A2_port %99, %1, %2
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// ... [intervening instructions, %0->vreg3] ...
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2015-03-31 21:35:12 +08:00
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// [deleted]
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// variant "down":
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// [deleted]
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// ... [intervening instructions] ...
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2017-11-30 20:12:19 +08:00
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// %3 = A2_port %99, %1, %2
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2015-03-31 21:35:12 +08:00
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//
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// Both, one or none of these variants may be valid, and checks are made
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// to rule out inapplicable variants.
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//
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// As an additional optimization, before either of the two steps above is
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// executed, the pass attempts to coalesce the target register with one of
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// the source registers, e.g. given an instruction
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2017-11-30 20:12:19 +08:00
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// %3 = C2_mux %0, %1, %2
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// %3 will be coalesced with either %1 or %2. If this succeeds,
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2015-03-31 21:35:12 +08:00
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// the instruction would then be (for example)
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2017-11-30 20:12:19 +08:00
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// %3 = C2_mux %0, %3, %2
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2015-03-31 21:35:12 +08:00
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// and, under certain circumstances, this could result in only one predicated
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// instruction:
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2017-11-30 20:12:19 +08:00
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// %3 = A2_tfrf %0, %2
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2015-03-31 21:35:12 +08:00
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//
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2016-06-08 20:31:16 +08:00
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// Splitting a definition of a register into two predicated transfers
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// creates a complication in liveness tracking. Live interval computation
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// will see both instructions as actual definitions, and will mark the
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// first one as dead. The definition is not actually dead, and this
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// situation will need to be fixed. For example:
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2017-12-07 18:40:31 +08:00
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// dead %1 = A2_tfrt ... ; marked as dead
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// %1 = A2_tfrf ...
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2016-06-08 20:31:16 +08:00
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//
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// Since any of the individual predicated transfers may end up getting
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// removed (in case it is an identity copy), some pre-existing def may
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// be marked as dead after live interval recomputation:
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2017-12-07 18:40:31 +08:00
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// dead %1 = ... ; marked as dead
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2016-06-08 20:31:16 +08:00
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// ...
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2017-12-07 18:40:31 +08:00
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// %1 = A2_tfrf ... ; if A2_tfrt is removed
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2017-11-30 20:12:19 +08:00
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// This case happens if %1 was used as a source in A2_tfrt, which means
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2016-06-08 20:31:16 +08:00
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// that is it actually live at the A2_tfrf, and so the now dead definition
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2017-11-30 20:12:19 +08:00
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// of %1 will need to be updated to non-dead at some point.
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2016-06-08 20:31:16 +08:00
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//
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// This issue could be remedied by adding implicit uses to the predicated
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// transfers, but this will create a problem with subsequent predication,
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// since the transfers will no longer be possible to reorder. To avoid
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// that, the initial splitting will not add any implicit uses. These
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// implicit uses will be added later, after predication. The extra price,
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// however, is that finding the locations where the implicit uses need
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// to be added, and updating the live ranges will be more involved.
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2016-12-15 06:50:46 +08:00
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#include "HexagonInstrInfo.h"
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2017-09-15 23:46:05 +08:00
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#include "HexagonRegisterInfo.h"
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2016-12-15 06:50:46 +08:00
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#include "llvm/ADT/DenseMap.h"
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2016-06-08 20:31:16 +08:00
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#include "llvm/ADT/SetVector.h"
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2016-12-15 06:50:46 +08:00
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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2015-03-31 21:35:12 +08:00
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#include "llvm/CodeGen/LiveInterval.h"
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2017-12-13 10:51:04 +08:00
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#include "llvm/CodeGen/LiveIntervals.h"
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2016-12-15 06:50:46 +08:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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2016-06-08 20:31:16 +08:00
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#include "llvm/CodeGen/MachineDominators.h"
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2015-03-31 21:35:12 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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2016-12-15 06:50:46 +08:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2015-03-31 21:35:12 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2016-12-15 06:50:46 +08:00
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#include "llvm/CodeGen/MachineOperand.h"
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2015-03-31 21:35:12 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2016-12-15 06:50:46 +08:00
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#include "llvm/CodeGen/SlotIndexes.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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2016-12-15 06:50:46 +08:00
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#include "llvm/IR/DebugLoc.h"
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2017-07-27 07:20:35 +08:00
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#include "llvm/IR/Function.h"
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Sink all InitializePasses.h includes
This file lists every pass in LLVM, and is included by Pass.h, which is
very popular. Every time we add, remove, or rename a pass in LLVM, it
caused lots of recompilation.
I found this fact by looking at this table, which is sorted by the
number of times a file was changed over the last 100,000 git commits
multiplied by the number of object files that depend on it in the
current checkout:
recompiles touches affected_files header
342380 95 3604 llvm/include/llvm/ADT/STLExtras.h
314730 234 1345 llvm/include/llvm/InitializePasses.h
307036 118 2602 llvm/include/llvm/ADT/APInt.h
213049 59 3611 llvm/include/llvm/Support/MathExtras.h
170422 47 3626 llvm/include/llvm/Support/Compiler.h
162225 45 3605 llvm/include/llvm/ADT/Optional.h
158319 63 2513 llvm/include/llvm/ADT/Triple.h
140322 39 3598 llvm/include/llvm/ADT/StringRef.h
137647 59 2333 llvm/include/llvm/Support/Error.h
131619 73 1803 llvm/include/llvm/Support/FileSystem.h
Before this change, touching InitializePasses.h would cause 1345 files
to recompile. After this change, touching it only causes 550 compiles in
an incremental rebuild.
Reviewers: bkramer, asbirlea, bollu, jdoerfert
Differential Revision: https://reviews.llvm.org/D70211
2019-11-14 05:15:01 +08:00
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#include "llvm/InitializePasses.h"
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2017-07-27 07:20:35 +08:00
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#include "llvm/MC/LaneBitmask.h"
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2016-12-15 06:50:46 +08:00
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#include "llvm/Pass.h"
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2015-03-31 21:35:12 +08:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2016-12-15 06:50:46 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2015-03-31 21:35:12 +08:00
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#include "llvm/Support/raw_ostream.h"
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2016-12-15 06:50:46 +08:00
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#include <cassert>
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2016-06-08 20:31:16 +08:00
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#include <iterator>
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#include <set>
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#include <utility>
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2017-07-14 04:26:45 +08:00
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#define DEBUG_TYPE "expand-condsets"
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2015-03-31 21:35:12 +08:00
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using namespace llvm;
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static cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit",
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cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"));
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static cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit",
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cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"));
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namespace llvm {
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2016-12-15 06:50:46 +08:00
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2015-03-31 21:35:12 +08:00
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void initializeHexagonExpandCondsetsPass(PassRegistry&);
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FunctionPass *createHexagonExpandCondsets();
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2016-12-15 06:50:46 +08:00
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} // end namespace llvm
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2015-03-31 21:35:12 +08:00
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namespace {
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2016-12-15 06:50:46 +08:00
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2015-03-31 21:35:12 +08:00
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class HexagonExpandCondsets : public MachineFunctionPass {
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public:
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static char ID;
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2016-12-15 06:50:46 +08:00
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2017-07-27 07:20:35 +08:00
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HexagonExpandCondsets() : MachineFunctionPass(ID) {
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2015-03-31 21:35:12 +08:00
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if (OptCoaLimit.getPosition())
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CoaLimitActive = true, CoaLimit = OptCoaLimit;
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if (OptTfrLimit.getPosition())
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TfrLimitActive = true, TfrLimit = OptTfrLimit;
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initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
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}
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2016-10-01 10:56:57 +08:00
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StringRef getPassName() const override { return "Hexagon Expand Condsets"; }
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2016-12-15 06:50:46 +08:00
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2016-06-08 20:31:16 +08:00
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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2015-03-31 21:35:12 +08:00
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreserved<SlotIndexes>();
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2016-06-08 20:31:16 +08:00
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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2015-03-31 21:35:12 +08:00
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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2016-12-15 06:50:46 +08:00
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2016-06-08 20:31:16 +08:00
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bool runOnMachineFunction(MachineFunction &MF) override;
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2015-03-31 21:35:12 +08:00
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private:
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2017-07-27 07:20:35 +08:00
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const HexagonInstrInfo *HII = nullptr;
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const TargetRegisterInfo *TRI = nullptr;
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2016-06-08 20:31:16 +08:00
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MachineDominatorTree *MDT;
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2017-07-27 07:20:35 +08:00
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MachineRegisterInfo *MRI = nullptr;
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LiveIntervals *LIS = nullptr;
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bool CoaLimitActive = false;
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bool TfrLimitActive = false;
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unsigned CoaLimit;
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unsigned TfrLimit;
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unsigned CoaCounter = 0;
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unsigned TfrCounter = 0;
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2015-03-31 21:35:12 +08:00
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struct RegisterRef {
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RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
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Sub(Op.getSubReg()) {}
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RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
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2016-12-15 06:50:46 +08:00
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2015-03-31 21:35:12 +08:00
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bool operator== (RegisterRef RR) const {
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return Reg == RR.Reg && Sub == RR.Sub;
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}
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bool operator!= (RegisterRef RR) const { return !operator==(RR); }
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2016-06-08 20:31:16 +08:00
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bool operator< (RegisterRef RR) const {
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return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
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}
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2016-12-15 06:50:46 +08:00
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2015-03-31 21:35:12 +08:00
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unsigned Reg, Sub;
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};
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2017-07-27 07:20:35 +08:00
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using ReferenceMap = DenseMap<unsigned, unsigned>;
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2015-03-31 21:35:12 +08:00
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enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
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enum { Exec_Then = 0x10, Exec_Else = 0x20 };
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2017-07-27 07:20:35 +08:00
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2015-03-31 21:35:12 +08:00
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unsigned getMaskForSub(unsigned Sub);
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2016-07-12 09:55:32 +08:00
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bool isCondset(const MachineInstr &MI);
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2016-06-08 20:31:16 +08:00
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LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
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2015-03-31 21:35:12 +08:00
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void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
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bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
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2016-06-08 20:31:16 +08:00
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void updateDeadsInRange(unsigned Reg, LaneBitmask LM, LiveRange &Range);
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void updateKillFlags(unsigned Reg);
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void updateDeadFlags(unsigned Reg);
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void recalculateLiveInterval(unsigned Reg);
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2016-07-12 09:55:32 +08:00
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void removeInstr(MachineInstr &MI);
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2016-06-08 20:31:16 +08:00
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void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
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bool UpdateKills, bool UpdateDeads);
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2015-03-31 21:35:12 +08:00
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unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
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2016-06-08 20:31:16 +08:00
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MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
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MachineBasicBlock::iterator At, unsigned DstR,
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unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
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bool ReadUndef, bool ImpUse);
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2016-07-12 09:55:32 +08:00
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bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs);
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2015-03-31 21:35:12 +08:00
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bool isPredicable(MachineInstr *MI);
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MachineInstr *getReachingDefForPred(RegisterRef RD,
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MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
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2016-07-12 09:55:32 +08:00
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bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
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bool canMoveMemTo(MachineInstr &MI, MachineInstr &ToI, bool IsDown);
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void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
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MachineBasicBlock::iterator Where,
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const MachineOperand &PredOp, bool Cond,
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std::set<unsigned> &UpdRegs);
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2015-03-31 21:35:12 +08:00
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void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
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bool Cond, MachineBasicBlock::iterator First,
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MachineBasicBlock::iterator Last);
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2016-07-12 09:55:32 +08:00
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bool predicate(MachineInstr &TfrI, bool Cond, std::set<unsigned> &UpdRegs);
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2016-06-08 20:31:16 +08:00
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bool predicateInBlock(MachineBasicBlock &B,
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std::set<unsigned> &UpdRegs);
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2015-03-31 21:35:12 +08:00
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bool isIntReg(RegisterRef RR, unsigned &BW);
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bool isIntraBlocks(LiveInterval &LI);
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bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
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2016-10-28 23:50:22 +08:00
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bool coalesceSegments(const SmallVectorImpl<MachineInstr*> &Condsets,
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std::set<unsigned> &UpdRegs);
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2015-03-31 21:35:12 +08:00
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};
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2016-12-15 06:50:46 +08:00
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} // end anonymous namespace
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2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
char HexagonExpandCondsets::ID = 0;
|
|
|
|
|
2016-08-25 06:27:36 +08:00
|
|
|
namespace llvm {
|
2016-12-15 06:50:46 +08:00
|
|
|
|
2016-08-25 06:27:36 +08:00
|
|
|
char &HexagonExpandCondsetsID = HexagonExpandCondsets::ID;
|
2016-12-15 06:50:46 +08:00
|
|
|
|
|
|
|
} // end namespace llvm
|
2016-08-25 06:27:36 +08:00
|
|
|
|
2016-05-28 05:15:34 +08:00
|
|
|
INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets",
|
|
|
|
"Hexagon Expand Condsets", false, false)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
|
|
|
|
INITIALIZE_PASS_END(HexagonExpandCondsets, "expand-condsets",
|
|
|
|
"Hexagon Expand Condsets", false, false)
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
|
|
|
|
switch (Sub) {
|
2016-11-10 00:19:08 +08:00
|
|
|
case Hexagon::isub_lo:
|
|
|
|
case Hexagon::vsub_lo:
|
2015-03-31 21:35:12 +08:00
|
|
|
return Sub_Low;
|
2016-11-10 00:19:08 +08:00
|
|
|
case Hexagon::isub_hi:
|
|
|
|
case Hexagon::vsub_hi:
|
2015-03-31 21:35:12 +08:00
|
|
|
return Sub_High;
|
|
|
|
case Hexagon::NoSubRegister:
|
|
|
|
return Sub_None;
|
|
|
|
}
|
|
|
|
llvm_unreachable("Invalid subregister");
|
|
|
|
}
|
|
|
|
|
2016-07-12 09:55:32 +08:00
|
|
|
bool HexagonExpandCondsets::isCondset(const MachineInstr &MI) {
|
|
|
|
unsigned Opc = MI.getOpcode();
|
2015-03-31 21:35:12 +08:00
|
|
|
switch (Opc) {
|
|
|
|
case Hexagon::C2_mux:
|
|
|
|
case Hexagon::C2_muxii:
|
|
|
|
case Hexagon::C2_muxir:
|
|
|
|
case Hexagon::C2_muxri:
|
2016-08-12 03:12:18 +08:00
|
|
|
case Hexagon::PS_pselect:
|
2015-03-31 21:35:12 +08:00
|
|
|
return true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
|
2019-08-02 07:27:28 +08:00
|
|
|
assert(Register::isVirtualRegister(Reg));
|
2016-06-08 20:31:16 +08:00
|
|
|
return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
|
|
|
|
: MRI->getMaxLaneMaskForVReg(Reg);
|
|
|
|
}
|
|
|
|
|
2015-03-31 21:35:12 +08:00
|
|
|
void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
|
|
|
|
unsigned Exec) {
|
|
|
|
unsigned Mask = getMaskForSub(RR.Sub) | Exec;
|
|
|
|
ReferenceMap::iterator F = Map.find(RR.Reg);
|
|
|
|
if (F == Map.end())
|
|
|
|
Map.insert(std::make_pair(RR.Reg, Mask));
|
|
|
|
else
|
|
|
|
F->second |= Mask;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
|
|
|
|
unsigned Exec) {
|
|
|
|
ReferenceMap::iterator F = Map.find(RR.Reg);
|
|
|
|
if (F == Map.end())
|
|
|
|
return false;
|
|
|
|
unsigned Mask = getMaskForSub(RR.Sub) | Exec;
|
|
|
|
if (Mask & F->second)
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
|
|
|
|
auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void {
|
|
|
|
// Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
|
|
|
|
MachineInstr *MI = LIS->getInstructionFromIndex(K);
|
2018-03-24 03:39:37 +08:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &Op = MI->getOperand(i);
|
|
|
|
if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg ||
|
|
|
|
MI->isRegTiedToDefOperand(i))
|
2016-06-08 03:25:28 +08:00
|
|
|
continue;
|
2016-06-08 20:31:16 +08:00
|
|
|
LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
|
|
|
|
if ((SLM & LM) == SLM) {
|
|
|
|
// Only set the kill flag on the first encountered use of Reg in this
|
|
|
|
// instruction.
|
|
|
|
Op.setIsKill(true);
|
|
|
|
break;
|
|
|
|
}
|
2016-06-08 03:25:28 +08:00
|
|
|
}
|
2016-06-08 20:31:16 +08:00
|
|
|
};
|
2016-06-08 03:25:28 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
LiveInterval &LI = LIS->getInterval(Reg);
|
|
|
|
for (auto I = LI.begin(), E = LI.end(); I != E; ++I) {
|
|
|
|
if (!I->end.isRegister())
|
2015-03-31 21:35:12 +08:00
|
|
|
continue;
|
2016-06-08 20:31:16 +08:00
|
|
|
// Do not mark the end of the segment as <kill>, if the next segment
|
|
|
|
// starts with a predicated instruction.
|
|
|
|
auto NextI = std::next(I);
|
|
|
|
if (NextI != E && NextI->start.isRegister()) {
|
|
|
|
MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
|
|
|
|
if (HII->isPredicated(*DefI))
|
2016-06-08 03:06:23 +08:00
|
|
|
continue;
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
2016-06-08 20:31:16 +08:00
|
|
|
bool WholeReg = true;
|
|
|
|
if (LI.hasSubRanges()) {
|
|
|
|
auto EndsAtI = [I] (LiveInterval::SubRange &S) -> bool {
|
|
|
|
LiveRange::iterator F = S.find(I->end);
|
|
|
|
return F != S.end() && I->end == F->end;
|
|
|
|
};
|
|
|
|
// Check if all subranges end at I->end. If so, make sure to kill
|
|
|
|
// the whole register.
|
|
|
|
for (LiveInterval::SubRange &S : LI.subranges()) {
|
|
|
|
if (EndsAtI(S))
|
|
|
|
KillAt(I->end, S.LaneMask);
|
|
|
|
else
|
|
|
|
WholeReg = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (WholeReg)
|
|
|
|
KillAt(I->end, MRI->getMaxLaneMaskForVReg(Reg));
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
2016-06-08 03:25:28 +08:00
|
|
|
}
|
2015-03-31 21:35:12 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
|
|
|
|
LiveRange &Range) {
|
2019-08-02 07:27:28 +08:00
|
|
|
assert(Register::isVirtualRegister(Reg));
|
2016-06-08 20:31:16 +08:00
|
|
|
if (Range.empty())
|
2016-06-08 03:25:28 +08:00
|
|
|
return;
|
|
|
|
|
2017-03-07 01:09:06 +08:00
|
|
|
// Return two booleans: { def-modifes-reg, def-covers-reg }.
|
|
|
|
auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> {
|
2016-06-08 20:31:16 +08:00
|
|
|
if (!Op.isReg() || !Op.isDef())
|
2017-03-07 01:09:06 +08:00
|
|
|
return { false, false };
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register DR = Op.getReg(), DSR = Op.getSubReg();
|
2019-08-02 07:27:28 +08:00
|
|
|
if (!Register::isVirtualRegister(DR) || DR != Reg)
|
2017-03-07 01:09:06 +08:00
|
|
|
return { false, false };
|
2016-06-08 20:31:16 +08:00
|
|
|
LaneBitmask SLM = getLaneMask(DR, DSR);
|
2017-03-07 01:09:06 +08:00
|
|
|
LaneBitmask A = SLM & LM;
|
|
|
|
return { A.any(), A == SLM };
|
2016-06-08 20:31:16 +08:00
|
|
|
};
|
2015-03-31 21:35:12 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
// The splitting step will create pairs of predicated definitions without
|
|
|
|
// any implicit uses (since implicit uses would interfere with predication).
|
|
|
|
// This can cause the reaching defs to become dead after live range
|
|
|
|
// recomputation, even though they are not really dead.
|
|
|
|
// We need to identify predicated defs that need implicit uses, and
|
|
|
|
// dead defs that are not really dead, and correct both problems.
|
|
|
|
|
|
|
|
auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs,
|
|
|
|
MachineBasicBlock *Dest) -> bool {
|
|
|
|
for (MachineBasicBlock *D : Defs)
|
|
|
|
if (D != Dest && MDT->dominates(D, Dest))
|
|
|
|
return true;
|
2015-03-31 21:35:12 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
MachineBasicBlock *Entry = &Dest->getParent()->front();
|
|
|
|
SetVector<MachineBasicBlock*> Work(Dest->pred_begin(), Dest->pred_end());
|
|
|
|
for (unsigned i = 0; i < Work.size(); ++i) {
|
|
|
|
MachineBasicBlock *B = Work[i];
|
|
|
|
if (Defs.count(B))
|
|
|
|
continue;
|
|
|
|
if (B == Entry)
|
|
|
|
return false;
|
|
|
|
for (auto *P : B->predecessors())
|
|
|
|
Work.insert(P);
|
2016-06-08 03:25:28 +08:00
|
|
|
}
|
2016-06-08 20:31:16 +08:00
|
|
|
return true;
|
|
|
|
};
|
2016-06-08 03:25:28 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
// First, try to extend live range within individual basic blocks. This
|
|
|
|
// will leave us only with dead defs that do not reach any predicated
|
|
|
|
// defs in the same block.
|
2016-10-28 23:50:22 +08:00
|
|
|
SetVector<MachineBasicBlock*> Defs;
|
2016-06-08 20:31:16 +08:00
|
|
|
SmallVector<SlotIndex,4> PredDefs;
|
|
|
|
for (auto &Seg : Range) {
|
|
|
|
if (!Seg.start.isRegister())
|
|
|
|
continue;
|
|
|
|
MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
|
|
|
|
Defs.insert(DefI->getParent());
|
|
|
|
if (HII->isPredicated(*DefI))
|
|
|
|
PredDefs.push_back(Seg.start);
|
|
|
|
}
|
2016-08-24 21:37:55 +08:00
|
|
|
|
|
|
|
SmallVector<SlotIndex,8> Undefs;
|
|
|
|
LiveInterval &LI = LIS->getInterval(Reg);
|
|
|
|
LI.computeSubRangeUndefs(Undefs, LM, *MRI, *LIS->getSlotIndexes());
|
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
for (auto &SI : PredDefs) {
|
|
|
|
MachineBasicBlock *BB = LIS->getMBBFromIndex(SI);
|
2016-08-24 21:37:55 +08:00
|
|
|
auto P = Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI);
|
|
|
|
if (P.first != nullptr || P.second)
|
2016-06-08 20:31:16 +08:00
|
|
|
SI = SlotIndex();
|
2016-06-08 03:25:28 +08:00
|
|
|
}
|
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
// Calculate reachability for those predicated defs that were not handled
|
|
|
|
// by the in-block extension.
|
|
|
|
SmallVector<SlotIndex,4> ExtTo;
|
|
|
|
for (auto &SI : PredDefs) {
|
|
|
|
if (!SI.isValid())
|
|
|
|
continue;
|
|
|
|
MachineBasicBlock *BB = LIS->getMBBFromIndex(SI);
|
|
|
|
if (BB->pred_empty())
|
|
|
|
continue;
|
|
|
|
// If the defs from this range reach SI via all predecessors, it is live.
|
2016-10-28 23:50:22 +08:00
|
|
|
// It can happen that SI is reached by the defs through some paths, but
|
|
|
|
// not all. In the IR coming into this optimization, SI would not be
|
|
|
|
// considered live, since the defs would then not jointly dominate SI.
|
|
|
|
// That means that SI is an overwriting def, and no implicit use is
|
|
|
|
// needed at this point. Do not add SI to the extension points, since
|
|
|
|
// extendToIndices will abort if there is no joint dominance.
|
|
|
|
// If the abort was avoided by adding extra undefs added to Undefs,
|
|
|
|
// extendToIndices could actually indicate that SI is live, contrary
|
|
|
|
// to the original IR.
|
2016-06-08 20:31:16 +08:00
|
|
|
if (Dominate(Defs, BB))
|
|
|
|
ExtTo.push_back(SI);
|
|
|
|
}
|
2016-10-28 23:50:22 +08:00
|
|
|
|
|
|
|
if (!ExtTo.empty())
|
|
|
|
LIS->extendToIndices(Range, ExtTo, Undefs);
|
2016-06-08 20:31:16 +08:00
|
|
|
|
|
|
|
// Remove <dead> flags from all defs that are not dead after live range
|
|
|
|
// extension, and collect all def operands. They will be used to generate
|
|
|
|
// the necessary implicit uses.
|
2017-03-07 01:09:06 +08:00
|
|
|
// At the same time, add <dead> flag to all defs that are actually dead.
|
|
|
|
// This can happen, for example, when a mux with identical inputs is
|
|
|
|
// replaced with a COPY: the use of the predicate register disappears and
|
|
|
|
// the dead can become dead.
|
2016-06-08 20:31:16 +08:00
|
|
|
std::set<RegisterRef> DefRegs;
|
|
|
|
for (auto &Seg : Range) {
|
|
|
|
if (!Seg.start.isRegister())
|
2016-06-08 03:25:28 +08:00
|
|
|
continue;
|
2016-06-08 20:31:16 +08:00
|
|
|
MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
|
|
|
|
for (auto &Op : DefI->operands()) {
|
2017-03-07 01:09:06 +08:00
|
|
|
auto P = IsRegDef(Op);
|
|
|
|
if (P.second && Seg.end.isDead()) {
|
|
|
|
Op.setIsDead(true);
|
|
|
|
} else if (P.first) {
|
|
|
|
DefRegs.insert(Op);
|
|
|
|
Op.setIsDead(false);
|
|
|
|
}
|
2016-06-08 03:25:28 +08:00
|
|
|
}
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
|
2017-03-07 01:09:06 +08:00
|
|
|
// Now, add implicit uses to each predicated def that is reached
|
2016-08-25 00:36:37 +08:00
|
|
|
// by other defs.
|
2016-06-08 20:31:16 +08:00
|
|
|
for (auto &Seg : Range) {
|
|
|
|
if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot()))
|
2016-06-08 03:25:28 +08:00
|
|
|
continue;
|
2016-06-08 20:31:16 +08:00
|
|
|
MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
|
|
|
|
if (!HII->isPredicated(*DefI))
|
2016-06-08 03:25:28 +08:00
|
|
|
continue;
|
2016-06-08 20:31:16 +08:00
|
|
|
// Construct the set of all necessary implicit uses, based on the def
|
2017-08-10 03:58:00 +08:00
|
|
|
// operands in the instruction. We need to tie the implicit uses to
|
|
|
|
// the corresponding defs.
|
|
|
|
std::map<RegisterRef,unsigned> ImpUses;
|
|
|
|
for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &Op = DefI->getOperand(i);
|
|
|
|
if (!Op.isReg() || !DefRegs.count(Op))
|
|
|
|
continue;
|
|
|
|
if (Op.isDef()) {
|
2018-07-10 20:57:49 +08:00
|
|
|
// Tied defs will always have corresponding uses, so no extra
|
|
|
|
// implicit uses are needed.
|
|
|
|
if (!Op.isTied())
|
|
|
|
ImpUses.insert({Op, i});
|
2017-08-10 03:58:00 +08:00
|
|
|
} else {
|
|
|
|
// This function can be called for the same register with different
|
|
|
|
// lane masks. If the def in this instruction was for the whole
|
|
|
|
// register, we can get here more than once. Avoid adding multiple
|
|
|
|
// implicit uses (or adding an implicit use when an explicit one is
|
|
|
|
// present).
|
2018-07-10 20:57:49 +08:00
|
|
|
if (Op.isTied())
|
|
|
|
ImpUses.erase(Op);
|
2017-08-10 03:58:00 +08:00
|
|
|
}
|
|
|
|
}
|
2016-10-28 23:50:22 +08:00
|
|
|
if (ImpUses.empty())
|
|
|
|
continue;
|
|
|
|
MachineFunction &MF = *DefI->getParent()->getParent();
|
2017-08-10 03:58:00 +08:00
|
|
|
for (std::pair<RegisterRef, unsigned> P : ImpUses) {
|
|
|
|
RegisterRef R = P.first;
|
2016-06-08 20:31:16 +08:00
|
|
|
MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
|
2017-08-10 03:58:00 +08:00
|
|
|
DefI->tieOperands(P.second, DefI->getNumOperands()-1);
|
|
|
|
}
|
2016-06-08 20:31:16 +08:00
|
|
|
}
|
|
|
|
}
|
2016-06-08 03:06:23 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
|
|
|
|
LiveInterval &LI = LIS->getInterval(Reg);
|
|
|
|
if (LI.hasSubRanges()) {
|
|
|
|
for (LiveInterval::SubRange &S : LI.subranges()) {
|
|
|
|
updateDeadsInRange(Reg, S.LaneMask, S);
|
|
|
|
LIS->shrinkToUses(S, Reg);
|
2016-06-08 03:25:28 +08:00
|
|
|
}
|
2016-06-08 20:31:16 +08:00
|
|
|
LI.clear();
|
|
|
|
LIS->constructMainRangeFromSubranges(LI);
|
|
|
|
} else {
|
|
|
|
updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI);
|
2016-06-08 03:25:28 +08:00
|
|
|
}
|
2016-06-08 20:31:16 +08:00
|
|
|
}
|
2016-06-08 03:06:23 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
void HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) {
|
|
|
|
LIS->removeInterval(Reg);
|
|
|
|
LIS->createAndComputeVirtRegInterval(Reg);
|
|
|
|
}
|
|
|
|
|
2016-07-12 09:55:32 +08:00
|
|
|
void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
|
|
|
|
LIS->RemoveMachineInstrFromMaps(MI);
|
|
|
|
MI.eraseFromParent();
|
2016-06-08 20:31:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
|
|
|
|
bool Recalc, bool UpdateKills, bool UpdateDeads) {
|
|
|
|
UpdateKills |= UpdateDeads;
|
2018-05-04 21:59:05 +08:00
|
|
|
for (unsigned R : RegSet) {
|
2019-08-02 07:27:28 +08:00
|
|
|
if (!Register::isVirtualRegister(R)) {
|
|
|
|
assert(Register::isPhysicalRegister(R));
|
2018-05-04 21:59:05 +08:00
|
|
|
// There shouldn't be any physical registers as operands, except
|
|
|
|
// possibly reserved registers.
|
|
|
|
assert(MRI->isReserved(R));
|
|
|
|
continue;
|
|
|
|
}
|
2016-06-08 20:31:16 +08:00
|
|
|
if (Recalc)
|
|
|
|
recalculateLiveInterval(R);
|
|
|
|
if (UpdateKills)
|
|
|
|
MRI->clearKillFlags(R);
|
|
|
|
if (UpdateDeads)
|
|
|
|
updateDeadFlags(R);
|
|
|
|
// Fixing <dead> flags may extend live ranges, so reset <kill> flags
|
|
|
|
// after that.
|
|
|
|
if (UpdateKills)
|
|
|
|
updateKillFlags(R);
|
|
|
|
LIS->getInterval(R).verify();
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Get the opcode for a conditional transfer of the value in SO (source
|
|
|
|
/// operand). The condition (true/false) is given in Cond.
|
|
|
|
unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
|
2016-06-08 20:31:16 +08:00
|
|
|
bool IfTrue) {
|
2015-03-31 21:35:12 +08:00
|
|
|
using namespace Hexagon;
|
2016-12-15 06:50:46 +08:00
|
|
|
|
2015-03-31 21:35:12 +08:00
|
|
|
if (SO.isReg()) {
|
2019-08-03 04:23:00 +08:00
|
|
|
Register PhysR;
|
2015-03-31 21:35:12 +08:00
|
|
|
RegisterRef RS = SO;
|
2019-08-02 07:27:28 +08:00
|
|
|
if (Register::isVirtualRegister(RS.Reg)) {
|
2015-03-31 21:35:12 +08:00
|
|
|
const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
|
|
|
|
assert(VC->begin() != VC->end() && "Empty register class");
|
|
|
|
PhysR = *VC->begin();
|
|
|
|
} else {
|
2019-08-02 07:27:28 +08:00
|
|
|
assert(Register::isPhysicalRegister(RS.Reg));
|
2015-03-31 21:35:12 +08:00
|
|
|
PhysR = RS.Reg;
|
|
|
|
}
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
|
2015-03-31 21:35:12 +08:00
|
|
|
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
|
2017-04-25 02:55:33 +08:00
|
|
|
switch (TRI->getRegSizeInBits(*RC)) {
|
|
|
|
case 32:
|
2016-06-08 20:31:16 +08:00
|
|
|
return IfTrue ? A2_tfrt : A2_tfrf;
|
2017-04-25 02:55:33 +08:00
|
|
|
case 64:
|
2016-06-08 20:31:16 +08:00
|
|
|
return IfTrue ? A2_tfrpt : A2_tfrpf;
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
llvm_unreachable("Invalid register operand");
|
|
|
|
}
|
2017-06-22 03:21:30 +08:00
|
|
|
switch (SO.getType()) {
|
|
|
|
case MachineOperand::MO_Immediate:
|
|
|
|
case MachineOperand::MO_FPImmediate:
|
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
|
|
|
case MachineOperand::MO_TargetIndex:
|
|
|
|
case MachineOperand::MO_JumpTableIndex:
|
|
|
|
case MachineOperand::MO_ExternalSymbol:
|
|
|
|
case MachineOperand::MO_GlobalAddress:
|
|
|
|
case MachineOperand::MO_BlockAddress:
|
|
|
|
return IfTrue ? C2_cmoveit : C2_cmoveif;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2015-03-31 21:35:12 +08:00
|
|
|
llvm_unreachable("Unexpected source operand");
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Generate a conditional transfer, copying the value SrcOp to the
|
|
|
|
/// destination register DstR:DstSR, and using the predicate register from
|
|
|
|
/// PredOp. The Cond argument specifies whether the predicate is to be
|
|
|
|
/// if(PredOp), or if(!PredOp).
|
2016-06-08 20:31:16 +08:00
|
|
|
MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
|
|
|
|
MachineBasicBlock::iterator At,
|
|
|
|
unsigned DstR, unsigned DstSR, const MachineOperand &PredOp,
|
|
|
|
bool PredSense, bool ReadUndef, bool ImpUse) {
|
2015-03-31 21:35:12 +08:00
|
|
|
MachineInstr *MI = SrcOp.getParent();
|
2016-06-08 20:31:16 +08:00
|
|
|
MachineBasicBlock &B = *At->getParent();
|
2016-06-13 01:30:47 +08:00
|
|
|
const DebugLoc &DL = MI->getDebugLoc();
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
// Don't avoid identity copies here (i.e. if the source and the destination
|
|
|
|
// are the same registers). It is actually better to generate them here,
|
|
|
|
// since this would cause the copy to potentially be predicated in the next
|
|
|
|
// step. The predication will remove such a copy if it is unable to
|
|
|
|
/// predicate.
|
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
unsigned Opc = getCondTfrOpcode(SrcOp, PredSense);
|
2016-10-28 23:50:22 +08:00
|
|
|
unsigned DstState = RegState::Define | (ReadUndef ? RegState::Undef : 0);
|
|
|
|
unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
|
|
|
|
MachineInstrBuilder MIB;
|
|
|
|
|
|
|
|
if (SrcOp.isReg()) {
|
|
|
|
unsigned SrcState = getRegState(SrcOp);
|
|
|
|
if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
|
|
|
|
SrcState &= ~RegState::Kill;
|
|
|
|
MIB = BuildMI(B, At, DL, HII->get(Opc))
|
|
|
|
.addReg(DstR, DstState, DstSR)
|
|
|
|
.addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
|
|
|
|
.addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
|
|
|
|
} else {
|
|
|
|
MIB = BuildMI(B, At, DL, HII->get(Opc))
|
2017-01-13 17:58:52 +08:00
|
|
|
.addReg(DstR, DstState, DstSR)
|
|
|
|
.addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
|
|
|
|
.add(SrcOp);
|
2016-10-28 23:50:22 +08:00
|
|
|
}
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "created an initial copy: " << *MIB);
|
2016-06-08 20:31:16 +08:00
|
|
|
return &*MIB;
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
|
|
|
|
/// performs all necessary changes to complete the replacement.
|
2016-07-12 09:55:32 +08:00
|
|
|
bool HexagonExpandCondsets::split(MachineInstr &MI,
|
|
|
|
std::set<unsigned> &UpdRegs) {
|
2015-03-31 21:35:12 +08:00
|
|
|
if (TfrLimitActive) {
|
|
|
|
if (TfrCounter >= TfrLimit)
|
|
|
|
return false;
|
|
|
|
TfrCounter++;
|
|
|
|
}
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent())
|
|
|
|
<< ": " << MI);
|
2016-07-12 09:55:32 +08:00
|
|
|
MachineOperand &MD = MI.getOperand(0); // Definition
|
|
|
|
MachineOperand &MP = MI.getOperand(1); // Predicate register
|
2015-03-31 21:35:12 +08:00
|
|
|
assert(MD.isDef());
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register DR = MD.getReg(), DSR = MD.getSubReg();
|
2016-06-08 20:31:16 +08:00
|
|
|
bool ReadUndef = MD.isUndef();
|
|
|
|
MachineBasicBlock::iterator At = MI;
|
|
|
|
|
2017-03-07 01:09:06 +08:00
|
|
|
auto updateRegs = [&UpdRegs] (const MachineInstr &MI) -> void {
|
|
|
|
for (auto &Op : MI.operands())
|
|
|
|
if (Op.isReg())
|
|
|
|
UpdRegs.insert(Op.getReg());
|
|
|
|
};
|
|
|
|
|
2016-10-31 23:45:09 +08:00
|
|
|
// If this is a mux of the same register, just replace it with COPY.
|
|
|
|
// Ideally, this would happen earlier, so that register coalescing would
|
|
|
|
// see it.
|
|
|
|
MachineOperand &ST = MI.getOperand(2);
|
|
|
|
MachineOperand &SF = MI.getOperand(3);
|
|
|
|
if (ST.isReg() && SF.isReg()) {
|
|
|
|
RegisterRef RT(ST);
|
|
|
|
if (RT == RegisterRef(SF)) {
|
2017-03-07 01:09:06 +08:00
|
|
|
// Copy regs to update first.
|
|
|
|
updateRegs(MI);
|
2016-10-31 23:45:09 +08:00
|
|
|
MI.setDesc(HII->get(TargetOpcode::COPY));
|
|
|
|
unsigned S = getRegState(ST);
|
|
|
|
while (MI.getNumOperands() > 1)
|
|
|
|
MI.RemoveOperand(MI.getNumOperands()-1);
|
|
|
|
MachineFunction &MF = *MI.getParent()->getParent();
|
|
|
|
MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-03-31 21:35:12 +08:00
|
|
|
// First, create the two invididual conditional transfers, and add each
|
|
|
|
// of them to the live intervals information. Do that first and then remove
|
|
|
|
// the old instruction from live intervals.
|
2016-07-12 09:55:32 +08:00
|
|
|
MachineInstr *TfrT =
|
2016-10-31 23:45:09 +08:00
|
|
|
genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false);
|
2016-07-12 09:55:32 +08:00
|
|
|
MachineInstr *TfrF =
|
2016-10-31 23:45:09 +08:00
|
|
|
genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true);
|
2016-06-08 20:31:16 +08:00
|
|
|
LIS->InsertMachineInstrInMaps(*TfrT);
|
|
|
|
LIS->InsertMachineInstrInMaps(*TfrF);
|
|
|
|
|
|
|
|
// Will need to recalculate live intervals for all registers in MI.
|
2017-03-07 01:09:06 +08:00
|
|
|
updateRegs(MI);
|
2015-03-31 21:35:12 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
removeInstr(MI);
|
2015-03-31 21:35:12 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
|
2016-02-23 10:46:52 +08:00
|
|
|
if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
|
2015-03-31 21:35:12 +08:00
|
|
|
return false;
|
|
|
|
if (MI->hasUnmodeledSideEffects() || MI->mayStore())
|
|
|
|
return false;
|
|
|
|
// Reject instructions with multiple defs (e.g. post-increment loads).
|
|
|
|
bool HasDef = false;
|
|
|
|
for (auto &Op : MI->operands()) {
|
|
|
|
if (!Op.isReg() || !Op.isDef())
|
|
|
|
continue;
|
|
|
|
if (HasDef)
|
|
|
|
return false;
|
|
|
|
HasDef = true;
|
|
|
|
}
|
|
|
|
for (auto &Mo : MI->memoperands())
|
2019-02-24 08:45:09 +08:00
|
|
|
if (Mo->isVolatile() || Mo->isAtomic())
|
2015-03-31 21:35:12 +08:00
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Find the reaching definition for a predicated use of RD. The RD is used
|
|
|
|
/// under the conditions given by PredR and Cond, and this function will ignore
|
|
|
|
/// definitions that set RD under the opposite conditions.
|
|
|
|
MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
|
|
|
|
MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
|
|
|
|
MachineBasicBlock &B = *UseIt->getParent();
|
|
|
|
MachineBasicBlock::iterator I = UseIt, S = B.begin();
|
|
|
|
if (I == S)
|
2016-12-15 06:50:46 +08:00
|
|
|
return nullptr;
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
bool PredValid = true;
|
|
|
|
do {
|
|
|
|
--I;
|
|
|
|
MachineInstr *MI = &*I;
|
|
|
|
// Check if this instruction can be ignored, i.e. if it is predicated
|
|
|
|
// on the complementary condition.
|
2016-02-23 10:46:52 +08:00
|
|
|
if (PredValid && HII->isPredicated(*MI)) {
|
|
|
|
if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
|
2015-03-31 21:35:12 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check the defs. If the PredR is defined, invalidate it. If RD is
|
|
|
|
// defined, return the instruction or 0, depending on the circumstances.
|
|
|
|
for (auto &Op : MI->operands()) {
|
|
|
|
if (!Op.isReg() || !Op.isDef())
|
|
|
|
continue;
|
|
|
|
RegisterRef RR = Op;
|
|
|
|
if (RR.Reg == PredR) {
|
|
|
|
PredValid = false;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (RR.Reg != RD.Reg)
|
|
|
|
continue;
|
|
|
|
// If the "Reg" part agrees, there is still the subregister to check.
|
2017-11-30 20:12:19 +08:00
|
|
|
// If we are looking for %1:loreg, we can skip %1:hireg, but
|
|
|
|
// not %1 (w/o subregisters).
|
2015-03-31 21:35:12 +08:00
|
|
|
if (RR.Sub == RD.Sub)
|
|
|
|
return MI;
|
|
|
|
if (RR.Sub == 0 || RD.Sub == 0)
|
2016-12-15 06:50:46 +08:00
|
|
|
return nullptr;
|
2015-03-31 21:35:12 +08:00
|
|
|
// We have different subregisters, so we can continue looking.
|
|
|
|
}
|
|
|
|
} while (I != S);
|
|
|
|
|
2016-12-15 06:50:46 +08:00
|
|
|
return nullptr;
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Check if the instruction MI can be safely moved over a set of instructions
|
|
|
|
/// whose side-effects (in terms of register defs and uses) are expressed in
|
|
|
|
/// the maps Defs and Uses. These maps reflect the conditional defs and uses
|
|
|
|
/// that depend on the same predicate register to allow moving instructions
|
|
|
|
/// over instructions predicated on the opposite condition.
|
2016-07-12 09:55:32 +08:00
|
|
|
bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs,
|
|
|
|
ReferenceMap &Uses) {
|
2015-03-31 21:35:12 +08:00
|
|
|
// In order to be able to safely move MI over instructions that define
|
|
|
|
// "Defs" and use "Uses", no def operand from MI can be defined or used
|
|
|
|
// and no use operand can be defined.
|
2016-07-12 09:55:32 +08:00
|
|
|
for (auto &Op : MI.operands()) {
|
2015-03-31 21:35:12 +08:00
|
|
|
if (!Op.isReg())
|
|
|
|
continue;
|
|
|
|
RegisterRef RR = Op;
|
|
|
|
// For physical register we would need to check register aliases, etc.
|
|
|
|
// and we don't want to bother with that. It would be of little value
|
|
|
|
// before the actual register rewriting (from virtual to physical).
|
2019-08-02 07:27:28 +08:00
|
|
|
if (!Register::isVirtualRegister(RR.Reg))
|
2015-03-31 21:35:12 +08:00
|
|
|
return false;
|
|
|
|
// No redefs for any operand.
|
|
|
|
if (isRefInMap(RR, Defs, Exec_Then))
|
|
|
|
return false;
|
|
|
|
// For defs, there cannot be uses.
|
|
|
|
if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Check if the instruction accessing memory (TheI) can be moved to the
|
|
|
|
/// location ToI.
|
2016-07-12 09:55:32 +08:00
|
|
|
bool HexagonExpandCondsets::canMoveMemTo(MachineInstr &TheI, MachineInstr &ToI,
|
|
|
|
bool IsDown) {
|
|
|
|
bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore();
|
2015-03-31 21:35:12 +08:00
|
|
|
if (!IsLoad && !IsStore)
|
|
|
|
return true;
|
2016-07-12 09:55:32 +08:00
|
|
|
if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
|
2015-03-31 21:35:12 +08:00
|
|
|
return true;
|
2016-07-12 09:55:32 +08:00
|
|
|
if (TheI.hasUnmodeledSideEffects())
|
2015-03-31 21:35:12 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI;
|
|
|
|
MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI;
|
2016-07-12 09:55:32 +08:00
|
|
|
bool Ordered = TheI.hasOrderedMemoryRef();
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
// Search for aliased memory reference in (StartI, EndI).
|
|
|
|
for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) {
|
|
|
|
MachineInstr *MI = &*I;
|
|
|
|
if (MI->hasUnmodeledSideEffects())
|
|
|
|
return false;
|
|
|
|
bool L = MI->mayLoad(), S = MI->mayStore();
|
|
|
|
if (!L && !S)
|
|
|
|
continue;
|
|
|
|
if (Ordered && MI->hasOrderedMemoryRef())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
bool Conflict = (L && IsStore) || S;
|
|
|
|
if (Conflict)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Generate a predicated version of MI (where the condition is given via
|
|
|
|
/// PredR and Cond) at the point indicated by Where.
|
2016-06-08 20:31:16 +08:00
|
|
|
void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
|
2016-07-12 09:55:32 +08:00
|
|
|
MachineInstr &MI,
|
|
|
|
MachineBasicBlock::iterator Where,
|
|
|
|
const MachineOperand &PredOp, bool Cond,
|
|
|
|
std::set<unsigned> &UpdRegs) {
|
2015-03-31 21:35:12 +08:00
|
|
|
// The problem with updating live intervals is that we can move one def
|
|
|
|
// past another def. In particular, this can happen when moving an A2_tfrt
|
|
|
|
// over an A2_tfrf defining the same register. From the point of view of
|
|
|
|
// live intervals, these two instructions are two separate definitions,
|
|
|
|
// and each one starts another live segment. LiveIntervals's "handleMove"
|
|
|
|
// does not allow such moves, so we need to handle it ourselves. To avoid
|
|
|
|
// invalidating liveness data while we are using it, the move will be
|
|
|
|
// implemented in 4 steps: (1) add a clone of the instruction MI at the
|
|
|
|
// target location, (2) update liveness, (3) delete the old instruction,
|
|
|
|
// and (4) update liveness again.
|
|
|
|
|
2016-07-12 09:55:32 +08:00
|
|
|
MachineBasicBlock &B = *MI.getParent();
|
2015-03-31 21:35:12 +08:00
|
|
|
DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction.
|
2016-07-12 09:55:32 +08:00
|
|
|
unsigned Opc = MI.getOpcode();
|
2015-03-31 21:35:12 +08:00
|
|
|
unsigned PredOpc = HII->getCondOpcode(Opc, !Cond);
|
|
|
|
MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
|
2016-07-12 09:55:32 +08:00
|
|
|
unsigned Ox = 0, NP = MI.getNumOperands();
|
2015-03-31 21:35:12 +08:00
|
|
|
// Skip all defs from MI first.
|
|
|
|
while (Ox < NP) {
|
2016-07-12 09:55:32 +08:00
|
|
|
MachineOperand &MO = MI.getOperand(Ox);
|
2015-03-31 21:35:12 +08:00
|
|
|
if (!MO.isReg() || !MO.isDef())
|
|
|
|
break;
|
|
|
|
Ox++;
|
|
|
|
}
|
|
|
|
// Add the new def, then the predicate register, then the rest of the
|
|
|
|
// operands.
|
2016-06-08 20:31:16 +08:00
|
|
|
MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
|
|
|
|
MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
|
|
|
|
PredOp.getSubReg());
|
2015-03-31 21:35:12 +08:00
|
|
|
while (Ox < NP) {
|
2016-07-12 09:55:32 +08:00
|
|
|
MachineOperand &MO = MI.getOperand(Ox);
|
2015-03-31 21:35:12 +08:00
|
|
|
if (!MO.isReg() || !MO.isImplicit())
|
2017-01-13 17:58:52 +08:00
|
|
|
MB.add(MO);
|
2015-03-31 21:35:12 +08:00
|
|
|
Ox++;
|
|
|
|
}
|
2018-08-17 05:30:05 +08:00
|
|
|
MB.cloneMemRefs(MI);
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
MachineInstr *NewI = MB;
|
|
|
|
NewI->clearKillInfo();
|
2016-06-08 20:31:16 +08:00
|
|
|
LIS->InsertMachineInstrInMaps(*NewI);
|
|
|
|
|
|
|
|
for (auto &Op : NewI->operands())
|
|
|
|
if (Op.isReg())
|
|
|
|
UpdRegs.insert(Op.getReg());
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// In the range [First, Last], rename all references to the "old" register RO
|
|
|
|
/// to the "new" register RN, but only in instructions predicated on the given
|
|
|
|
/// condition.
|
|
|
|
void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
|
|
|
|
unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
|
|
|
|
MachineBasicBlock::iterator Last) {
|
|
|
|
MachineBasicBlock::iterator End = std::next(Last);
|
|
|
|
for (MachineBasicBlock::iterator I = First; I != End; ++I) {
|
|
|
|
MachineInstr *MI = &*I;
|
|
|
|
// Do not touch instructions that are not predicated, or are predicated
|
|
|
|
// on the opposite condition.
|
2016-02-23 10:46:52 +08:00
|
|
|
if (!HII->isPredicated(*MI))
|
2015-03-31 21:35:12 +08:00
|
|
|
continue;
|
2016-02-23 10:46:52 +08:00
|
|
|
if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI)))
|
2015-03-31 21:35:12 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
for (auto &Op : MI->operands()) {
|
|
|
|
if (!Op.isReg() || RO != RegisterRef(Op))
|
|
|
|
continue;
|
|
|
|
Op.setReg(RN.Reg);
|
|
|
|
Op.setSubReg(RN.Sub);
|
|
|
|
// In practice, this isn't supposed to see any defs.
|
|
|
|
assert(!Op.isDef() && "Not expecting a def");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// For a given conditional copy, predicate the definition of the source of
|
|
|
|
/// the copy under the given condition (using the same predicate register as
|
|
|
|
/// the copy).
|
2016-07-12 09:55:32 +08:00
|
|
|
bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
|
|
|
|
std::set<unsigned> &UpdRegs) {
|
2015-03-31 21:35:12 +08:00
|
|
|
// TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
|
2016-07-12 09:55:32 +08:00
|
|
|
unsigned Opc = TfrI.getOpcode();
|
2015-04-01 03:43:47 +08:00
|
|
|
(void)Opc;
|
2015-03-31 21:35:12 +08:00
|
|
|
assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
|
|
|
|
<< ": " << TfrI);
|
2015-03-31 21:35:12 +08:00
|
|
|
|
2016-07-12 09:55:32 +08:00
|
|
|
MachineOperand &MD = TfrI.getOperand(0);
|
|
|
|
MachineOperand &MP = TfrI.getOperand(1);
|
|
|
|
MachineOperand &MS = TfrI.getOperand(2);
|
2015-03-31 21:35:12 +08:00
|
|
|
// The source operand should be a <kill>. This is not strictly necessary,
|
|
|
|
// but it makes things a lot simpler. Otherwise, we would need to rename
|
|
|
|
// some registers, which would complicate the transformation considerably.
|
|
|
|
if (!MS.isKill())
|
|
|
|
return false;
|
2016-06-08 20:31:16 +08:00
|
|
|
// Avoid predicating instructions that define a subregister if subregister
|
|
|
|
// liveness tracking is not enabled.
|
|
|
|
if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg()))
|
2016-05-31 22:27:10 +08:00
|
|
|
return false;
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
RegisterRef RT(MS);
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register PredR = MP.getReg();
|
2015-03-31 21:35:12 +08:00
|
|
|
MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond);
|
|
|
|
if (!DefI || !isPredicable(DefI))
|
|
|
|
return false;
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Source def: " << *DefI);
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
// Collect the information about registers defined and used between the
|
|
|
|
// DefI and the TfrI.
|
|
|
|
// Map: reg -> bitmask of subregs
|
|
|
|
ReferenceMap Uses, Defs;
|
|
|
|
MachineBasicBlock::iterator DefIt = DefI, TfrIt = TfrI;
|
|
|
|
|
|
|
|
// Check if the predicate register is valid between DefI and TfrI.
|
|
|
|
// If it is, we can then ignore instructions predicated on the negated
|
|
|
|
// conditions when collecting def and use information.
|
|
|
|
bool PredValid = true;
|
|
|
|
for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
|
2016-12-15 06:50:46 +08:00
|
|
|
if (!I->modifiesRegister(PredR, nullptr))
|
2015-03-31 21:35:12 +08:00
|
|
|
continue;
|
|
|
|
PredValid = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
|
|
|
|
MachineInstr *MI = &*I;
|
|
|
|
// If this instruction is predicated on the same register, it could
|
|
|
|
// potentially be ignored.
|
|
|
|
// By default assume that the instruction executes on the same condition
|
|
|
|
// as TfrI (Exec_Then), and also on the opposite one (Exec_Else).
|
|
|
|
unsigned Exec = Exec_Then | Exec_Else;
|
2016-02-23 10:46:52 +08:00
|
|
|
if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
|
|
|
|
Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else;
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
for (auto &Op : MI->operands()) {
|
|
|
|
if (!Op.isReg())
|
|
|
|
continue;
|
|
|
|
// We don't want to deal with physical registers. The reason is that
|
|
|
|
// they can be aliased with other physical registers. Aliased virtual
|
|
|
|
// registers must share the same register number, and can only differ
|
|
|
|
// in the subregisters, which we are keeping track of. Physical
|
|
|
|
// registers ters no longer have subregisters---their super- and
|
|
|
|
// subregisters are other physical registers, and we are not checking
|
|
|
|
// that.
|
|
|
|
RegisterRef RR = Op;
|
2019-08-02 07:27:28 +08:00
|
|
|
if (!Register::isVirtualRegister(RR.Reg))
|
2015-03-31 21:35:12 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
ReferenceMap &Map = Op.isDef() ? Defs : Uses;
|
2016-11-05 04:41:03 +08:00
|
|
|
if (Op.isDef() && Op.isUndef()) {
|
|
|
|
assert(RR.Sub && "Expecting a subregister on <def,read-undef>");
|
|
|
|
// If this is a <def,read-undef>, then it invalidates the non-written
|
|
|
|
// part of the register. For the purpose of checking the validity of
|
|
|
|
// the move, assume that it modifies the whole register.
|
|
|
|
RR.Sub = 0;
|
|
|
|
}
|
2015-03-31 21:35:12 +08:00
|
|
|
addRefToMap(RR, Map, Exec);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// The situation:
|
|
|
|
// RT = DefI
|
|
|
|
// ...
|
|
|
|
// RD = TfrI ..., RT
|
|
|
|
|
|
|
|
// If the register-in-the-middle (RT) is used or redefined between
|
|
|
|
// DefI and TfrI, we may not be able proceed with this transformation.
|
|
|
|
// We can ignore a def that will not execute together with TfrI, and a
|
|
|
|
// use that will. If there is such a use (that does execute together with
|
|
|
|
// TfrI), we will not be able to move DefI down. If there is a use that
|
|
|
|
// executed if TfrI's condition is false, then RT must be available
|
|
|
|
// unconditionally (cannot be predicated).
|
|
|
|
// Essentially, we need to be able to rename RT to RD in this segment.
|
|
|
|
if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else))
|
|
|
|
return false;
|
|
|
|
RegisterRef RD = MD;
|
|
|
|
// If the predicate register is defined between DefI and TfrI, the only
|
|
|
|
// potential thing to do would be to move the DefI down to TfrI, and then
|
|
|
|
// predicate. The reaching def (DefI) must be movable down to the location
|
|
|
|
// of the TfrI.
|
|
|
|
// If the target register of the TfrI (RD) is not used or defined between
|
|
|
|
// DefI and TfrI, consider moving TfrI up to DefI.
|
|
|
|
bool CanUp = canMoveOver(TfrI, Defs, Uses);
|
2016-07-12 09:55:32 +08:00
|
|
|
bool CanDown = canMoveOver(*DefI, Defs, Uses);
|
2015-03-31 21:35:12 +08:00
|
|
|
// The TfrI does not access memory, but DefI could. Check if it's safe
|
|
|
|
// to move DefI down to TfrI.
|
2019-12-19 19:19:36 +08:00
|
|
|
if (DefI->mayLoadOrStore())
|
2016-07-12 09:55:32 +08:00
|
|
|
if (!canMoveMemTo(*DefI, TfrI, true))
|
2015-03-31 21:35:12 +08:00
|
|
|
CanDown = false;
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
|
|
|
|
<< ", can move down: " << (CanDown ? "yes\n" : "no\n"));
|
2015-03-31 21:35:12 +08:00
|
|
|
MachineBasicBlock::iterator PastDefIt = std::next(DefIt);
|
|
|
|
if (CanUp)
|
2016-07-12 09:55:32 +08:00
|
|
|
predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs);
|
2015-03-31 21:35:12 +08:00
|
|
|
else if (CanDown)
|
2016-07-12 09:55:32 +08:00
|
|
|
predicateAt(MD, *DefI, TfrIt, MP, Cond, UpdRegs);
|
2015-03-31 21:35:12 +08:00
|
|
|
else
|
|
|
|
return false;
|
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
if (RT != RD) {
|
2015-03-31 21:35:12 +08:00
|
|
|
renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt);
|
2016-06-08 20:31:16 +08:00
|
|
|
UpdRegs.insert(RT.Reg);
|
|
|
|
}
|
2015-03-31 21:35:12 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
removeInstr(TfrI);
|
2016-07-12 09:55:32 +08:00
|
|
|
removeInstr(*DefI);
|
2015-03-31 21:35:12 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Predicate all cases of conditional copies in the specified block.
|
2016-06-08 20:31:16 +08:00
|
|
|
bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
|
|
|
|
std::set<unsigned> &UpdRegs) {
|
2015-03-31 21:35:12 +08:00
|
|
|
bool Changed = false;
|
|
|
|
MachineBasicBlock::iterator I, E, NextI;
|
|
|
|
for (I = B.begin(), E = B.end(); I != E; I = NextI) {
|
|
|
|
NextI = std::next(I);
|
|
|
|
unsigned Opc = I->getOpcode();
|
|
|
|
if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
|
2016-07-12 09:55:32 +08:00
|
|
|
bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs);
|
2015-03-31 21:35:12 +08:00
|
|
|
if (!Done) {
|
|
|
|
// If we didn't predicate I, we may need to remove it in case it is
|
2017-11-30 20:12:19 +08:00
|
|
|
// an "identity" copy, e.g. %1 = A2_tfrt %2, %1.
|
2016-06-08 20:31:16 +08:00
|
|
|
if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
|
|
|
|
for (auto &Op : I->operands())
|
|
|
|
if (Op.isReg())
|
|
|
|
UpdRegs.insert(Op.getReg());
|
2016-07-12 09:55:32 +08:00
|
|
|
removeInstr(*I);
|
2016-06-08 20:31:16 +08:00
|
|
|
}
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
Changed |= Done;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
|
2019-08-02 07:27:28 +08:00
|
|
|
if (!Register::isVirtualRegister(RR.Reg))
|
2015-03-31 21:35:12 +08:00
|
|
|
return false;
|
|
|
|
const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
|
|
|
|
if (RC == &Hexagon::IntRegsRegClass) {
|
|
|
|
BW = 32;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (RC == &Hexagon::DoubleRegsRegClass) {
|
|
|
|
BW = (RR.Sub != 0) ? 32 : 64;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) {
|
|
|
|
for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
|
|
|
|
LiveRange::Segment &LR = *I;
|
|
|
|
// Range must start at a register...
|
|
|
|
if (!LR.start.isRegister())
|
|
|
|
return false;
|
|
|
|
// ...and end in a register or in a dead slot.
|
|
|
|
if (!LR.end.isRegister() && !LR.end.isDead())
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
|
|
|
|
if (CoaLimitActive) {
|
|
|
|
if (CoaCounter >= CoaLimit)
|
|
|
|
return false;
|
|
|
|
CoaCounter++;
|
|
|
|
}
|
|
|
|
unsigned BW1, BW2;
|
|
|
|
if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2)
|
|
|
|
return false;
|
|
|
|
if (MRI->isLiveIn(R1.Reg))
|
|
|
|
return false;
|
|
|
|
if (MRI->isLiveIn(R2.Reg))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
LiveInterval &L1 = LIS->getInterval(R1.Reg);
|
|
|
|
LiveInterval &L2 = LIS->getInterval(R2.Reg);
|
2016-08-19 22:29:43 +08:00
|
|
|
if (L2.empty())
|
|
|
|
return false;
|
2016-11-03 01:59:54 +08:00
|
|
|
if (L1.hasSubRanges() || L2.hasSubRanges())
|
|
|
|
return false;
|
2015-03-31 21:35:12 +08:00
|
|
|
bool Overlap = L1.overlaps(L2);
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "compatible registers: ("
|
|
|
|
<< (Overlap ? "overlap" : "disjoint") << ")\n "
|
|
|
|
<< printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
|
|
|
|
<< printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
|
2015-03-31 21:35:12 +08:00
|
|
|
if (R1.Sub || R2.Sub)
|
|
|
|
return false;
|
|
|
|
if (Overlap)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Coalescing could have a negative impact on scheduling, so try to limit
|
|
|
|
// to some reasonable extent. Only consider coalescing segments, when one
|
|
|
|
// of them does not cross basic block boundaries.
|
|
|
|
if (!isIntraBlocks(L1) && !isIntraBlocks(L2))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MRI->replaceRegWith(R2.Reg, R1.Reg);
|
|
|
|
|
|
|
|
// Move all live segments from L2 to L1.
|
2017-07-27 07:20:35 +08:00
|
|
|
using ValueInfoMap = DenseMap<VNInfo *, VNInfo *>;
|
2015-03-31 21:35:12 +08:00
|
|
|
ValueInfoMap VM;
|
|
|
|
for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
|
|
|
|
VNInfo *NewVN, *OldVN = I->valno;
|
|
|
|
ValueInfoMap::iterator F = VM.find(OldVN);
|
|
|
|
if (F == VM.end()) {
|
|
|
|
NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator());
|
|
|
|
VM.insert(std::make_pair(OldVN, NewVN));
|
|
|
|
} else {
|
|
|
|
NewVN = F->second;
|
|
|
|
}
|
|
|
|
L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
|
|
|
|
}
|
|
|
|
while (L2.begin() != L2.end())
|
|
|
|
L2.removeSegment(*L2.begin());
|
2016-11-03 01:59:54 +08:00
|
|
|
LIS->removeInterval(R2.Reg);
|
2015-03-31 21:35:12 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
updateKillFlags(R1.Reg);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "coalesced: " << L1 << "\n");
|
2015-03-31 21:35:12 +08:00
|
|
|
L1.verify();
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-11-18 03:21:20 +08:00
|
|
|
/// Attempt to coalesce one of the source registers to a MUX instruction with
|
2015-03-31 21:35:12 +08:00
|
|
|
/// the destination register. This could lead to having only one predicated
|
|
|
|
/// instruction in the end instead of two.
|
2016-10-28 23:50:22 +08:00
|
|
|
bool HexagonExpandCondsets::coalesceSegments(
|
|
|
|
const SmallVectorImpl<MachineInstr*> &Condsets,
|
|
|
|
std::set<unsigned> &UpdRegs) {
|
|
|
|
SmallVector<MachineInstr*,16> TwoRegs;
|
|
|
|
for (MachineInstr *MI : Condsets) {
|
|
|
|
MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
|
|
|
|
if (!S1.isReg() && !S2.isReg())
|
|
|
|
continue;
|
|
|
|
TwoRegs.push_back(MI);
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool Changed = false;
|
2016-10-28 23:50:22 +08:00
|
|
|
for (MachineInstr *CI : TwoRegs) {
|
2015-03-31 21:35:12 +08:00
|
|
|
RegisterRef RD = CI->getOperand(0);
|
|
|
|
RegisterRef RP = CI->getOperand(1);
|
|
|
|
MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
|
|
|
|
bool Done = false;
|
|
|
|
// Consider this case:
|
2017-11-30 20:12:19 +08:00
|
|
|
// %1 = instr1 ...
|
|
|
|
// %2 = instr2 ...
|
|
|
|
// %0 = C2_mux ..., %1, %2
|
|
|
|
// If %0 was coalesced with %1, we could end up with the following
|
2015-03-31 21:35:12 +08:00
|
|
|
// code:
|
2017-11-30 20:12:19 +08:00
|
|
|
// %0 = instr1 ...
|
|
|
|
// %2 = instr2 ...
|
|
|
|
// %0 = A2_tfrf ..., %2
|
2015-03-31 21:35:12 +08:00
|
|
|
// which will later become:
|
2017-11-30 20:12:19 +08:00
|
|
|
// %0 = instr1 ...
|
|
|
|
// %0 = instr2_cNotPt ...
|
|
|
|
// i.e. there will be an unconditional definition (instr1) of %0
|
2015-03-31 21:35:12 +08:00
|
|
|
// followed by a conditional one. The output dependency was there before
|
|
|
|
// and it unavoidable, but if instr1 is predicable, we will no longer be
|
|
|
|
// able to predicate it here.
|
|
|
|
// To avoid this scenario, don't coalesce the destination register with
|
|
|
|
// a source register that is defined by a predicable instruction.
|
|
|
|
if (S1.isReg()) {
|
|
|
|
RegisterRef RS = S1;
|
|
|
|
MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true);
|
2016-10-28 23:50:22 +08:00
|
|
|
if (!RDef || !HII->isPredicable(*RDef)) {
|
2015-03-31 21:35:12 +08:00
|
|
|
Done = coalesceRegisters(RD, RegisterRef(S1));
|
2016-10-28 23:50:22 +08:00
|
|
|
if (Done) {
|
|
|
|
UpdRegs.insert(RD.Reg);
|
|
|
|
UpdRegs.insert(S1.getReg());
|
|
|
|
}
|
|
|
|
}
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
if (!Done && S2.isReg()) {
|
|
|
|
RegisterRef RS = S2;
|
|
|
|
MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false);
|
2016-11-02 18:00:40 +08:00
|
|
|
if (!RDef || !HII->isPredicable(*RDef)) {
|
2015-03-31 21:35:12 +08:00
|
|
|
Done = coalesceRegisters(RD, RegisterRef(S2));
|
2016-10-28 23:50:22 +08:00
|
|
|
if (Done) {
|
|
|
|
UpdRegs.insert(RD.Reg);
|
|
|
|
UpdRegs.insert(S2.getReg());
|
|
|
|
}
|
2016-11-02 18:00:40 +08:00
|
|
|
}
|
2015-03-31 21:35:12 +08:00
|
|
|
}
|
|
|
|
Changed |= Done;
|
|
|
|
}
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
|
2017-12-16 06:22:58 +08:00
|
|
|
if (skipFunction(MF.getFunction()))
|
2016-04-27 03:46:28 +08:00
|
|
|
return false;
|
|
|
|
|
2015-03-31 21:35:12 +08:00
|
|
|
HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo());
|
|
|
|
TRI = MF.getSubtarget().getRegisterInfo();
|
2016-06-08 20:31:16 +08:00
|
|
|
MDT = &getAnalysis<MachineDominatorTree>();
|
2015-03-31 21:35:12 +08:00
|
|
|
LIS = &getAnalysis<LiveIntervals>();
|
|
|
|
MRI = &MF.getRegInfo();
|
2016-06-08 20:31:16 +08:00
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(LIS->print(dbgs() << "Before expand-condsets\n",
|
|
|
|
MF.getFunction().getParent()));
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
bool Changed = false;
|
2016-10-28 23:50:22 +08:00
|
|
|
std::set<unsigned> CoalUpd, PredUpd;
|
|
|
|
|
|
|
|
SmallVector<MachineInstr*,16> Condsets;
|
|
|
|
for (auto &B : MF)
|
|
|
|
for (auto &I : B)
|
|
|
|
if (isCondset(I))
|
|
|
|
Condsets.push_back(&I);
|
2015-03-31 21:35:12 +08:00
|
|
|
|
|
|
|
// Try to coalesce the target of a mux with one of its sources.
|
|
|
|
// This could eliminate a register copy in some circumstances.
|
2016-10-28 23:50:22 +08:00
|
|
|
Changed |= coalesceSegments(Condsets, CoalUpd);
|
|
|
|
|
|
|
|
// Update kill flags on all source operands. This is done here because
|
|
|
|
// at this moment (when expand-condsets runs), there are no kill flags
|
|
|
|
// in the IR (they have been removed by live range analysis).
|
|
|
|
// Updating them right before we split is the easiest, because splitting
|
|
|
|
// adds definitions which would interfere with updating kills afterwards.
|
|
|
|
std::set<unsigned> KillUpd;
|
|
|
|
for (MachineInstr *MI : Condsets)
|
|
|
|
for (MachineOperand &Op : MI->operands())
|
|
|
|
if (Op.isReg() && Op.isUse())
|
|
|
|
if (!CoalUpd.count(Op.getReg()))
|
|
|
|
KillUpd.insert(Op.getReg());
|
|
|
|
updateLiveness(KillUpd, false, true, false);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(
|
|
|
|
LIS->print(dbgs() << "After coalescing\n", MF.getFunction().getParent()));
|
2015-03-31 21:35:12 +08:00
|
|
|
|
2016-06-08 20:31:16 +08:00
|
|
|
// First, simply split all muxes into a pair of conditional transfers
|
|
|
|
// and update the live intervals to reflect the new arrangement. The
|
|
|
|
// goal is to update the kill flags, since predication will rely on
|
|
|
|
// them.
|
2016-10-28 23:50:22 +08:00
|
|
|
for (MachineInstr *MI : Condsets)
|
|
|
|
Changed |= split(*MI, PredUpd);
|
|
|
|
Condsets.clear(); // The contents of Condsets are invalid here anyway.
|
|
|
|
|
|
|
|
// Do not update live ranges after splitting. Recalculation of live
|
|
|
|
// intervals removes kill flags, which were preserved by splitting on
|
|
|
|
// the source operands of condsets. These kill flags are needed by
|
|
|
|
// predication, and after splitting they are difficult to recalculate
|
|
|
|
// (because of predicated defs), so make sure they are left untouched.
|
|
|
|
// Predication does not use live intervals.
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(
|
|
|
|
LIS->print(dbgs() << "After splitting\n", MF.getFunction().getParent()));
|
2016-06-08 20:31:16 +08:00
|
|
|
|
|
|
|
// Traverse all blocks and collapse predicable instructions feeding
|
|
|
|
// conditional transfers into predicated instructions.
|
|
|
|
// Walk over all the instructions again, so we may catch pre-existing
|
|
|
|
// cases that were not created in the previous step.
|
|
|
|
for (auto &B : MF)
|
|
|
|
Changed |= predicateInBlock(B, PredUpd);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(LIS->print(dbgs() << "After predicating\n",
|
|
|
|
MF.getFunction().getParent()));
|
2016-06-08 20:31:16 +08:00
|
|
|
|
2016-10-28 23:50:22 +08:00
|
|
|
PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
|
2016-06-08 20:31:16 +08:00
|
|
|
updateLiveness(PredUpd, true, true, true);
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG({
|
2016-06-08 20:31:16 +08:00
|
|
|
if (Changed)
|
|
|
|
LIS->print(dbgs() << "After expand-condsets\n",
|
2017-12-16 06:22:58 +08:00
|
|
|
MF.getFunction().getParent());
|
2016-06-08 20:31:16 +08:00
|
|
|
});
|
2016-04-23 00:47:01 +08:00
|
|
|
|
2015-03-31 21:35:12 +08:00
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Public Constructor Functions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
FunctionPass *llvm::createHexagonExpandCondsets() {
|
|
|
|
return new HexagonExpandCondsets();
|
|
|
|
}
|