forked from OSchip/llvm-project
166 lines
3.9 KiB
LLVM
166 lines
3.9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/bmi-builtins.c
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;
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; AMD Intrinsics
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;
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define i64 @test__andn_u64(i64 %a0, i64 %a1) {
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; X64-LABEL: test__andn_u64:
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; X64: # BB#0:
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; X64-NEXT: xorq $-1, %rdi
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; X64-NEXT: andq %rsi, %rdi
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: retq
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%xor = xor i64 %a0, -1
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%res = and i64 %xor, %a1
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ret i64 %res
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}
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define i64 @test__bextr_u64(i64 %a0, i64 %a1) {
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; X64-LABEL: test__bextr_u64:
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; X64: # BB#0:
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; X64-NEXT: bextrq %rsi, %rdi, %rax
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; X64-NEXT: retq
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%res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %a1)
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ret i64 %res
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}
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define i64 @test__blsi_u64(i64 %a0) {
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; X64-LABEL: test__blsi_u64:
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; X64: # BB#0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: subq %rdi, %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%neg = sub i64 0, %a0
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%res = and i64 %a0, %neg
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ret i64 %res
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}
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define i64 @test__blsmsk_u64(i64 %a0) {
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; X64-LABEL: test__blsmsk_u64:
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; X64: # BB#0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: xorq %rdi, %rax
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; X64-NEXT: retq
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%dec = sub i64 %a0, 1
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%res = xor i64 %a0, %dec
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ret i64 %res
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}
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define i64 @test__blsr_u64(i64 %a0) {
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; X64-LABEL: test__blsr_u64:
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; X64: # BB#0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%dec = sub i64 %a0, 1
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%res = and i64 %a0, %dec
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ret i64 %res
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}
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define i64 @test__tzcnt_u64(i64 %a0) {
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; X64-LABEL: test__tzcnt_u64:
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; X64: # BB#0:
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; X64-NEXT: movl $64, %ecx
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; X64-NEXT: tzcntq %rdi, %rax
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; X64-NEXT: cmovbq %rcx, %rax
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; X64-NEXT: retq
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%cmp = icmp ne i64 %a0, 0
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%cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 true)
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%res = select i1 %cmp, i64 %cttz, i64 64
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ret i64 %res
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}
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;
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; Intel intrinsics
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;
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define i64 @test_andn_u64(i64 %a0, i64 %a1) {
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; X64-LABEL: test_andn_u64:
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; X64: # BB#0:
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; X64-NEXT: xorq $-1, %rdi
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; X64-NEXT: andq %rsi, %rdi
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: retq
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%xor = xor i64 %a0, -1
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%res = and i64 %xor, %a1
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ret i64 %res
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}
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define i64 @test_bextr_u64(i64 %a0, i32 %a1, i32 %a2) {
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; X64-LABEL: test_bextr_u64:
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; X64: # BB#0:
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; X64-NEXT: andl $255, %esi
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; X64-NEXT: andl $255, %edx
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; X64-NEXT: shll $8, %edx
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; X64-NEXT: orl %esi, %edx
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; X64-NEXT: movl %edx, %eax
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; X64-NEXT: bextrq %rax, %rdi, %rax
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; X64-NEXT: retq
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%and1 = and i32 %a1, 255
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%and2 = and i32 %a2, 255
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%shl = shl i32 %and2, 8
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%or = or i32 %and1, %shl
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%zext = zext i32 %or to i64
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%res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %zext)
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ret i64 %res
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}
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define i64 @test_blsi_u64(i64 %a0) {
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; X64-LABEL: test_blsi_u64:
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; X64: # BB#0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: subq %rdi, %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%neg = sub i64 0, %a0
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%res = and i64 %a0, %neg
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ret i64 %res
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}
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define i64 @test_blsmsk_u64(i64 %a0) {
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; X64-LABEL: test_blsmsk_u64:
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; X64: # BB#0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: xorq %rdi, %rax
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; X64-NEXT: retq
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%dec = sub i64 %a0, 1
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%res = xor i64 %a0, %dec
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ret i64 %res
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}
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define i64 @test_blsr_u64(i64 %a0) {
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; X64-LABEL: test_blsr_u64:
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; X64: # BB#0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%dec = sub i64 %a0, 1
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%res = and i64 %a0, %dec
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ret i64 %res
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}
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define i64 @test_tzcnt_u64(i64 %a0) {
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; X64-LABEL: test_tzcnt_u64:
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; X64: # BB#0:
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; X64-NEXT: movl $64, %ecx
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; X64-NEXT: tzcntq %rdi, %rax
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; X64-NEXT: cmovbq %rcx, %rax
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; X64-NEXT: retq
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%cmp = icmp ne i64 %a0, 0
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%cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 true)
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%res = select i1 %cmp, i64 %cttz, i64 64
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ret i64 %res
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}
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declare i64 @llvm.cttz.i64(i64, i1)
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declare i64 @llvm.x86.bmi.bextr.64(i64, i64)
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