2017-12-15 19:02:50 +08:00
|
|
|
// REQUIRES: aarch64
|
|
|
|
// RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
|
2019-08-20 16:34:56 +08:00
|
|
|
// RUN: ld.lld --fix-cortex-a53-843419 -z separate-code %t.o -o %t2
|
Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
|
|
|
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2162688 -stop-address=2162700 | FileCheck --check-prefix=CHECK1 %s
|
|
|
|
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2166784 -stop-address=2166788 | FileCheck --check-prefix=CHECK2 %s
|
|
|
|
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2170872 -stop-address=2170888 | FileCheck --check-prefix=CHECK3 %s
|
|
|
|
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=69287928 -stop-address=69287944 | FileCheck --check-prefix=CHECK4 %s
|
|
|
|
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=102842376 -stop-address=102842392 | FileCheck --check-prefix=CHECK5 %s
|
|
|
|
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=136384524 -stop-address=136384528 | FileCheck --check-prefix=CHECK6 %s
|
|
|
|
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=136388604 -stop-address=136388628 | FileCheck --check-prefix=CHECK7 %s
|
2017-12-15 19:02:50 +08:00
|
|
|
// Test case for Cortex-A53 Erratum 843419 in an OutputSection exceeding
|
|
|
|
// the maximum branch range. Both range extension thunks and patches are
|
Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
|
|
|
// required.
|
|
|
|
|
2017-12-15 19:02:50 +08:00
|
|
|
// CHECK1: __AArch64AbsLongThunk_need_thunk_after_patch:
|
Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
|
|
|
// CHECK1-NEXT: 210000: 50 00 00 58 ldr x16, #8
|
|
|
|
// CHECK1-NEXT: 210004: 00 02 1f d6 br x16
|
|
|
|
// CHECK1: $d:
|
|
|
|
// CHECK1-NEXT: 210008: 0c 10 21 08 .word 0x0821100c
|
|
|
|
|
2017-12-15 19:02:50 +08:00
|
|
|
.section .text.01, "ax", %progbits
|
|
|
|
.balign 4096
|
|
|
|
.globl _start
|
|
|
|
.type _start, %function
|
|
|
|
_start:
|
|
|
|
// Expect thunk on pass 2
|
|
|
|
bl need_thunk_after_patch
|
|
|
|
.section .text.02, "ax", %progbits
|
|
|
|
.space 4096 - 12
|
|
|
|
|
|
|
|
// CHECK2: _start:
|
Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
|
|
|
// CHECK2-NEXT: 211000: 00 fc ff 97 bl #-4096
|
2017-12-15 19:02:50 +08:00
|
|
|
|
|
|
|
// Expect patch on pass 1
|
|
|
|
.section .text.03, "ax", %progbits
|
|
|
|
.globl t3_ff8_ldr
|
|
|
|
.type t3_ff8_ldr, %function
|
|
|
|
t3_ff8_ldr:
|
|
|
|
adrp x0, dat
|
|
|
|
ldr x1, [x1, #0]
|
|
|
|
ldr x0, [x0, :got_lo12:dat]
|
|
|
|
ret
|
|
|
|
|
|
|
|
// CHECK3: t3_ff8_ldr:
|
[ELF] Simplify RelRo, TLS, NOBITS section ranks and make RW PT_LOAD start with RelRo
Old: PT_LOAD(.data | PT_GNU_RELRO(.data.rel.ro .bss.rel.ro) | .bss)
New: PT_LOAD(PT_GNU_RELRO(.data.rel.ro .bss.rel.ro) | .data .bss)
The placement of | indicates page alignment caused by PT_GNU_RELRO. The
new layout has simpler rules and saves space for many cases.
Old size: roundup(.data) + roundup(.data.rel.ro)
New size: roundup(.data.rel.ro + .bss.rel.ro) + .data
Other advantages:
* At runtime the 3 memory mappings decrease to 2.
* start(PT_TLS) = start(PT_GNU_RELRO) = start(RW PT_LOAD). This
simplifies binary manipulation tools.
GNU strip before 2.31 discards PT_GNU_RELRO if its
address is not equal to the start of its associated PT_LOAD.
This has been fixed by https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f2731e0c374e5323ce4cdae2bcc7b7fe22da1a6f
But with this change, we will be compatible with GNU strip before 2.31
* Before, .got.plt (non-relro by default) was placed before .got (relro
by default), which made it impossible to have _GLOBAL_OFFSET_TABLE_
(start of .got.plt on x86-64) equal to the end of .got (R_GOT*_FROM_END)
(https://bugs.llvm.org/show_bug.cgi?id=36555). With the new ordering, we
can improve on this regard if we'd like to.
Reviewers: ruiu, espindola, pcc
Subscribers: emaste, arichardson, llvm-commits, joerg, jdoerfert
Differential Revision: https://reviews.llvm.org/D56828
llvm-svn: 356117
2019-03-14 11:47:45 +08:00
|
|
|
// CHECK3-NEXT: 211ff8: e0 00 04 f0 adrp x0, #134344704
|
Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
|
|
|
// CHECK3-NEXT: 211ffc: 21 00 40 f9 ldr x1, [x1]
|
|
|
|
// CHECK3-NEXT: 212000: 02 08 80 15 b #100671496
|
|
|
|
// CHECK3-NEXT: 212004: c0 03 5f d6 ret
|
2017-12-15 19:02:50 +08:00
|
|
|
|
|
|
|
.section .text.04, "ax", %progbits
|
|
|
|
.space 64 * 1024 * 1024
|
|
|
|
|
|
|
|
// Expect patch on pass 1
|
|
|
|
.section .text.05, "ax", %progbits
|
|
|
|
.balign 4096
|
|
|
|
.space 4096 - 8
|
|
|
|
.globl t3_ff8_str
|
|
|
|
.type t3_ff8_str, %function
|
|
|
|
t3_ff8_str:
|
|
|
|
adrp x0, dat
|
|
|
|
ldr x1, [x1, #0]
|
|
|
|
str x0, [x0, :got_lo12:dat]
|
|
|
|
ret
|
|
|
|
|
|
|
|
// CHECK4: t3_ff8_str:
|
[ELF] Simplify RelRo, TLS, NOBITS section ranks and make RW PT_LOAD start with RelRo
Old: PT_LOAD(.data | PT_GNU_RELRO(.data.rel.ro .bss.rel.ro) | .bss)
New: PT_LOAD(PT_GNU_RELRO(.data.rel.ro .bss.rel.ro) | .data .bss)
The placement of | indicates page alignment caused by PT_GNU_RELRO. The
new layout has simpler rules and saves space for many cases.
Old size: roundup(.data) + roundup(.data.rel.ro)
New size: roundup(.data.rel.ro + .bss.rel.ro) + .data
Other advantages:
* At runtime the 3 memory mappings decrease to 2.
* start(PT_TLS) = start(PT_GNU_RELRO) = start(RW PT_LOAD). This
simplifies binary manipulation tools.
GNU strip before 2.31 discards PT_GNU_RELRO if its
address is not equal to the start of its associated PT_LOAD.
This has been fixed by https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f2731e0c374e5323ce4cdae2bcc7b7fe22da1a6f
But with this change, we will be compatible with GNU strip before 2.31
* Before, .got.plt (non-relro by default) was placed before .got (relro
by default), which made it impossible to have _GLOBAL_OFFSET_TABLE_
(start of .got.plt on x86-64) equal to the end of .got (R_GOT*_FROM_END)
(https://bugs.llvm.org/show_bug.cgi?id=36555). With the new ordering, we
can improve on this regard if we'd like to.
Reviewers: ruiu, espindola, pcc
Subscribers: emaste, arichardson, llvm-commits, joerg, jdoerfert
Differential Revision: https://reviews.llvm.org/D56828
llvm-svn: 356117
2019-03-14 11:47:45 +08:00
|
|
|
// CHECK4-NEXT: 4213ff8: e0 00 02 b0 adrp x0, #67227648
|
Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
|
|
|
// CHECK4-NEXT: 4213ffc: 21 00 40 f9 ldr x1, [x1]
|
|
|
|
// CHECK4-NEXT: 4214000: 04 00 80 14 b #33554448
|
|
|
|
// CHECK4-NEXT: 4214004: c0 03 5f d6 ret
|
2017-12-15 19:02:50 +08:00
|
|
|
|
|
|
|
.section .text.06, "ax", %progbits
|
|
|
|
.space 32 * 1024 * 1024
|
|
|
|
|
Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
|
|
|
// CHECK5: __CortexA53843419_211000:
|
|
|
|
// CHECK5-NEXT: 6214008: 00 00 40 f9 ldr x0, [x0]
|
|
|
|
// CHECK5-NEXT: 621400c: fe f7 7f 16 b #-100671496
|
|
|
|
// CHECK5: __CortexA53843419_4213000:
|
|
|
|
// CHECK5-NEXT: 6214010: 00 00 00 f9 str x0, [x0]
|
|
|
|
// CHECK5-NEXT: 6214014: fc ff 7f 17 b #-33554448
|
2017-12-15 19:02:50 +08:00
|
|
|
|
|
|
|
.section .text.07, "ax", %progbits
|
|
|
|
.space (32 * 1024 * 1024) - 12300
|
|
|
|
|
|
|
|
.section .text.08, "ax", %progbits
|
|
|
|
.globl need_thunk_after_patch
|
|
|
|
.type need_thunk_after_patch, %function
|
|
|
|
need_thunk_after_patch:
|
|
|
|
ret
|
|
|
|
|
|
|
|
// CHECK6: need_thunk_after_patch:
|
Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
|
|
|
// CHECK6-NEXT: 821100c: c0 03 5f d6 ret
|
2017-12-15 19:02:50 +08:00
|
|
|
|
|
|
|
// Will need a patch on pass 2
|
|
|
|
.section .text.09, "ax", %progbits
|
|
|
|
.space 4096 - 20
|
|
|
|
.globl t3_ffc_ldr
|
|
|
|
.type t3_ffc_ldr, %function
|
|
|
|
t3_ffc_ldr:
|
|
|
|
adrp x0, dat
|
|
|
|
ldr x1, [x1, #0]
|
|
|
|
ldr x0, [x0, :got_lo12:dat]
|
|
|
|
ret
|
|
|
|
|
|
|
|
// CHECK7: t3_ffc_ldr:
|
[ELF] Simplify RelRo, TLS, NOBITS section ranks and make RW PT_LOAD start with RelRo
Old: PT_LOAD(.data | PT_GNU_RELRO(.data.rel.ro .bss.rel.ro) | .bss)
New: PT_LOAD(PT_GNU_RELRO(.data.rel.ro .bss.rel.ro) | .data .bss)
The placement of | indicates page alignment caused by PT_GNU_RELRO. The
new layout has simpler rules and saves space for many cases.
Old size: roundup(.data) + roundup(.data.rel.ro)
New size: roundup(.data.rel.ro + .bss.rel.ro) + .data
Other advantages:
* At runtime the 3 memory mappings decrease to 2.
* start(PT_TLS) = start(PT_GNU_RELRO) = start(RW PT_LOAD). This
simplifies binary manipulation tools.
GNU strip before 2.31 discards PT_GNU_RELRO if its
address is not equal to the start of its associated PT_LOAD.
This has been fixed by https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f2731e0c374e5323ce4cdae2bcc7b7fe22da1a6f
But with this change, we will be compatible with GNU strip before 2.31
* Before, .got.plt (non-relro by default) was placed before .got (relro
by default), which made it impossible to have _GLOBAL_OFFSET_TABLE_
(start of .got.plt on x86-64) equal to the end of .got (R_GOT*_FROM_END)
(https://bugs.llvm.org/show_bug.cgi?id=36555). With the new ordering, we
can improve on this regard if we'd like to.
Reviewers: ruiu, espindola, pcc
Subscribers: emaste, arichardson, llvm-commits, joerg, jdoerfert
Differential Revision: https://reviews.llvm.org/D56828
llvm-svn: 356117
2019-03-14 11:47:45 +08:00
|
|
|
// CHECK7-NEXT: 8211ffc: e0 00 00 f0 adrp x0, #126976
|
Align AArch64 and i386 image base to superpage
Summary:
As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.
On AArch64, this is 2 MiB, on i386 it is 4 MiB.
Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard
Reviewed By: ruiu, peter.smith
Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50297
llvm-svn: 342746
2018-09-22 00:58:13 +08:00
|
|
|
// CHECK7-NEXT: 8212000: 21 00 40 f9 ldr x1, [x1]
|
|
|
|
// CHECK7-NEXT: 8212004: 02 00 00 14 b #8
|
|
|
|
// CHECK7-NEXT: 8212008: c0 03 5f d6 ret
|
|
|
|
// CHECK7: __CortexA53843419_8212004:
|
|
|
|
// CHECK7-NEXT: 821200c: 00 00 40 f9 ldr x0, [x0]
|
|
|
|
// CHECK7-NEXT: 8212010: fe ff ff 17 b #-8
|
2017-12-15 19:02:50 +08:00
|
|
|
|
|
|
|
.section .data
|
|
|
|
.globl dat
|
|
|
|
dat: .quad 0
|