2018-01-22 18:06:50 +08:00
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//===---- ReachingDefAnalysis.cpp - Reaching Def Analysis ---*- C++ -*-----===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2018-01-22 18:06:50 +08:00
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//
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//===----------------------------------------------------------------------===//
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2020-01-29 16:26:11 +08:00
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#include "llvm/ADT/SmallSet.h"
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2019-11-26 18:03:25 +08:00
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#include "llvm/CodeGen/LivePhysRegs.h"
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2018-01-22 18:06:50 +08:00
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#include "llvm/CodeGen/ReachingDefAnalysis.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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2019-10-19 08:22:07 +08:00
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#include "llvm/Support/Debug.h"
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2018-01-22 18:06:50 +08:00
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using namespace llvm;
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#define DEBUG_TYPE "reaching-deps-analysis"
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char ReachingDefAnalysis::ID = 0;
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INITIALIZE_PASS(ReachingDefAnalysis, DEBUG_TYPE, "ReachingDefAnalysis", false,
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true)
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2020-03-11 01:24:04 +08:00
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static bool isValidReg(const MachineOperand &MO) {
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2020-02-28 19:14:42 +08:00
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return MO.isReg() && MO.getReg();
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}
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2020-03-11 01:24:04 +08:00
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static bool isValidRegUse(const MachineOperand &MO) {
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2020-02-28 19:14:42 +08:00
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return isValidReg(MO) && MO.isUse();
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}
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2020-03-11 01:24:04 +08:00
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static bool isValidRegUseOf(const MachineOperand &MO, int PhysReg) {
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2020-02-28 19:14:42 +08:00
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return isValidRegUse(MO) && MO.getReg() == PhysReg;
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}
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2020-03-11 01:24:04 +08:00
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static bool isValidRegDef(const MachineOperand &MO) {
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2020-02-28 19:14:42 +08:00
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return isValidReg(MO) && MO.isDef();
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}
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2020-03-11 01:24:04 +08:00
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static bool isValidRegDefOf(const MachineOperand &MO, int PhysReg) {
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2020-02-28 19:14:42 +08:00
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return isValidRegDef(MO) && MO.getReg() == PhysReg;
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}
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2020-04-06 03:14:59 +08:00
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void ReachingDefAnalysis::enterBasicBlock(MachineBasicBlock *MBB) {
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2018-01-22 21:24:10 +08:00
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unsigned MBBNumber = MBB->getNumber();
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2018-01-22 18:06:50 +08:00
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assert(MBBNumber < MBBReachingDefs.size() &&
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"Unexpected basic block number.");
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MBBReachingDefs[MBBNumber].resize(NumRegUnits);
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// Reset instruction counter in each basic block.
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CurInstr = 0;
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// Set up LiveRegs to represent registers entering MBB.
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// Default values are 'nothing happened a long time ago'.
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if (LiveRegs.empty())
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2018-03-21 04:53:21 +08:00
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LiveRegs.assign(NumRegUnits, ReachingDefDefaultVal);
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2018-01-22 18:06:50 +08:00
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// This is the entry block.
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if (MBB->pred_empty()) {
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for (const auto &LI : MBB->liveins()) {
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for (MCRegUnitIterator Unit(LI.PhysReg, TRI); Unit.isValid(); ++Unit) {
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// Treat function live-ins as if they were defined just before the first
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// instruction. Usually, function arguments are set up immediately
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// before the call.
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2020-04-06 03:09:49 +08:00
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if (LiveRegs[*Unit] != -1) {
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LiveRegs[*Unit] = -1;
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MBBReachingDefs[MBBNumber][*Unit].push_back(-1);
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}
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2018-01-22 18:06:50 +08:00
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}
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}
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
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2018-01-22 18:06:50 +08:00
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return;
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}
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock *pred : MBB->predecessors()) {
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2018-01-22 21:24:10 +08:00
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assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&
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2018-01-22 18:06:50 +08:00
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"Should have pre-allocated MBBInfos for all MBBs");
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const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming.empty())
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continue;
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[RDA] Only store most recent reaching def from predecessors (NFCI)
When entering a basic block, RDA inserts reaching definitions coming
from predecessor blocks (which will be negative numbers) in a rather
peculiar way. If you have incoming reaching definitions -4, -3, -2, -1,
it will insert those. If you have incoming reaching definitions
-1, -2, -3, -4, it will insert -1, -1, -1, -1, as the max is taken
at each step. That's probably not what was intended...
However, RDA only actually cares about the most recent reaching
definition from a predecessor (to calculate clearance), so this
ends up working fine as far as behavior is concerned. It does
waste memory on unnecessary reaching definitions though.
This patch changes the implementation to first compute the most
recent reaching definition in one loop, and then insert only that
one in a separate loop.
Differential Revision: https://reviews.llvm.org/D77508
2020-04-05 06:46:20 +08:00
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// Find the most recent reaching definition from a predecessor.
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit)
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2018-01-22 18:06:50 +08:00
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LiveRegs[Unit] = std::max(LiveRegs[Unit], Incoming[Unit]);
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}
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[RDA] Only store most recent reaching def from predecessors (NFCI)
When entering a basic block, RDA inserts reaching definitions coming
from predecessor blocks (which will be negative numbers) in a rather
peculiar way. If you have incoming reaching definitions -4, -3, -2, -1,
it will insert those. If you have incoming reaching definitions
-1, -2, -3, -4, it will insert -1, -1, -1, -1, as the max is taken
at each step. That's probably not what was intended...
However, RDA only actually cares about the most recent reaching
definition from a predecessor (to calculate clearance), so this
ends up working fine as far as behavior is concerned. It does
waste memory on unnecessary reaching definitions though.
This patch changes the implementation to first compute the most
recent reaching definition in one loop, and then insert only that
one in a separate loop.
Differential Revision: https://reviews.llvm.org/D77508
2020-04-05 06:46:20 +08:00
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// Insert the most recent reaching definition we found.
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit)
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if (LiveRegs[Unit] != ReachingDefDefaultVal)
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MBBReachingDefs[MBBNumber][Unit].push_back(LiveRegs[Unit]);
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2018-01-22 18:06:50 +08:00
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}
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2020-04-06 03:14:59 +08:00
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void ReachingDefAnalysis::leaveBasicBlock(MachineBasicBlock *MBB) {
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2018-01-22 18:06:50 +08:00
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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2020-04-06 03:14:59 +08:00
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unsigned MBBNumber = MBB->getNumber();
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2018-01-22 18:06:50 +08:00
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assert(MBBNumber < MBBOutRegsInfos.size() &&
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"Unexpected basic block number.");
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// Save register clearances at end of MBB - used by enterBasicBlock().
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MBBOutRegsInfos[MBBNumber] = LiveRegs;
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// While processing the basic block, we kept `Def` relative to the start
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// of the basic block for convenience. However, future use of this information
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// only cares about the clearance from the end of the block, so adjust
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// everything to be relative to the end of the basic block.
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for (int &OutLiveReg : MBBOutRegsInfos[MBBNumber])
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2020-04-06 01:16:56 +08:00
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if (OutLiveReg != ReachingDefDefaultVal)
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OutLiveReg -= CurInstr;
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2018-01-22 18:06:50 +08:00
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LiveRegs.clear();
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}
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void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
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2018-05-09 10:42:00 +08:00
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assert(!MI->isDebugInstr() && "Won't process debug instructions");
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2018-01-22 18:06:50 +08:00
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2018-01-22 21:24:10 +08:00
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unsigned MBBNumber = MI->getParent()->getNumber();
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2018-01-22 18:06:50 +08:00
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assert(MBBNumber < MBBReachingDefs.size() &&
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"Unexpected basic block number.");
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2020-02-28 19:14:42 +08:00
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for (auto &MO : MI->operands()) {
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if (!isValidRegDef(MO))
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2018-01-22 18:06:50 +08:00
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continue;
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for (MCRegUnitIterator Unit(MO.getReg(), TRI); Unit.isValid(); ++Unit) {
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// This instruction explicitly defines the current reg unit.
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2020-04-06 03:09:49 +08:00
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LLVM_DEBUG(dbgs() << printReg(*Unit, TRI) << ":\t" << CurInstr
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2018-05-14 20:53:11 +08:00
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<< '\t' << *MI);
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2018-01-22 18:06:50 +08:00
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// How many instructions since this reg unit was last written?
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2020-04-06 03:09:49 +08:00
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if (LiveRegs[*Unit] != CurInstr) {
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LiveRegs[*Unit] = CurInstr;
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MBBReachingDefs[MBBNumber][*Unit].push_back(CurInstr);
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}
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2018-01-22 18:06:50 +08:00
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}
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}
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InstIds[MI] = CurInstr;
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++CurInstr;
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}
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2020-04-05 06:22:54 +08:00
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void ReachingDefAnalysis::reprocessBasicBlock(MachineBasicBlock *MBB) {
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unsigned MBBNumber = MBB->getNumber();
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assert(MBBNumber < MBBReachingDefs.size() &&
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"Unexpected basic block number.");
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// Count number of non-debug instructions for end of block adjustment.
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2020-08-07 16:49:09 +08:00
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auto NonDbgInsts =
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instructionsWithoutDebug(MBB->instr_begin(), MBB->instr_end());
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int NumInsts = std::distance(NonDbgInsts.begin(), NonDbgInsts.end());
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2020-04-05 06:22:54 +08:00
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// When reprocessing a block, the only thing we need to do is check whether
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// there is now a more recent incoming reaching definition from a predecessor.
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for (MachineBasicBlock *pred : MBB->predecessors()) {
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assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming may be empty for dead predecessors.
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if (Incoming.empty())
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continue;
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {
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int Def = Incoming[Unit];
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if (Def == ReachingDefDefaultVal)
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continue;
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auto Start = MBBReachingDefs[MBBNumber][Unit].begin();
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if (Start != MBBReachingDefs[MBBNumber][Unit].end() && *Start < 0) {
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if (*Start >= Def)
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continue;
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// Update existing reaching def from predecessor to a more recent one.
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*Start = Def;
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} else {
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// Insert new reaching def from predecessor.
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MBBReachingDefs[MBBNumber][Unit].insert(Start, Def);
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}
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// Update reaching def at end of of BB. Keep in mind that these are
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// adjusted relative to the end of the basic block.
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if (MBBOutRegsInfos[MBBNumber][Unit] < Def - NumInsts)
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MBBOutRegsInfos[MBBNumber][Unit] = Def - NumInsts;
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}
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}
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}
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2018-01-22 18:06:50 +08:00
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void ReachingDefAnalysis::processBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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2020-04-06 03:14:59 +08:00
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MachineBasicBlock *MBB = TraversedMBB.MBB;
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LLVM_DEBUG(dbgs() << printMBBReference(*MBB)
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<< (!TraversedMBB.IsDone ? ": incomplete\n"
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: ": all preds known\n"));
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2020-04-05 06:22:54 +08:00
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if (!TraversedMBB.PrimaryPass) {
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// Reprocess MBB that is part of a loop.
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reprocessBasicBlock(MBB);
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return;
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}
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2020-04-06 03:14:59 +08:00
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enterBasicBlock(MBB);
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2020-08-07 16:49:09 +08:00
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for (MachineInstr &MI :
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instructionsWithoutDebug(MBB->instr_begin(), MBB->instr_end()))
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processDefs(&MI);
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2020-04-06 03:14:59 +08:00
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leaveBasicBlock(MBB);
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2018-01-22 18:06:50 +08:00
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}
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bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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TRI = MF->getSubtarget().getRegisterInfo();
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2020-02-20 22:58:08 +08:00
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LLVM_DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n");
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init();
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traverse();
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return false;
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}
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2018-01-22 18:06:50 +08:00
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2020-02-20 22:58:08 +08:00
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void ReachingDefAnalysis::releaseMemory() {
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// Clear the internal vectors.
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MBBOutRegsInfos.clear();
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MBBReachingDefs.clear();
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InstIds.clear();
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2018-01-22 18:06:50 +08:00
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LiveRegs.clear();
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2020-02-20 22:58:08 +08:00
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}
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2018-01-22 18:06:50 +08:00
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2020-02-20 22:58:08 +08:00
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void ReachingDefAnalysis::reset() {
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releaseMemory();
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init();
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traverse();
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}
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2018-01-22 18:06:50 +08:00
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2020-02-20 22:58:08 +08:00
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void ReachingDefAnalysis::init() {
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NumRegUnits = TRI->getNumRegUnits();
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MBBReachingDefs.resize(MF->getNumBlockIDs());
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2018-01-22 18:06:50 +08:00
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// Initialize the MBBOutRegsInfos
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2020-02-20 22:58:08 +08:00
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MBBOutRegsInfos.resize(MF->getNumBlockIDs());
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LoopTraversal Traversal;
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TraversedMBBOrder = Traversal.traverse(*MF);
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}
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2018-01-22 18:06:50 +08:00
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2020-02-20 22:58:08 +08:00
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void ReachingDefAnalysis::traverse() {
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2018-01-22 18:06:50 +08:00
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// Traverse the basic blocks.
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2020-02-20 22:58:08 +08:00
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for (LoopTraversal::TraversedMBBInfo TraversedMBB : TraversedMBBOrder)
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2018-01-22 18:06:50 +08:00
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processBasicBlock(TraversedMBB);
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2020-04-05 06:22:54 +08:00
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#ifndef NDEBUG
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// Make sure reaching defs are sorted and unique.
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2018-01-22 18:06:50 +08:00
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for (MBBDefsInfo &MBBDefs : MBBReachingDefs) {
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2020-04-05 06:22:54 +08:00
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for (MBBRegUnitDefs &RegUnitDefs : MBBDefs) {
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int LastDef = ReachingDefDefaultVal;
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for (int Def : RegUnitDefs) {
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assert(Def > LastDef && "Defs must be sorted and unique");
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LastDef = Def;
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}
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}
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2018-01-22 18:06:50 +08:00
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}
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2020-04-05 06:22:54 +08:00
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#endif
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2018-01-22 18:06:50 +08:00
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}
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2020-01-23 21:22:13 +08:00
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int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) const {
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2018-01-22 18:06:50 +08:00
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assert(InstIds.count(MI) && "Unexpected machine instuction.");
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2020-01-23 21:22:13 +08:00
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int InstId = InstIds.lookup(MI);
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2018-03-21 04:53:21 +08:00
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int DefRes = ReachingDefDefaultVal;
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2018-01-22 21:24:10 +08:00
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unsigned MBBNumber = MI->getParent()->getNumber();
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2018-01-22 18:06:50 +08:00
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assert(MBBNumber < MBBReachingDefs.size() &&
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"Unexpected basic block number.");
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2018-03-21 04:53:21 +08:00
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int LatestDef = ReachingDefDefaultVal;
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2018-01-22 18:06:50 +08:00
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for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
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for (int Def : MBBReachingDefs[MBBNumber][*Unit]) {
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if (Def >= InstId)
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break;
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DefRes = Def;
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}
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LatestDef = std::max(LatestDef, DefRes);
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}
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return LatestDef;
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}
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|
|
2020-02-26 19:14:54 +08:00
|
|
|
MachineInstr* ReachingDefAnalysis::getReachingLocalMIDef(MachineInstr *MI,
|
2020-08-25 15:35:07 +08:00
|
|
|
int PhysReg) const {
|
|
|
|
return hasLocalDefBefore(MI, PhysReg)
|
|
|
|
? getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg))
|
|
|
|
: nullptr;
|
2019-11-26 18:03:25 +08:00
|
|
|
}
|
|
|
|
|
2019-11-26 18:25:04 +08:00
|
|
|
bool ReachingDefAnalysis::hasSameReachingDef(MachineInstr *A, MachineInstr *B,
|
2020-01-23 21:22:13 +08:00
|
|
|
int PhysReg) const {
|
2019-11-26 18:25:04 +08:00
|
|
|
MachineBasicBlock *ParentA = A->getParent();
|
|
|
|
MachineBasicBlock *ParentB = B->getParent();
|
|
|
|
if (ParentA != ParentB)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return getReachingDef(A, PhysReg) == getReachingDef(B, PhysReg);
|
|
|
|
}
|
|
|
|
|
2019-11-26 18:03:25 +08:00
|
|
|
MachineInstr *ReachingDefAnalysis::getInstFromId(MachineBasicBlock *MBB,
|
2020-01-23 21:22:13 +08:00
|
|
|
int InstId) const {
|
2019-11-26 18:25:04 +08:00
|
|
|
assert(static_cast<size_t>(MBB->getNumber()) < MBBReachingDefs.size() &&
|
2019-11-26 18:03:25 +08:00
|
|
|
"Unexpected basic block number.");
|
|
|
|
assert(InstId < static_cast<int>(MBB->size()) &&
|
|
|
|
"Unexpected instruction id.");
|
|
|
|
|
|
|
|
if (InstId < 0)
|
|
|
|
return nullptr;
|
|
|
|
|
|
|
|
for (auto &MI : *MBB) {
|
2020-02-06 22:13:31 +08:00
|
|
|
auto F = InstIds.find(&MI);
|
|
|
|
if (F != InstIds.end() && F->second == InstId)
|
2019-11-26 18:03:25 +08:00
|
|
|
return &MI;
|
|
|
|
}
|
2020-02-06 22:13:31 +08:00
|
|
|
|
2019-11-26 18:03:25 +08:00
|
|
|
return nullptr;
|
|
|
|
}
|
|
|
|
|
2020-01-23 21:22:13 +08:00
|
|
|
int
|
|
|
|
ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) const {
|
2018-01-22 18:06:50 +08:00
|
|
|
assert(InstIds.count(MI) && "Unexpected machine instuction.");
|
2020-01-23 21:22:13 +08:00
|
|
|
return InstIds.lookup(MI) - getReachingDef(MI, PhysReg);
|
2018-01-22 18:06:50 +08:00
|
|
|
}
|
2019-11-26 18:03:25 +08:00
|
|
|
|
2020-01-29 16:26:11 +08:00
|
|
|
bool
|
|
|
|
ReachingDefAnalysis::hasLocalDefBefore(MachineInstr *MI, int PhysReg) const {
|
|
|
|
return getReachingDef(MI, PhysReg) >= 0;
|
|
|
|
}
|
|
|
|
|
2019-11-26 18:25:04 +08:00
|
|
|
void ReachingDefAnalysis::getReachingLocalUses(MachineInstr *Def, int PhysReg,
|
2020-01-28 21:06:07 +08:00
|
|
|
InstSet &Uses) const {
|
2019-11-26 18:25:04 +08:00
|
|
|
MachineBasicBlock *MBB = Def->getParent();
|
|
|
|
MachineBasicBlock::iterator MI = MachineBasicBlock::iterator(Def);
|
|
|
|
while (++MI != MBB->end()) {
|
2020-01-24 00:44:25 +08:00
|
|
|
if (MI->isDebugInstr())
|
|
|
|
continue;
|
|
|
|
|
2019-12-20 17:32:36 +08:00
|
|
|
// If/when we find a new reaching def, we know that there's no more uses
|
|
|
|
// of 'Def'.
|
2020-02-26 19:14:54 +08:00
|
|
|
if (getReachingLocalMIDef(&*MI, PhysReg) != Def)
|
2019-12-20 17:32:36 +08:00
|
|
|
return;
|
|
|
|
|
2019-11-26 18:25:04 +08:00
|
|
|
for (auto &MO : MI->operands()) {
|
2020-02-28 19:14:42 +08:00
|
|
|
if (!isValidRegUseOf(MO, PhysReg))
|
2019-11-26 18:25:04 +08:00
|
|
|
continue;
|
|
|
|
|
2020-01-17 21:08:24 +08:00
|
|
|
Uses.insert(&*MI);
|
2019-11-26 18:25:04 +08:00
|
|
|
if (MO.isKill())
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2019-11-26 18:03:25 +08:00
|
|
|
|
2020-01-23 21:22:13 +08:00
|
|
|
bool
|
|
|
|
ReachingDefAnalysis::getLiveInUses(MachineBasicBlock *MBB, int PhysReg,
|
2020-01-28 21:06:07 +08:00
|
|
|
InstSet &Uses) const {
|
2020-08-07 16:49:09 +08:00
|
|
|
for (MachineInstr &MI :
|
|
|
|
instructionsWithoutDebug(MBB->instr_begin(), MBB->instr_end())) {
|
2020-01-17 21:08:24 +08:00
|
|
|
for (auto &MO : MI.operands()) {
|
2020-02-28 19:14:42 +08:00
|
|
|
if (!isValidRegUseOf(MO, PhysReg))
|
2020-01-17 21:08:24 +08:00
|
|
|
continue;
|
|
|
|
if (getReachingDef(&MI, PhysReg) >= 0)
|
|
|
|
return false;
|
|
|
|
Uses.insert(&MI);
|
|
|
|
}
|
|
|
|
}
|
2020-10-10 21:50:25 +08:00
|
|
|
auto Last = MBB->getLastNonDebugInstr();
|
|
|
|
if (Last == MBB->end())
|
|
|
|
return true;
|
|
|
|
return isReachingDefLiveOut(&*Last, PhysReg);
|
2020-01-17 21:08:24 +08:00
|
|
|
}
|
|
|
|
|
2020-01-23 21:22:13 +08:00
|
|
|
void
|
|
|
|
ReachingDefAnalysis::getGlobalUses(MachineInstr *MI, int PhysReg,
|
2020-01-28 21:06:07 +08:00
|
|
|
InstSet &Uses) const {
|
2020-01-17 21:08:24 +08:00
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
|
|
|
|
// Collect the uses that each def touches within the block.
|
|
|
|
getReachingLocalUses(MI, PhysReg, Uses);
|
|
|
|
|
|
|
|
// Handle live-out values.
|
|
|
|
if (auto *LiveOut = getLocalLiveOutMIDef(MI->getParent(), PhysReg)) {
|
|
|
|
if (LiveOut != MI)
|
|
|
|
return;
|
|
|
|
|
|
|
|
SmallVector<MachineBasicBlock*, 4> ToVisit;
|
|
|
|
ToVisit.insert(ToVisit.begin(), MBB->successors().begin(),
|
|
|
|
MBB->successors().end());
|
|
|
|
SmallPtrSet<MachineBasicBlock*, 4>Visited;
|
|
|
|
while (!ToVisit.empty()) {
|
|
|
|
MachineBasicBlock *MBB = ToVisit.back();
|
|
|
|
ToVisit.pop_back();
|
|
|
|
if (Visited.count(MBB) || !MBB->isLiveIn(PhysReg))
|
|
|
|
continue;
|
|
|
|
if (getLiveInUses(MBB, PhysReg, Uses))
|
|
|
|
ToVisit.insert(ToVisit.end(), MBB->successors().begin(),
|
|
|
|
MBB->successors().end());
|
|
|
|
Visited.insert(MBB);
|
|
|
|
}
|
|
|
|
}
|
2019-11-26 18:03:25 +08:00
|
|
|
}
|
|
|
|
|
2020-08-28 20:56:16 +08:00
|
|
|
void
|
|
|
|
ReachingDefAnalysis::getGlobalReachingDefs(MachineInstr *MI, int PhysReg,
|
|
|
|
InstSet &Defs) const {
|
|
|
|
if (auto *Def = getUniqueReachingMIDef(MI, PhysReg)) {
|
|
|
|
Defs.insert(Def);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (auto *MBB : MI->getParent()->predecessors())
|
|
|
|
getLiveOuts(MBB, PhysReg, Defs);
|
|
|
|
}
|
|
|
|
|
2020-07-01 15:27:12 +08:00
|
|
|
void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB, int PhysReg,
|
|
|
|
InstSet &Defs) const {
|
|
|
|
SmallPtrSet<MachineBasicBlock*, 2> VisitedBBs;
|
|
|
|
getLiveOuts(MBB, PhysReg, Defs, VisitedBBs);
|
|
|
|
}
|
|
|
|
|
2020-02-26 19:14:54 +08:00
|
|
|
void
|
|
|
|
ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB, int PhysReg,
|
|
|
|
InstSet &Defs, BlockSet &VisitedBBs) const {
|
|
|
|
if (VisitedBBs.count(MBB))
|
|
|
|
return;
|
|
|
|
|
|
|
|
VisitedBBs.insert(MBB);
|
|
|
|
LivePhysRegs LiveRegs(*TRI);
|
|
|
|
LiveRegs.addLiveOuts(*MBB);
|
|
|
|
if (!LiveRegs.contains(PhysReg))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (auto *Def = getLocalLiveOutMIDef(MBB, PhysReg))
|
|
|
|
Defs.insert(Def);
|
|
|
|
else
|
|
|
|
for (auto *Pred : MBB->predecessors())
|
|
|
|
getLiveOuts(Pred, PhysReg, Defs, VisitedBBs);
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstr *ReachingDefAnalysis::getUniqueReachingMIDef(MachineInstr *MI,
|
|
|
|
int PhysReg) const {
|
|
|
|
// If there's a local def before MI, return it.
|
|
|
|
MachineInstr *LocalDef = getReachingLocalMIDef(MI, PhysReg);
|
2020-03-03 23:19:57 +08:00
|
|
|
if (LocalDef && InstIds.lookup(LocalDef) < InstIds.lookup(MI))
|
2020-02-26 19:14:54 +08:00
|
|
|
return LocalDef;
|
|
|
|
|
|
|
|
SmallPtrSet<MachineInstr*, 2> Incoming;
|
2020-08-26 18:11:15 +08:00
|
|
|
MachineBasicBlock *Parent = MI->getParent();
|
|
|
|
for (auto *Pred : Parent->predecessors())
|
2020-09-16 19:42:58 +08:00
|
|
|
getLiveOuts(Pred, PhysReg, Incoming);
|
2020-02-26 19:14:54 +08:00
|
|
|
|
2020-09-16 19:42:58 +08:00
|
|
|
// Check that we have a single incoming value and that it does not
|
|
|
|
// come from the same block as MI - since it would mean that the def
|
|
|
|
// is executed after MI.
|
|
|
|
if (Incoming.size() == 1 && (*Incoming.begin())->getParent() != Parent)
|
2020-02-26 19:14:54 +08:00
|
|
|
return *Incoming.begin();
|
2020-09-16 19:42:58 +08:00
|
|
|
return nullptr;
|
2020-02-26 19:14:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI,
|
|
|
|
unsigned Idx) const {
|
|
|
|
assert(MI->getOperand(Idx).isReg() && "Expected register operand");
|
|
|
|
return getUniqueReachingMIDef(MI, MI->getOperand(Idx).getReg());
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI,
|
|
|
|
MachineOperand &MO) const {
|
|
|
|
assert(MO.isReg() && "Expected register operand");
|
|
|
|
return getUniqueReachingMIDef(MI, MO.getReg());
|
|
|
|
}
|
|
|
|
|
2020-01-23 21:22:13 +08:00
|
|
|
bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI, int PhysReg) const {
|
2019-11-26 18:03:25 +08:00
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
LivePhysRegs LiveRegs(*TRI);
|
|
|
|
LiveRegs.addLiveOuts(*MBB);
|
|
|
|
|
|
|
|
// Yes if the register is live out of the basic block.
|
|
|
|
if (LiveRegs.contains(PhysReg))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Walk backwards through the block to see if the register is live at some
|
|
|
|
// point.
|
2020-08-07 16:49:09 +08:00
|
|
|
for (MachineInstr &Last :
|
|
|
|
instructionsWithoutDebug(MBB->instr_rbegin(), MBB->instr_rend())) {
|
|
|
|
LiveRegs.stepBackward(Last);
|
2019-11-26 18:03:25 +08:00
|
|
|
if (LiveRegs.contains(PhysReg))
|
2020-08-07 16:49:09 +08:00
|
|
|
return InstIds.lookup(&Last) > InstIds.lookup(MI);
|
2019-11-26 18:03:25 +08:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2020-01-29 16:26:11 +08:00
|
|
|
bool ReachingDefAnalysis::isRegDefinedAfter(MachineInstr *MI,
|
|
|
|
int PhysReg) const {
|
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
2020-10-10 21:50:25 +08:00
|
|
|
auto Last = MBB->getLastNonDebugInstr();
|
|
|
|
if (Last != MBB->end() &&
|
|
|
|
getReachingDef(MI, PhysReg) != getReachingDef(&*Last, PhysReg))
|
2020-01-29 16:26:11 +08:00
|
|
|
return true;
|
|
|
|
|
|
|
|
if (auto *Def = getLocalLiveOutMIDef(MBB, PhysReg))
|
2020-02-26 19:14:54 +08:00
|
|
|
return Def == getReachingLocalMIDef(MI, PhysReg);
|
2020-01-29 16:26:11 +08:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2020-01-23 21:22:13 +08:00
|
|
|
bool
|
|
|
|
ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI, int PhysReg) const {
|
2019-12-20 17:32:36 +08:00
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
LivePhysRegs LiveRegs(*TRI);
|
|
|
|
LiveRegs.addLiveOuts(*MBB);
|
|
|
|
if (!LiveRegs.contains(PhysReg))
|
|
|
|
return false;
|
|
|
|
|
2020-10-10 21:50:25 +08:00
|
|
|
auto Last = MBB->getLastNonDebugInstr();
|
2019-12-20 17:32:36 +08:00
|
|
|
int Def = getReachingDef(MI, PhysReg);
|
2020-10-10 21:50:25 +08:00
|
|
|
if (Last != MBB->end() && getReachingDef(&*Last, PhysReg) != Def)
|
2019-12-20 17:32:36 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Finally check that the last instruction doesn't redefine the register.
|
|
|
|
for (auto &MO : Last->operands())
|
2020-02-28 19:14:42 +08:00
|
|
|
if (isValidRegDefOf(MO, PhysReg))
|
2019-12-20 17:32:36 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstr* ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB,
|
2020-01-23 21:22:13 +08:00
|
|
|
int PhysReg) const {
|
2019-12-20 17:32:36 +08:00
|
|
|
LivePhysRegs LiveRegs(*TRI);
|
|
|
|
LiveRegs.addLiveOuts(*MBB);
|
|
|
|
if (!LiveRegs.contains(PhysReg))
|
|
|
|
return nullptr;
|
|
|
|
|
2020-10-10 21:50:25 +08:00
|
|
|
auto Last = MBB->getLastNonDebugInstr();
|
|
|
|
if (Last == MBB->end())
|
|
|
|
return nullptr;
|
|
|
|
|
|
|
|
int Def = getReachingDef(&*Last, PhysReg);
|
2019-12-20 17:32:36 +08:00
|
|
|
for (auto &MO : Last->operands())
|
2020-02-28 19:14:42 +08:00
|
|
|
if (isValidRegDefOf(MO, PhysReg))
|
2020-10-10 21:50:25 +08:00
|
|
|
return &*Last;
|
2019-12-20 17:32:36 +08:00
|
|
|
|
|
|
|
return Def < 0 ? nullptr : getInstFromId(MBB, Def);
|
|
|
|
}
|
2020-01-29 16:26:11 +08:00
|
|
|
|
2020-02-06 21:53:09 +08:00
|
|
|
static bool mayHaveSideEffects(MachineInstr &MI) {
|
|
|
|
return MI.mayLoadOrStore() || MI.mayRaiseFPException() ||
|
|
|
|
MI.hasUnmodeledSideEffects() || MI.isTerminator() ||
|
|
|
|
MI.isCall() || MI.isBarrier() || MI.isBranch() || MI.isReturn();
|
|
|
|
}
|
|
|
|
|
2020-01-29 16:26:11 +08:00
|
|
|
// Can we safely move 'From' to just before 'To'? To satisfy this, 'From' must
|
|
|
|
// not define a register that is used by any instructions, after and including,
|
|
|
|
// 'To'. These instructions also must not redefine any of Froms operands.
|
|
|
|
template<typename Iterator>
|
|
|
|
bool ReachingDefAnalysis::isSafeToMove(MachineInstr *From,
|
|
|
|
MachineInstr *To) const {
|
2020-09-28 22:46:56 +08:00
|
|
|
if (From->getParent() != To->getParent() || From == To)
|
2020-01-29 16:26:11 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
SmallSet<int, 2> Defs;
|
|
|
|
// First check that From would compute the same value if moved.
|
|
|
|
for (auto &MO : From->operands()) {
|
2020-02-28 19:14:42 +08:00
|
|
|
if (!isValidReg(MO))
|
2020-01-29 16:26:11 +08:00
|
|
|
continue;
|
|
|
|
if (MO.isDef())
|
|
|
|
Defs.insert(MO.getReg());
|
|
|
|
else if (!hasSameReachingDef(From, To, MO.getReg()))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Now walk checking that the rest of the instructions will compute the same
|
2020-02-06 21:53:09 +08:00
|
|
|
// value and that we're not overwriting anything. Don't move the instruction
|
2020-04-29 05:50:52 +08:00
|
|
|
// past any memory, control-flow or other ambiguous instructions.
|
2020-01-29 16:26:11 +08:00
|
|
|
for (auto I = ++Iterator(From), E = Iterator(To); I != E; ++I) {
|
2020-02-06 21:53:09 +08:00
|
|
|
if (mayHaveSideEffects(*I))
|
|
|
|
return false;
|
2020-01-29 16:26:11 +08:00
|
|
|
for (auto &MO : I->operands())
|
2020-02-06 21:53:09 +08:00
|
|
|
if (MO.isReg() && MO.getReg() && Defs.count(MO.getReg()))
|
2020-01-29 16:26:11 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ReachingDefAnalysis::isSafeToMoveForwards(MachineInstr *From,
|
|
|
|
MachineInstr *To) const {
|
2020-09-28 22:46:56 +08:00
|
|
|
using Iterator = MachineBasicBlock::iterator;
|
|
|
|
// Walk forwards until we find the instruction.
|
|
|
|
for (auto I = Iterator(From), E = From->getParent()->end(); I != E; ++I)
|
|
|
|
if (&*I == To)
|
|
|
|
return isSafeToMove<Iterator>(From, To);
|
|
|
|
return false;
|
2020-01-29 16:26:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ReachingDefAnalysis::isSafeToMoveBackwards(MachineInstr *From,
|
|
|
|
MachineInstr *To) const {
|
2020-09-28 22:46:56 +08:00
|
|
|
using Iterator = MachineBasicBlock::reverse_iterator;
|
|
|
|
// Walk backwards until we find the instruction.
|
|
|
|
for (auto I = Iterator(From), E = From->getParent()->rend(); I != E; ++I)
|
|
|
|
if (&*I == To)
|
|
|
|
return isSafeToMove<Iterator>(From, To);
|
|
|
|
return false;
|
2020-01-29 16:26:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI,
|
|
|
|
InstSet &ToRemove) const {
|
|
|
|
SmallPtrSet<MachineInstr*, 1> Ignore;
|
|
|
|
SmallPtrSet<MachineInstr*, 2> Visited;
|
|
|
|
return isSafeToRemove(MI, Visited, ToRemove, Ignore);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI, InstSet &ToRemove,
|
|
|
|
InstSet &Ignore) const {
|
|
|
|
SmallPtrSet<MachineInstr*, 2> Visited;
|
|
|
|
return isSafeToRemove(MI, Visited, ToRemove, Ignore);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI, InstSet &Visited,
|
|
|
|
InstSet &ToRemove, InstSet &Ignore) const {
|
|
|
|
if (Visited.count(MI) || Ignore.count(MI))
|
|
|
|
return true;
|
2020-02-06 21:53:09 +08:00
|
|
|
else if (mayHaveSideEffects(*MI)) {
|
2020-01-29 16:26:11 +08:00
|
|
|
// Unless told to ignore the instruction, don't remove anything which has
|
|
|
|
// side effects.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
Visited.insert(MI);
|
|
|
|
for (auto &MO : MI->operands()) {
|
2020-02-28 19:14:42 +08:00
|
|
|
if (!isValidRegDef(MO))
|
2020-01-29 16:26:11 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
SmallPtrSet<MachineInstr*, 4> Uses;
|
|
|
|
getGlobalUses(MI, MO.getReg(), Uses);
|
|
|
|
|
|
|
|
for (auto I : Uses) {
|
|
|
|
if (Ignore.count(I) || ToRemove.count(I))
|
|
|
|
continue;
|
|
|
|
if (!isSafeToRemove(I, Visited, ToRemove, Ignore))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ToRemove.insert(MI);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2020-03-03 23:19:57 +08:00
|
|
|
void ReachingDefAnalysis::collectKilledOperands(MachineInstr *MI,
|
|
|
|
InstSet &Dead) const {
|
2020-02-24 21:50:46 +08:00
|
|
|
Dead.insert(MI);
|
2020-02-27 18:54:08 +08:00
|
|
|
auto IsDead = [this, &Dead](MachineInstr *Def, int PhysReg) {
|
2020-09-30 16:36:57 +08:00
|
|
|
if (mayHaveSideEffects(*Def))
|
|
|
|
return false;
|
|
|
|
|
2020-02-24 21:50:46 +08:00
|
|
|
unsigned LiveDefs = 0;
|
2020-02-28 19:14:42 +08:00
|
|
|
for (auto &MO : Def->operands()) {
|
|
|
|
if (!isValidRegDef(MO))
|
|
|
|
continue;
|
2020-02-24 21:50:46 +08:00
|
|
|
if (!MO.isDead())
|
|
|
|
++LiveDefs;
|
2020-02-28 19:14:42 +08:00
|
|
|
}
|
2020-02-24 21:50:46 +08:00
|
|
|
|
|
|
|
if (LiveDefs > 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SmallPtrSet<MachineInstr*, 4> Uses;
|
|
|
|
getGlobalUses(Def, PhysReg, Uses);
|
2020-02-27 18:54:08 +08:00
|
|
|
for (auto *Use : Uses)
|
|
|
|
if (!Dead.count(Use))
|
|
|
|
return false;
|
|
|
|
return true;
|
2020-02-24 21:50:46 +08:00
|
|
|
};
|
|
|
|
|
2020-02-28 19:14:42 +08:00
|
|
|
for (auto &MO : MI->operands()) {
|
2020-03-03 23:19:57 +08:00
|
|
|
if (!isValidRegUse(MO))
|
2020-02-24 21:50:46 +08:00
|
|
|
continue;
|
2020-03-03 23:19:57 +08:00
|
|
|
if (MachineInstr *Def = getMIOperand(MI, MO))
|
2020-02-24 21:50:46 +08:00
|
|
|
if (IsDead(Def, MO.getReg()))
|
2020-03-03 23:19:57 +08:00
|
|
|
collectKilledOperands(Def, Dead);
|
2020-02-24 21:50:46 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-01-29 16:26:11 +08:00
|
|
|
bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI,
|
|
|
|
int PhysReg) const {
|
|
|
|
SmallPtrSet<MachineInstr*, 1> Ignore;
|
|
|
|
return isSafeToDefRegAt(MI, PhysReg, Ignore);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI, int PhysReg,
|
|
|
|
InstSet &Ignore) const {
|
|
|
|
// Check for any uses of the register after MI.
|
|
|
|
if (isRegUsedAfter(MI, PhysReg)) {
|
2020-02-26 19:14:54 +08:00
|
|
|
if (auto *Def = getReachingLocalMIDef(MI, PhysReg)) {
|
2020-01-29 16:26:11 +08:00
|
|
|
SmallPtrSet<MachineInstr*, 2> Uses;
|
2020-09-30 19:25:06 +08:00
|
|
|
getGlobalUses(Def, PhysReg, Uses);
|
2020-01-29 16:26:11 +08:00
|
|
|
for (auto *Use : Uses)
|
|
|
|
if (!Ignore.count(Use))
|
|
|
|
return false;
|
|
|
|
} else
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
// Check for any defs after MI.
|
|
|
|
if (isRegDefinedAfter(MI, PhysReg)) {
|
|
|
|
auto I = MachineBasicBlock::iterator(MI);
|
|
|
|
for (auto E = MBB->end(); I != E; ++I) {
|
|
|
|
if (Ignore.count(&*I))
|
|
|
|
continue;
|
|
|
|
for (auto &MO : I->operands())
|
2020-02-28 19:14:42 +08:00
|
|
|
if (isValidRegDefOf(MO, PhysReg))
|
2020-01-29 16:26:11 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|