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llvm-project/llvm/test/CodeGen/ARM/tail-opts.ll

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ARM Darwin default relocation model is PIC. This matches clang, so default options in llc and friends are now closer to clang's defaults. llvm-svn: 140863
2011-10-01 01:41:35 +08:00
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic -mcpu=cortex-a8 -asm-verbose=false | FileCheck %s
Tail duplication still needs to iterate. Duplicating new instructions onto the tail of a block may make that block a new candidate for duplication. llvm-svn: 89264
2009-11-19 06:52:37 +08:00
declare void @bar(i32)
declare void @car(i32)
declare void @dar(i32)
declare void @ear(i32)
declare void @far(i32)
declare i1 @qux()
@GHJK = global i32 0
Delete useless trailing semicolons. llvm-svn: 92740
2010-01-06 01:55:26 +08:00
declare i8* @choose(i8*, i8*)
Tail duplication still needs to iterate. Duplicating new instructions onto the tail of a block may make that block a new candidate for duplication. llvm-svn: 89264
2009-11-19 06:52:37 +08:00
; BranchFolding should tail-duplicate the indirect jump to avoid
; redundant branching.
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LABEL: tail_duplicate_me:
Tail duplication still needs to iterate. Duplicating new instructions onto the tail of a block may make that block a new candidate for duplication. llvm-svn: 89264
2009-11-19 06:52:37 +08:00
; CHECK: qux
Last round of fixes for movw + movt global address codegen. 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
2011-01-22 02:55:51 +08:00
; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK
; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK
Tail duplication still needs to iterate. Duplicating new instructions onto the tail of a block may make that block a new candidate for duplication. llvm-svn: 89264
2009-11-19 06:52:37 +08:00
; CHECK: str r
; CHECK-NEXT: bx r
Flip the new block-placement pass to be on by default. This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. llvm-svn: 154816
2012-04-16 21:49:17 +08:00
; CHECK: qux
Last round of fixes for movw + movt global address codegen. 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
2011-01-22 02:55:51 +08:00
; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK
; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK
Tail duplication still needs to iterate. Duplicating new instructions onto the tail of a block may make that block a new candidate for duplication. llvm-svn: 89264
2009-11-19 06:52:37 +08:00
; CHECK: str r
; CHECK-NEXT: bx r
Last round of fixes for movw + movt global address codegen. 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
2011-01-22 02:55:51 +08:00
; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK
; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK
Tail duplication still needs to iterate. Duplicating new instructions onto the tail of a block may make that block a new candidate for duplication. llvm-svn: 89264
2009-11-19 06:52:37 +08:00
; CHECK: str r
; CHECK-NEXT: bx r
define void @tail_duplicate_me() nounwind {
entry:
%a = call i1 @qux()
%c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return),
i8* blockaddress(@tail_duplicate_me, %altret))
br i1 %a, label %A, label %next
next:
%b = call i1 @qux()
br i1 %b, label %B, label %C
A:
call void @bar(i32 0)
store i32 0, i32* @GHJK
br label %M
B:
call void @car(i32 1)
store i32 0, i32* @GHJK
br label %M
C:
call void @dar(i32 2)
store i32 0, i32* @GHJK
br label %M
M:
indirectbr i8* %c, [label %return, label %altret]
return:
call void @ear(i32 1000)
ret void
altret:
call void @far(i32 1001)
ret void
}
[BranchFolding] Tail common all identical unreachable blocks Summary: Blocks ending in unreachable are typically cold because they end the program or throw an exception, so merging them with other identical blocks is usually profitable because it reduces the size of cold code. MachineBlockPlacement generally does not arrange to fall through to such blocks, so commoning these blocks will not introduce additional unconditional branches. Reviewers: hans, iteratee, haicheng Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29153 llvm-svn: 295105
2017-02-15 05:02:24 +08:00
; Use alternating abort functions so that the blocks we wish to merge are not
; layout successors during branch folding.
; CHECK-LABEL: merge_alternating_aborts:
; CHECK-NOT: _abort
; CHECK-NOT: _alt_abort
; CHECK: bxne lr
; CHECK-NOT: _abort
; CHECK-NOT: _alt_abort
; CHECK: LBB{{.*}}:
; CHECK: mov lr, pc
; CHECK: b _alt_abort
; CHECK-NOT: _abort
; CHECK-NOT: _alt_abort
; CHECK: LBB{{.*}}:
; CHECK: mov lr, pc
; CHECK: b _abort
; CHECK-NOT: _abort
; CHECK-NOT: _alt_abort
declare void @abort()
declare void @alt_abort()
define void @merge_alternating_aborts() {
entry:
%c1 = call i1 @qux()
br i1 %c1, label %cont1, label %abort1
abort1:
call void @abort()
unreachable
cont1:
%c2 = call i1 @qux()
br i1 %c2, label %cont2, label %abort2
abort2:
call void @alt_abort()
unreachable
cont2:
%c3 = call i1 @qux()
br i1 %c3, label %cont3, label %abort3
abort3:
call void @abort()
unreachable
cont3:
%c4 = call i1 @qux()
br i1 %c4, label %cont4, label %abort4
abort4:
call void @alt_abort()
unreachable
cont4:
ret void
}