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llvm-project/llvm/test/CodeGen/X86/pr16031.ll

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Use autogenerate check in CodeGen/X86/pr16031.ll . NFC llvm-svn: 294761
2017-02-11 01:26:21 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx -enable-misched=false | FileCheck %s
X86: Bad peephole interaction between adc, MOV32r0 The peephole tries to reorder MOV32r0 instructions such that they are before the instruction that modifies EFLAGS. The problem is that the peephole does not consider the case where the instruction that modifies EFLAGS also depends on the previous state of EFLAGS. Instead, walk backwards until we find an instruction that has a def for EFLAGS but does not have a use. If we find such an instruction, insert the MOV32r0 before it. If it cannot find such an instruction, skip the optimization. llvm-svn: 182184
2013-05-18 09:02:03 +08:00
define i64 @main(i1 %tobool1) nounwind {
Use autogenerate check in CodeGen/X86/pr16031.ll . NFC llvm-svn: 294761
2017-02-11 01:26:21 +08:00
; CHECK-LABEL: main:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $-12, %eax
; CHECK-NEXT: movl $-1, %edx
; CHECK-NEXT: cmovel %edx, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: addl $-1, %esi
; CHECK-NEXT: movl $-1, %esi
; CHECK-NEXT: adcl $-1, %esi
; CHECK-NEXT: cmovsl %ecx, %eax
; CHECK-NEXT: cmovsl %ecx, %edx
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
X86: Bad peephole interaction between adc, MOV32r0 The peephole tries to reorder MOV32r0 instructions such that they are before the instruction that modifies EFLAGS. The problem is that the peephole does not consider the case where the instruction that modifies EFLAGS also depends on the previous state of EFLAGS. Instead, walk backwards until we find an instruction that has a def for EFLAGS but does not have a use. If we find such an instruction, insert the MOV32r0 before it. If it cannot find such an instruction, skip the optimization. llvm-svn: 182184
2013-05-18 09:02:03 +08:00
entry:
%0 = zext i1 %tobool1 to i32
%. = xor i32 %0, 1
%.21 = select i1 %tobool1, i32 -12, i32 -1
%conv = sext i32 %.21 to i64
%1 = add i64 %conv, -1
%cmp10 = icmp slt i64 %1, 0
%sub17 = select i1 %cmp10, i64 0, i64 %conv
ret i64 %sub17
}