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llvm-project/llvm/test/CodeGen/PowerPC/stfiwx-2.ll

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Add triple to test/CodeGen/PowerPC/stfiwx-2 llvm-svn: 178486
2013-04-02 02:18:44 +08:00
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 | FileCheck %s
Fix a latent bug exposed by my truncstore patch. We compiled stfiwx-2.ll to: _test: fctiwz f0, f1 stfiwx f0, 0, r4 blr instead of: _test: fctiwz f0, f1 stfd f0, -8(r1) nop nop lwz r2, -4(r1) stb r2, 0(r4) blr The former is not correct (stores 4 bytes, not 1). llvm-svn: 46161
2008-01-19 00:54:56 +08:00
define void @test(float %F, i8* %P) {
%I = fptosi float %F to i32
%X = trunc i32 %I to i8
store i8 %X, i8* %P
ret void
Add more PPC floating-point conversion instructions The P7 and A2 have additional floating-point conversion instructions which allow a direct two-instruction sequence (plus load/store) to convert from all combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores, only some combinations were directly available). llvm-svn: 178480
2013-04-02 01:52:07 +08:00
; CHECK: fctiwz 0, 1
; CHECK: stfiwx 0, 0, 4
; CHECK: lwz 4, 12(1)
; CHECK: stb 4, 0(3)
; CHECK: blr
Fix a latent bug exposed by my truncstore patch. We compiled stfiwx-2.ll to: _test: fctiwz f0, f1 stfiwx f0, 0, r4 blr instead of: _test: fctiwz f0, f1 stfd f0, -8(r1) nop nop lwz r2, -4(r1) stb r2, 0(r4) blr The former is not correct (stores 4 bytes, not 1). llvm-svn: 46161
2008-01-19 00:54:56 +08:00
}