2014-07-03 04:53:48 +08:00
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//===-- SIFixSGPRLiveRanges.cpp - Fix SGPR live ranges ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2015-08-15 08:12:30 +08:00
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/// \file SALU instructions ignore the execution mask, so we need to modify the
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/// live ranges of the registers they define in some cases.
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2014-07-03 04:53:48 +08:00
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///
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2014-09-24 09:33:24 +08:00
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/// The main case we need to handle is when a def is used in one side of a
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/// branch and not another. For example:
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///
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/// %def
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/// IF
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/// ...
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/// ...
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/// ELSE
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/// %use
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/// ...
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/// ENDIF
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///
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/// Here we need the register allocator to avoid assigning any of the defs
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/// inside of the IF to the same register as %def. In traditional live
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/// interval analysis %def is not live inside the IF branch, however, since
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/// SALU instructions inside of IF will be executed even if the branch is not
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/// taken, there is the chance that one of the instructions will overwrite the
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/// value of %def, so the use in ELSE will see the wrong value.
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///
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/// The strategy we use for solving this is to add an extra use after the ENDIF:
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///
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/// %def
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/// IF
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/// ...
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/// ...
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/// ELSE
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/// %use
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/// ...
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/// ENDIF
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/// %use
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///
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2015-08-09 02:27:36 +08:00
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/// Adding this use will make the def live throughout the IF branch, which is
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2014-09-24 09:33:24 +08:00
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/// what we want.
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2014-07-03 04:53:48 +08:00
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#include "AMDGPU.h"
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2014-09-24 09:33:24 +08:00
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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2015-08-22 08:43:38 +08:00
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#include "llvm/ADT/DepthFirstIterator.h"
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2014-07-03 04:53:48 +08:00
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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2015-08-15 08:12:37 +08:00
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#include "llvm/CodeGen/LiveVariables.h"
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2014-07-03 04:53:48 +08:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2014-09-24 09:33:24 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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2014-07-03 04:53:48 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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2015-03-24 03:32:43 +08:00
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#include "llvm/Support/raw_ostream.h"
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2014-07-03 04:53:48 +08:00
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-fix-sgpr-live-ranges"
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namespace {
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class SIFixSGPRLiveRanges : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIFixSGPRLiveRanges() : MachineFunctionPass(ID) {
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initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry());
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}
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2014-08-31 00:48:34 +08:00
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bool runOnMachineFunction(MachineFunction &MF) override;
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2014-07-03 04:53:48 +08:00
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2014-08-31 00:48:34 +08:00
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const char *getPassName() const override {
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2014-07-03 04:53:48 +08:00
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return "SI Fix SGPR live ranges";
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}
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2014-08-31 00:48:34 +08:00
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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2015-10-02 06:10:03 +08:00
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AU.addRequired<LiveVariables>();
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AU.addPreserved<LiveVariables>();
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2014-09-24 09:33:24 +08:00
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AU.addRequired<MachinePostDominatorTree>();
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2015-10-02 06:10:03 +08:00
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AU.addPreserved<MachinePostDominatorTree>();
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AU.setPreservesCFG();
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2014-07-03 04:53:48 +08:00
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SIFixSGPRLiveRanges, DEBUG_TYPE,
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"SI Fix SGPR Live Ranges", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveVariables)
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INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
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INITIALIZE_PASS_END(SIFixSGPRLiveRanges, DEBUG_TYPE,
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"SI Fix SGPR Live Ranges", false, false)
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char SIFixSGPRLiveRanges::ID = 0;
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char &llvm::SIFixSGPRLiveRangesID = SIFixSGPRLiveRanges::ID;
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FunctionPass *llvm::createSIFixSGPRLiveRangesPass() {
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return new SIFixSGPRLiveRanges();
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}
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bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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2014-09-24 09:33:24 +08:00
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
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MF.getSubtarget().getRegisterInfo());
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2015-08-27 03:12:03 +08:00
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bool MadeChange = false;
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2015-08-15 08:12:37 +08:00
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MachinePostDominatorTree *PDT = &getAnalysis<MachinePostDominatorTree>();
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2015-10-02 06:10:03 +08:00
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SmallVector<unsigned, 16> SGPRLiveRanges;
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2014-09-24 09:33:24 +08:00
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2015-10-02 06:10:03 +08:00
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LiveVariables *LV = &getAnalysis<LiveVariables>();
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2015-10-14 04:07:10 +08:00
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MachineBasicBlock *Entry = &MF.front();
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2015-08-15 08:12:37 +08:00
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2015-08-22 08:43:38 +08:00
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// Use a depth first order so that in SSA, we encounter all defs before
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// uses. Once the defs of the block have been found, attempt to insert
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// SGPR_USE instructions in successor blocks if required.
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for (MachineBasicBlock *MBB : depth_first(Entry)) {
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for (const MachineInstr &MI : *MBB) {
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2014-09-24 09:33:24 +08:00
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for (const MachineOperand &MO : MI.defs()) {
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2015-10-02 06:10:03 +08:00
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// We should never see a live out def of a physical register, so we also
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// do not need to worry about implicit_defs().
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2014-09-24 09:33:24 +08:00
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unsigned Def = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Def)) {
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if (TRI->isSGPRClass(MRI.getRegClass(Def))) {
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// Only consider defs that are live outs. We don't care about def /
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// use within the same block.
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2015-10-02 06:10:03 +08:00
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// LiveVariables does not consider registers that are only used in a
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// phi in a sucessor block as live out, unlike LiveIntervals.
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//
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// This is OK because SIFixSGPRCopies replaced any SGPR phis with
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// VGPRs.
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if (LV->isLiveOut(Def, *MBB))
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SGPRLiveRanges.push_back(Def);
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}
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2014-09-24 09:33:24 +08:00
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}
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}
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}
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2014-07-03 04:53:48 +08:00
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2015-08-22 08:43:38 +08:00
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if (MBB->succ_size() < 2)
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continue;
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2015-08-15 08:12:30 +08:00
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// We have structured control flow, so the number of successors should be
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// two.
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2015-08-22 08:43:38 +08:00
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assert(MBB->succ_size() == 2);
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MachineBasicBlock *SuccA = *MBB->succ_begin();
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MachineBasicBlock *SuccB = *(++MBB->succ_begin());
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2014-09-24 09:33:24 +08:00
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MachineBasicBlock *NCD = PDT->findNearestCommonDominator(SuccA, SuccB);
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if (!NCD)
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continue;
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MachineBasicBlock::iterator NCDTerm = NCD->getFirstTerminator();
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if (NCDTerm != NCD->end() && NCDTerm->getOpcode() == AMDGPU::SI_ELSE) {
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assert(NCD->succ_size() == 2);
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// We want to make sure we insert the Use after the ENDIF, not after
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// the ELSE.
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NCD = PDT->findNearestCommonDominator(*NCD->succ_begin(),
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*(++NCD->succ_begin()));
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}
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2015-08-15 08:12:32 +08:00
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2015-10-02 06:10:03 +08:00
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for (unsigned Reg : SGPRLiveRanges) {
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2015-08-15 08:12:30 +08:00
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// FIXME: We could be smarter here. If the register is Live-In to one
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// block, but the other doesn't have any SGPR defs, then there won't be a
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// conflict. Also, if the branch condition is uniform then there will be
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// no conflict.
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bool LiveInToA = LV->isLiveIn(Reg, *SuccA);
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bool LiveInToB = LV->isLiveIn(Reg, *SuccB);
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2014-09-24 09:33:24 +08:00
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2015-08-22 08:19:25 +08:00
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if (!LiveInToA && !LiveInToB) {
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DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
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<< " is live into neither successor\n");
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2014-07-03 04:53:48 +08:00
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continue;
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}
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if (LiveInToA && LiveInToB) {
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DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
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<< " is live into both successors\n");
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continue;
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}
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2014-07-03 04:53:48 +08:00
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2014-09-24 09:33:24 +08:00
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// This interval is live in to one successor, but not the other, so
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// we need to update its range so it is live in to both.
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2015-08-22 08:19:25 +08:00
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DEBUG(dbgs() << "Possible SGPR conflict detected for "
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2015-10-02 06:10:03 +08:00
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<< PrintReg(Reg, TRI, 0)
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<< " BB#" << SuccA->getNumber()
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<< ", BB#" << SuccB->getNumber()
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2015-08-22 08:19:25 +08:00
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<< " with NCD = BB#" << NCD->getNumber() << '\n');
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2014-09-24 09:33:24 +08:00
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2015-08-15 08:12:37 +08:00
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assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
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"Not expecting to extend live range of physreg");
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2014-09-24 09:33:24 +08:00
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// FIXME: Need to figure out how to update LiveRange here so this pass
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// will be able to preserve LiveInterval analysis.
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2015-08-15 08:12:35 +08:00
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MachineInstr *NCDSGPRUse =
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BuildMI(*NCD, NCD->getFirstNonPHI(), DebugLoc(),
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TII->get(AMDGPU::SGPR_USE))
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.addReg(Reg, RegState::Implicit);
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2015-08-27 03:12:03 +08:00
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MadeChange = true;
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2015-10-02 06:10:03 +08:00
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LV->HandleVirtRegUse(Reg, NCD, NCDSGPRUse);
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2015-08-15 08:12:37 +08:00
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2015-08-15 08:12:35 +08:00
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DEBUG(NCDSGPRUse->dump());
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2014-07-03 04:53:48 +08:00
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}
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}
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2015-08-27 03:12:03 +08:00
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return MadeChange;
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2014-07-03 04:53:48 +08:00
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}
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