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llvm-project/clang/test/CodeGen/sse-builtins.c

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[X86] Remove the mm_malloc.h include guard hack from the X86 builtins tests The X86 clang/test/CodeGen/*builtins.c tests define the mm_malloc.h include guard as a hack for avoiding its inclusion (mm_malloc.h requires a hosted environment since it expects stdlib.h to be available - which is not the case in these internal clang codegen tests). This patch removes this hack and instead passes -ffreestanding to clang cc1. Differential Revision: https://reviews.llvm.org/D24825 llvm-svn: 282581
2016-09-28 19:59:09 +08:00
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +sse -emit-llvm -o - -Wall -Werror | FileCheck %s
Tweak *mmintrin.h so that they don't make any bad assumptions about alignment (which probably has little effect in practice, but better to get it right). Make the load in _mm_loadh_pi and _mm_loadl_pi a single LLVM IR instruction to make optimizing easier for CodeGen. rdar://10054986 llvm-svn: 139874
2011-09-16 07:15:27 +08:00
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
#include <x86intrin.h>
// NOTE: This should match the tests in llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
Tweak *mmintrin.h so that they don't make any bad assumptions about alignment (which probably has little effect in practice, but better to get it right). Make the load in _mm_loadh_pi and _mm_loadl_pi a single LLVM IR instruction to make optimizing easier for CodeGen. rdar://10054986 llvm-svn: 139874
2011-09-16 07:15:27 +08:00
[X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file llvm-svn: 269852
2016-05-18 06:03:31 +08:00
__m128 test_mm_add_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_add_ps
// CHECK: fadd <4 x float>
return _mm_add_ps(A, B);
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_add_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_add_ss
// CHECK: extractelement <4 x float> %{{.*}}, i32 0
// CHECK: extractelement <4 x float> %{{.*}}, i32 0
// CHECK: fadd float
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
return _mm_add_ss(A, B);
}
[X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file llvm-svn: 269852
2016-05-18 06:03:31 +08:00
__m128 test_mm_and_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_and_ps
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: and <4 x i32>
[X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file llvm-svn: 269852
2016-05-18 06:03:31 +08:00
return _mm_and_ps(A, B);
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_andnot_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_andnot_ps
// CHECK: xor <4 x i32> %{{.*}}, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: and <4 x i32>
return _mm_andnot_ps(A, B);
}
__m128 test_mm_cmpeq_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpeq_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp oeq <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpeq_ps(__a, __b);
}
__m128 test_mm_cmpeq_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpeq_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 0)
return _mm_cmpeq_ss(__a, __b);
}
__m128 test_mm_cmpge_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpge_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp ole <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpge_ps(__a, __b);
}
__m128 test_mm_cmpge_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpge_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 2)
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
return _mm_cmpge_ss(__a, __b);
}
__m128 test_mm_cmpgt_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpgt_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp olt <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpgt_ps(__a, __b);
}
__m128 test_mm_cmpgt_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpgt_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 1)
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
return _mm_cmpgt_ss(__a, __b);
}
__m128 test_mm_cmple_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmple_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp ole <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmple_ps(__a, __b);
}
__m128 test_mm_cmple_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmple_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 2)
return _mm_cmple_ss(__a, __b);
}
__m128 test_mm_cmplt_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmplt_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp olt <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmplt_ps(__a, __b);
}
__m128 test_mm_cmplt_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmplt_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 1)
return _mm_cmplt_ss(__a, __b);
}
__m128 test_mm_cmpneq_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpneq_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp une <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpneq_ps(__a, __b);
}
__m128 test_mm_cmpneq_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpneq_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 4)
return _mm_cmpneq_ss(__a, __b);
}
__m128 test_mm_cmpnge_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpnge_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp ugt <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpnge_ps(__a, __b);
}
__m128 test_mm_cmpnge_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpnge_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 6)
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
return _mm_cmpnge_ss(__a, __b);
}
__m128 test_mm_cmpngt_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpngt_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp uge <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpngt_ps(__a, __b);
}
__m128 test_mm_cmpngt_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpngt_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 5)
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
return _mm_cmpngt_ss(__a, __b);
}
__m128 test_mm_cmpnle_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpnle_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp ugt <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpnle_ps(__a, __b);
}
__m128 test_mm_cmpnle_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpnle_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 6)
return _mm_cmpnle_ss(__a, __b);
}
__m128 test_mm_cmpnlt_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpnlt_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp uge <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpnlt_ps(__a, __b);
}
__m128 test_mm_cmpnlt_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpnlt_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 5)
return _mm_cmpnlt_ss(__a, __b);
}
__m128 test_mm_cmpord_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpord_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp ord <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpord_ps(__a, __b);
}
__m128 test_mm_cmpord_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpord_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 7)
return _mm_cmpord_ss(__a, __b);
}
__m128 test_mm_cmpunord_ps(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpunord_ps
[x86] translate SSE packed FP comparison builtins to IR As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
2016-06-16 05:20:04 +08:00
// CHECK: [[CMP:%.*]] = fcmp uno <4 x float>
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
// CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[SEXT]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[BC]]
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cmpunord_ps(__a, __b);
}
__m128 test_mm_cmpunord_ss(__m128 __a, __m128 __b) {
// CHECK-LABEL: @test_mm_cmpunord_ss
// CHECK: @llvm.x86.sse.cmp.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i8 3)
return _mm_cmpunord_ss(__a, __b);
}
int test_mm_comieq_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_comieq_ss
// CHECK: call i32 @llvm.x86.sse.comieq.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_comieq_ss(A, B);
}
int test_mm_comige_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_comige_ss
// CHECK: call i32 @llvm.x86.sse.comige.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_comige_ss(A, B);
}
int test_mm_comigt_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_comigt_ss
// CHECK: call i32 @llvm.x86.sse.comigt.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_comigt_ss(A, B);
}
int test_mm_comile_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_comile_ss
// CHECK: call i32 @llvm.x86.sse.comile.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_comile_ss(A, B);
}
int test_mm_comilt_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_comilt_ss
// CHECK: call i32 @llvm.x86.sse.comilt.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_comilt_ss(A, B);
}
int test_mm_comineq_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_comineq_ss
// CHECK: call i32 @llvm.x86.sse.comineq.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_comineq_ss(A, B);
}
int test_mm_cvt_ss2si(__m128 A) {
// CHECK-LABEL: test_mm_cvt_ss2si
// CHECK: call i32 @llvm.x86.sse.cvtss2si(<4 x float> %{{.*}})
return _mm_cvt_ss2si(A);
}
__m128 test_mm_cvtsi32_ss(__m128 A, int B) {
// CHECK-LABEL: test_mm_cvtsi32_ss
// CHECK: sitofp i32 %{{.*}} to float
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
return _mm_cvtsi32_ss(A, B);
}
__m128 test_mm_cvtsi64_ss(__m128 A, long long B) {
// CHECK-LABEL: test_mm_cvtsi64_ss
// CHECK: sitofp i64 %{{.*}} to float
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
return _mm_cvtsi64_ss(A, B);
}
float test_mm_cvtss_f32(__m128 A) {
// CHECK-LABEL: test_mm_cvtss_f32
// CHECK: extractelement <4 x float> %{{.*}}, i32 0
return _mm_cvtss_f32(A);
}
int test_mm_cvtss_si32(__m128 A) {
// CHECK-LABEL: test_mm_cvtss_si32
// CHECK: call i32 @llvm.x86.sse.cvtss2si(<4 x float> %{{.*}})
return _mm_cvtss_si32(A);
}
long long test_mm_cvtss_si64(__m128 A) {
// CHECK-LABEL: test_mm_cvtss_si64
// CHECK: call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %{{.*}})
return _mm_cvtss_si64(A);
}
int test_mm_cvtt_ss2si(__m128 A) {
// CHECK-LABEL: test_mm_cvtt_ss2si
[X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using generic IR D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and VCVTTPD2DQ truncating conversions with generic IR instead. It turns out that the behaviour of these intrinsics is different enough from generic IR that this will cause problems, INF/NAN/out of range values are guaranteed to result in a 0x80000000 value - which plays havoc with constant folding which converts them to either zero or UNDEF. This is also an issue with the scalar implementations (which were already generic IR and what I was trying to match). This patch changes both scalar and packed versions back to using x86-specific builtins. It also deals with the other scalar conversion cases that are runtime rounding mode dependent and can have similar issues with constant folding. Differential Revision: https://reviews.llvm.org/D22105 llvm-svn: 276102
2016-07-20 18:18:01 +08:00
// CHECK: call i32 @llvm.x86.sse.cvttss2si(<4 x float> %{{.*}})
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cvtt_ss2si(A);
}
int test_mm_cvttss_si32(__m128 A) {
// CHECK-LABEL: test_mm_cvttss_si32
[X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using generic IR D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and VCVTTPD2DQ truncating conversions with generic IR instead. It turns out that the behaviour of these intrinsics is different enough from generic IR that this will cause problems, INF/NAN/out of range values are guaranteed to result in a 0x80000000 value - which plays havoc with constant folding which converts them to either zero or UNDEF. This is also an issue with the scalar implementations (which were already generic IR and what I was trying to match). This patch changes both scalar and packed versions back to using x86-specific builtins. It also deals with the other scalar conversion cases that are runtime rounding mode dependent and can have similar issues with constant folding. Differential Revision: https://reviews.llvm.org/D22105 llvm-svn: 276102
2016-07-20 18:18:01 +08:00
// CHECK: call i32 @llvm.x86.sse.cvttss2si(<4 x float> %{{.*}})
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cvttss_si32(A);
}
long long test_mm_cvttss_si64(__m128 A) {
// CHECK-LABEL: test_mm_cvttss_si64
[X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using generic IR D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and VCVTTPD2DQ truncating conversions with generic IR instead. It turns out that the behaviour of these intrinsics is different enough from generic IR that this will cause problems, INF/NAN/out of range values are guaranteed to result in a 0x80000000 value - which plays havoc with constant folding which converts them to either zero or UNDEF. This is also an issue with the scalar implementations (which were already generic IR and what I was trying to match). This patch changes both scalar and packed versions back to using x86-specific builtins. It also deals with the other scalar conversion cases that are runtime rounding mode dependent and can have similar issues with constant folding. Differential Revision: https://reviews.llvm.org/D22105 llvm-svn: 276102
2016-07-20 18:18:01 +08:00
// CHECK: call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %{{.*}})
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_cvttss_si64(A);
}
[X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file llvm-svn: 269852
2016-05-18 06:03:31 +08:00
__m128 test_mm_div_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_div_ps
// CHECK: fdiv <4 x float>
return _mm_div_ps(A, B);
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_div_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_div_ss
// CHECK: extractelement <4 x float> %{{.*}}, i32 0
// CHECK: extractelement <4 x float> %{{.*}}, i32 0
// CHECK: fdiv float
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
return _mm_div_ss(A, B);
}
unsigned int test_MM_GET_EXCEPTION_MASK() {
// CHECK-LABEL: test_MM_GET_EXCEPTION_MASK
// CHECK: call void @llvm.x86.sse.stmxcsr(i8* %{{.*}})
// CHECK: and i32 %{{.*}}, 8064
return _MM_GET_EXCEPTION_MASK();
}
unsigned int test_MM_GET_EXCEPTION_STATE() {
// CHECK-LABEL: test_MM_GET_EXCEPTION_STATE
// CHECK: call void @llvm.x86.sse.stmxcsr(i8* %{{.*}})
// CHECK: and i32 %{{.*}}, 63
return _MM_GET_EXCEPTION_STATE();
}
unsigned int test_MM_GET_FLUSH_ZERO_MODE() {
// CHECK-LABEL: test_MM_GET_FLUSH_ZERO_MODE
// CHECK: call void @llvm.x86.sse.stmxcsr(i8* %{{.*}})
// CHECK: and i32 %{{.*}}, 32768
return _MM_GET_FLUSH_ZERO_MODE();
}
unsigned int test_MM_GET_ROUNDING_MODE() {
// CHECK-LABEL: test_MM_GET_ROUNDING_MODE
// CHECK: call void @llvm.x86.sse.stmxcsr(i8* %{{.*}})
// CHECK: and i32 %{{.*}}, 24576
return _MM_GET_ROUNDING_MODE();
}
unsigned int test_mm_getcsr() {
// CHECK-LABEL: test_mm_getcsr
// CHECK: call void @llvm.x86.sse.stmxcsr(i8* %{{.*}})
// CHECK: load i32
return _mm_getcsr();
}
__m128 test_mm_load_ps(float* y) {
// CHECK-LABEL: test_mm_load_ps
// CHECK: load <4 x float>, <4 x float>* {{.*}}, align 16
return _mm_load_ps(y);
}
__m128 test_mm_load_ps1(float* y) {
// CHECK-LABEL: test_mm_load_ps1
// CHECK: load float, float* %{{.*}}, align 4
// CHECK: insertelement <4 x float> undef, float %{{.*}}, i32 0
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 1
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 2
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 3
return _mm_load_ps1(y);
}
__m128 test_mm_load_ss(float* y) {
// CHECK-LABEL: test_mm_load_ss
[X86] Ensure load/store tests unaligned pointers really are align 1 llvm-svn: 271227
2016-05-31 03:20:55 +08:00
// CHECK: load float, float* {{.*}}, align 1{{$}}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: insertelement <4 x float> undef, float %{{.*}}, i32 0
// CHECK: insertelement <4 x float> %{{.*}}, float 0.000000e+00, i32 1
// CHECK: insertelement <4 x float> %{{.*}}, float 0.000000e+00, i32 2
// CHECK: insertelement <4 x float> %{{.*}}, float 0.000000e+00, i32 3
return _mm_load_ss(y);
}
__m128 test_mm_load1_ps(float* y) {
// CHECK-LABEL: test_mm_load1_ps
// CHECK: load float, float* %{{.*}}, align 4
// CHECK: insertelement <4 x float> undef, float %{{.*}}, i32 0
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 1
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 2
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 3
return _mm_load1_ps(y);
}
__m128 test_mm_loadh_pi(__m128 x, __m64* y) {
// CHECK-LABEL: test_mm_loadh_pi
// CHECK: load <2 x float>, <2 x float>* {{.*}}, align 1{{$}}
// CHECK: shufflevector {{.*}} <4 x i32> <i32 0, i32 1
// CHECK: shufflevector {{.*}} <4 x i32> <i32 0, i32 1, i32 4, i32 5>
return _mm_loadh_pi(x,y);
}
__m128 test_mm_loadl_pi(__m128 x, __m64* y) {
// CHECK-LABEL: test_mm_loadl_pi
// CHECK: load <2 x float>, <2 x float>* {{.*}}, align 1{{$}}
// CHECK: shufflevector {{.*}} <4 x i32> <i32 0, i32 1
// CHECK: shufflevector {{.*}} <4 x i32> <i32 4, i32 5, i32 2, i32 3>
return _mm_loadl_pi(x,y);
}
__m128 test_mm_loadr_ps(float* A) {
// CHECK-LABEL: test_mm_loadr_ps
// CHECK: load <4 x float>, <4 x float>* %{{.*}}, align 16
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
return _mm_loadr_ps(A);
}
__m128 test_mm_loadu_ps(float* A) {
// CHECK-LABEL: test_mm_loadu_ps
[X86] Ensure load/store tests unaligned pointers really are align 1 llvm-svn: 271227
2016-05-31 03:20:55 +08:00
// CHECK: load <4 x float>, <4 x float>* %{{.*}}, align 1{{$}}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
return _mm_loadu_ps(A);
}
__m128 test_mm_max_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_max_ps
// CHECK: @llvm.x86.sse.max.ps(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_max_ps(A, B);
}
__m128 test_mm_max_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_max_ss
// CHECK: @llvm.x86.sse.max.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_max_ss(A, B);
}
__m128 test_mm_min_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_min_ps
// CHECK: @llvm.x86.sse.min.ps(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_min_ps(A, B);
}
__m128 test_mm_min_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_min_ss
// CHECK: @llvm.x86.sse.min.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_min_ss(A, B);
}
__m128 test_mm_move_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_move_ss
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
return _mm_move_ss(A, B);
}
__m128 test_mm_movehl_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_movehl_ps
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
return _mm_movehl_ps(A, B);
}
__m128 test_mm_movelh_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_movelh_ps
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
return _mm_movelh_ps(A, B);
}
int test_mm_movemask_ps(__m128 A) {
// CHECK-LABEL: test_mm_movemask_ps
// CHECK: call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %{{.*}})
return _mm_movemask_ps(A);
}
[X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file llvm-svn: 269852
2016-05-18 06:03:31 +08:00
__m128 test_mm_mul_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_mul_ps
// CHECK: fmul <4 x float>
return _mm_mul_ps(A, B);
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_mul_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_mul_ss
// CHECK: extractelement <4 x float> %{{.*}}, i32 0
// CHECK: extractelement <4 x float> %{{.*}}, i32 0
// CHECK: fmul float
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
return _mm_mul_ss(A, B);
}
[X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file llvm-svn: 269852
2016-05-18 06:03:31 +08:00
__m128 test_mm_or_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_or_ps
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: or <4 x i32>
[X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file llvm-svn: 269852
2016-05-18 06:03:31 +08:00
return _mm_or_ps(A, B);
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_prefetch(char const* p) {
// CHECK-LABEL: test_mm_prefetch
// CHECK: call void @llvm.prefetch(i8* {{.*}}, i32 0, i32 0, i32 1)
_mm_prefetch(p, 0);
[X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file llvm-svn: 269852
2016-05-18 06:03:31 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_rcp_ps(__m128 x) {
// CHECK-LABEL: test_mm_rcp_ps
// CHECK: call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> {{.*}})
return _mm_rcp_ps(x);
[X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file llvm-svn: 269852
2016-05-18 06:03:31 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_rcp_ss(__m128 x) {
// CHECK-LABEL: test_mm_rcp_ss
// CHECK: call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> {{.*}})
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
// CHECK: extractelement <4 x float> {{.*}}, i32 0
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: insertelement <4 x float> undef, float {{.*}}, i32 0
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
// CHECK: extractelement <4 x float> {{.*}}, i32 1
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 1
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
// CHECK: extractelement <4 x float> {{.*}}, i32 2
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 2
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
// CHECK: extractelement <4 x float> {{.*}}, i32 3
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 3
return _mm_rcp_ss(x);
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_rsqrt_ps(__m128 x) {
// CHECK-LABEL: test_mm_rsqrt_ps
// CHECK: call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> {{.*}})
return _mm_rsqrt_ps(x);
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_rsqrt_ss(__m128 x) {
// CHECK-LABEL: test_mm_rsqrt_ss
// CHECK: call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> {{.*}})
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
// CHECK: extractelement <4 x float> {{.*}}, i32 0
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: insertelement <4 x float> undef, float {{.*}}, i32 0
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
// CHECK: extractelement <4 x float> {{.*}}, i32 1
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 1
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
// CHECK: extractelement <4 x float> {{.*}}, i32 2
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 2
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
// CHECK: extractelement <4 x float> {{.*}}, i32 3
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 3
return _mm_rsqrt_ss(x);
X86 SSE Intrinsics: update header for sqrt_ss, rsqrt_ss and rcp_ss. There intrinsics pass through the upper FP values from the input. rdar://12558838 llvm-svn: 166743
2012-10-26 08:25:10 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_MM_SET_EXCEPTION_MASK(unsigned int A) {
// CHECK-LABEL: test_MM_SET_EXCEPTION_MASK
// CHECK: call void @llvm.x86.sse.stmxcsr(i8* {{.*}})
// CHECK: load i32
// CHECK: and i32 {{.*}}, -8065
// CHECK: or i32
// CHECK: store i32
// CHECK: call void @llvm.x86.sse.ldmxcsr(i8* {{.*}})
_MM_SET_EXCEPTION_MASK(A);
}
void test_MM_SET_EXCEPTION_STATE(unsigned int A) {
// CHECK-LABEL: test_MM_SET_EXCEPTION_STATE
// CHECK: call void @llvm.x86.sse.stmxcsr(i8* {{.*}})
// CHECK: load i32
// CHECK: and i32 {{.*}}, -64
// CHECK: or i32
// CHECK: store i32
// CHECK: call void @llvm.x86.sse.ldmxcsr(i8* {{.*}})
_MM_SET_EXCEPTION_STATE(A);
Tweak *mmintrin.h so that they don't make any bad assumptions about alignment (which probably has little effect in practice, but better to get it right). Make the load in _mm_loadh_pi and _mm_loadl_pi a single LLVM IR instruction to make optimizing easier for CodeGen. rdar://10054986 llvm-svn: 139874
2011-09-16 07:15:27 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_MM_SET_FLUSH_ZERO_MODE(unsigned int A) {
// CHECK-LABEL: test_MM_SET_FLUSH_ZERO_MODE
// CHECK: call void @llvm.x86.sse.stmxcsr(i8* {{.*}})
// CHECK: load i32
// CHECK: and i32 {{.*}}, -32769
// CHECK: or i32
// CHECK: store i32
// CHECK: call void @llvm.x86.sse.ldmxcsr(i8* {{.*}})
_MM_SET_FLUSH_ZERO_MODE(A);
Tweak *mmintrin.h so that they don't make any bad assumptions about alignment (which probably has little effect in practice, but better to get it right). Make the load in _mm_loadh_pi and _mm_loadl_pi a single LLVM IR instruction to make optimizing easier for CodeGen. rdar://10054986 llvm-svn: 139874
2011-09-16 07:15:27 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_set_ps(float A, float B, float C, float D) {
// CHECK-LABEL: test_mm_set_ps
// CHECK: insertelement <4 x float> undef, float {{.*}}, i32 0
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 1
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 2
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 3
return _mm_set_ps(A, B, C, D);
Tweak *mmintrin.h so that they don't make any bad assumptions about alignment (which probably has little effect in practice, but better to get it right). Make the load in _mm_loadh_pi and _mm_loadl_pi a single LLVM IR instruction to make optimizing easier for CodeGen. rdar://10054986 llvm-svn: 139874
2011-09-16 07:15:27 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_set_ps1(float A) {
// CHECK-LABEL: test_mm_set_ps1
// CHECK: insertelement <4 x float> undef, float {{.*}}, i32 0
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 1
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 2
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 3
return _mm_set_ps1(A);
Tweak *mmintrin.h so that they don't make any bad assumptions about alignment (which probably has little effect in practice, but better to get it right). Make the load in _mm_loadh_pi and _mm_loadl_pi a single LLVM IR instruction to make optimizing easier for CodeGen. rdar://10054986 llvm-svn: 139874
2011-09-16 07:15:27 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_MM_SET_ROUNDING_MODE(unsigned int A) {
// CHECK-LABEL: test_MM_SET_ROUNDING_MODE
// CHECK: call void @llvm.x86.sse.stmxcsr(i8* {{.*}})
// CHECK: load i32
// CHECK: and i32 {{.*}}, -24577
// CHECK: or i32
// CHECK: store i32
// CHECK: call void @llvm.x86.sse.ldmxcsr(i8* {{.*}})
_MM_SET_ROUNDING_MODE(A);
Tweak *mmintrin.h so that they don't make any bad assumptions about alignment (which probably has little effect in practice, but better to get it right). Make the load in _mm_loadh_pi and _mm_loadl_pi a single LLVM IR instruction to make optimizing easier for CodeGen. rdar://10054986 llvm-svn: 139874
2011-09-16 07:15:27 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_set_ss(float A) {
// CHECK-LABEL: test_mm_set_ss
// CHECK: insertelement <4 x float> undef, float {{.*}}, i32 0
// CHECK: insertelement <4 x float> {{.*}}, float 0.000000e+00, i32 1
// CHECK: insertelement <4 x float> {{.*}}, float 0.000000e+00, i32 2
// CHECK: insertelement <4 x float> {{.*}}, float 0.000000e+00, i32 3
return _mm_set_ss(A);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_set1_ps(float A) {
// CHECK-LABEL: test_mm_set1_ps
// CHECK: insertelement <4 x float> undef, float {{.*}}, i32 0
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 1
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 2
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 3
return _mm_set1_ps(A);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_setcsr(unsigned int A) {
// CHECK-LABEL: test_mm_setcsr
// CHECK: store i32
// CHECK: call void @llvm.x86.sse.ldmxcsr(i8* {{.*}})
_mm_setcsr(A);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_setr_ps(float A, float B, float C, float D) {
// CHECK-LABEL: test_mm_setr_ps
// CHECK: insertelement <4 x float> undef, float {{.*}}, i32 0
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 1
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 2
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 3
return _mm_setr_ps(A, B, C, D);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_setzero_ps() {
// CHECK-LABEL: test_mm_setzero_ps
// CHECK: store <4 x float> zeroinitializer
return _mm_setzero_ps();
}
void test_mm_sfence() {
// CHECK-LABEL: test_mm_sfence
// CHECK: call void @llvm.x86.sse.sfence()
_mm_sfence();
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_shuffle_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_shuffle_ps
// CHECK: shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 0, i32 0, i32 4, i32 4>
return _mm_shuffle_ps(A, B, 0);
}
__m128 test_mm_sqrt_ps(__m128 x) {
// CHECK-LABEL: test_mm_sqrt_ps
// CHECK: call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> {{.*}})
return _mm_sqrt_ps(x);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_sqrt_ss(__m128 x) {
// CHECK: define {{.*}} @test_sqrt_ss
// CHECK: call <4 x float> @llvm.x86.sse.sqrt.ss
// CHECK: extractelement <4 x float> {{.*}}, i32 0
// CHECK: insertelement <4 x float> undef, float {{.*}}, i32 0
// CHECK: extractelement <4 x float> {{.*}}, i32 1
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 1
// CHECK: extractelement <4 x float> {{.*}}, i32 2
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 2
// CHECK: extractelement <4 x float> {{.*}}, i32 3
// CHECK: insertelement <4 x float> {{.*}}, float {{.*}}, i32 3
return _mm_sqrt_ss(x);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_store_ps(float* x, __m128 y) {
// CHECK-LABEL: test_mm_store_ps
// CHECK: store <4 x float> %{{.*}}, <4 x float>* {{.*}}, align 16
_mm_store_ps(x, y);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_store_ps1(float* x, __m128 y) {
// CHECK-LABEL: test_mm_store_ps1
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> zeroinitializer
[X86][SSE] Added missing tests (merge failure) Differential Revision: http://reviews.llvm.org/D20617 llvm-svn: 271219
2016-05-31 01:58:38 +08:00
// CHECK: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 16
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
_mm_store_ps1(x, y);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_store_ss(float* x, __m128 y) {
// CHECK-LABEL: test_mm_store_ss
// CHECK: extractelement <4 x float> {{.*}}, i32 0
// CHECK: store float %{{.*}}, float* {{.*}}, align 1{{$}}
_mm_store_ss(x, y);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_store1_ps(float* x, __m128 y) {
// CHECK-LABEL: test_mm_store1_ps
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> zeroinitializer
[X86][SSE] Added missing tests (merge failure) Differential Revision: http://reviews.llvm.org/D20617 llvm-svn: 271219
2016-05-31 01:58:38 +08:00
// CHECK: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 16
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
_mm_store1_ps(x, y);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_storeh_pi(__m64* x, __m128 y) {
// CHECK-LABEL: test_mm_storeh_pi
// CHECK: bitcast <4 x float> %{{.*}} to <2 x i64>
// CHECK: extractelement <2 x i64> %{{.*}}, i64 1
// CHECK: store i64 %{{.*}}, i64* {{.*}}
_mm_storeh_pi(x, y);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_storel_pi(__m64* x, __m128 y) {
// CHECK-LABEL: test_mm_storel_pi
// CHECK: bitcast <4 x float> %{{.*}} to <2 x i64>
// CHECK: extractelement <2 x i64> %{{.*}}, i64 0
// CHECK: store i64 %{{.*}}, i64* {{.*}}
_mm_storel_pi(x, y);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_storer_ps(float* x, __m128 y) {
// CHECK-LABEL: test_mm_storer_ps
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
// CHECK: store <4 x float> %{{.*}}, <4 x float>* {{.*}}, align 16
_mm_storer_ps(x, y);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_storeu_ps(float* x, __m128 y) {
// CHECK-LABEL: test_mm_storeu_ps
[X86] Replace unaligned store builtins in SSE/AVX intrinsic files with code that will compile to a native unaligned store. Remove the builtins since they are no longer used. Intrinsics will be removed from llvm in a future commit. llvm-svn: 271214
2016-05-31 01:10:30 +08:00
// CHECK: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 1{{$}}
// CHECK-NEXT: ret void
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
_mm_storeu_ps(x, y);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_mm_stream_ps(float*A, __m128d B) {
// CHECK-LABEL: test_mm_stream_ps
// CHECK: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 16, !nontemporal
_mm_stream_ps(A, B);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_sub_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_sub_ps
// CHECK: fsub <4 x float>
return _mm_sub_ps(A, B);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_sub_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_sub_ss
// CHECK: extractelement <4 x float> %{{.*}}, i32 0
// CHECK: extractelement <4 x float> %{{.*}}, i32 0
// CHECK: fsub float
// CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
return _mm_sub_ss(A, B);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
void test_MM_TRANSPOSE4_PS(__m128 *A, __m128 *B, __m128 *C, __m128 *D) {
// CHECK-LABEL: test_MM_TRANSPOSE4_PS
// CHECK: shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
// CHECK: shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
// CHECK: shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
// CHECK: shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
// CHECK: shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
// CHECK: shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
// CHECK: shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
// CHECK: shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
_MM_TRANSPOSE4_PS(*A, *B, *C, *D);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
int test_mm_ucomieq_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_ucomieq_ss
// CHECK: call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_ucomieq_ss(A, B);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
int test_mm_ucomige_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_ucomige_ss
// CHECK: call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_ucomige_ss(A, B);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
int test_mm_ucomigt_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_ucomigt_ss
// CHECK: call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_ucomigt_ss(A, B);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
int test_mm_ucomile_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_ucomile_ss
// CHECK: call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_ucomile_ss(A, B);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
int test_mm_ucomilt_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_ucomilt_ss
// CHECK: call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_ucomilt_ss(A, B);
}
int test_mm_ucomineq_ss(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_ucomineq_ss
// CHECK: call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}})
return _mm_ucomineq_ss(A, B);
[x86] Add the (v)cmpps/pd/ss/sd builtins to match gcc. Use them in the sse intrinsic files. This still lower to the same intrinsics as before. This is preparation for bounds checking the immediate on the avx version of the builtin so we don't pass illegal immediates into the backend. Since SSE uses a smaller size immediate its not possible to bounds check when using a shared builtin. Rather than creating a clang specific builtin for the different immediate, I decided (after consulting with Chandler) that it was better to match gcc. llvm-svn: 224879
2014-12-27 14:59:57 +08:00
}
[X86][SSE] Add _mm_undefined_* intrinsics Added missing SSE/AVX 'undefined' intrinsics (PR24040): _mm_undefined_pd, _mm_undefined_ps + _mm_undefined_si128 _mm256_undefined_pd, _mm256_undefined_ps + _mm256_undefined_si256 _mm512_undefined, _mm512_undefined_ps, _mm512_undefined_pd + _mm512_undefined_epi32 Added builtin intrinsicss: __builtin_ia32_undef128, __builtin_ia32_undef256 + __builtin_ia32_undef512 Differential Revision: http://reviews.llvm.org/D12052 llvm-svn: 246083
2015-08-27 05:17:12 +08:00
__m128 test_mm_undefined_ps() {
// CHECK-LABEL: @test_mm_undefined_ps
[x86] these aren't the undefs you're looking for (PR32176) x86 has undef SSE/AVX intrinsics that should represent a bogus register operand. This is not the same as LLVM's undef value which can take on multiple bit patterns. There are better solutions / follow-ups to this discussed here: https://bugs.llvm.org/show_bug.cgi?id=32176 ...but this should prevent miscompiles with a one-line code change. Differential Revision: https://reviews.llvm.org/D30834 llvm-svn: 297588
2017-03-13 03:15:10 +08:00
// CHECK: ret <4 x float> zeroinitializer
[X86][SSE] Add _mm_undefined_* intrinsics Added missing SSE/AVX 'undefined' intrinsics (PR24040): _mm_undefined_pd, _mm_undefined_ps + _mm_undefined_si128 _mm256_undefined_pd, _mm256_undefined_ps + _mm256_undefined_si256 _mm512_undefined, _mm512_undefined_ps, _mm512_undefined_pd + _mm512_undefined_epi32 Added builtin intrinsicss: __builtin_ia32_undef128, __builtin_ia32_undef256 + __builtin_ia32_undef512 Differential Revision: http://reviews.llvm.org/D12052 llvm-svn: 246083
2015-08-27 05:17:12 +08:00
return _mm_undefined_ps();
}
[X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll sse-builtins.c now just covers SSE1 intrinsics llvm-svn: 270083
2016-05-20 01:11:31 +08:00
__m128 test_mm_unpackhi_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_unpackhi_ps
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
return _mm_unpackhi_ps(A, B);
}
__m128 test_mm_unpacklo_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_unpacklo_ps
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
return _mm_unpacklo_ps(A, B);
}
__m128 test_mm_xor_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_xor_ps
// CHECK: xor <4 x i32>
return _mm_xor_ps(A, B);
}