llvm-project/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir

# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512F
--- |
  define <16 x i32> @test_load_v16i32_noalign(<16 x i32>* %p1) {
    %r = load <16 x i32>, <16 x i32>* %p1, align 1
    ret <16 x i32> %r
  }

  define <16 x i32> @test_load_v16i32_align(<16 x i32>* %p1) {
    %r = load <16 x i32>, <16 x i32>* %p1, align 32
    ret <16 x i32> %r
  }

  define void @test_store_v16i32_noalign(<16 x i32> %val, <16 x i32>* %p1) {
    store <16 x i32> %val, <16 x i32>* %p1, align 1
    ret void
  }

  define void @test_store_v16i32_align(<16 x i32> %val, <16 x i32>* %p1) {
    store <16 x i32> %val, <16 x i32>* %p1, align 32
    ret void
  }

...
---
name:            test_load_v16i32_noalign
# AVX512F-LABEL: name:  test_load_v16i32_noalign
alignment:       4
legalized:       true
regBankSelected: true
# AVX512F:      registers:
# AVX512F-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
# AVX512F-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: vecr }
# AVX512F:          %0 = COPY %rdi
# AVX512F-NEXT:     %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 1)
# AVX512F-NEXT:     %zmm0 = COPY %1
# AVX512F-NEXT:     RET 0, implicit %zmm0
body:             |
  bb.1 (%ir-block.0):
    liveins: %rdi

    %0(p0) = COPY %rdi
    %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
    %zmm0 = COPY %1(<16 x s32>)
    RET 0, implicit %zmm0

...
---
name:            test_load_v16i32_align
# AVX512F-LABEL: name:  test_load_v16i32_align
alignment:       4
legalized:       true
regBankSelected: true
# AVX512F:      registers:
# AVX512F-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
# AVX512F-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: vecr }
# AVX512F:          %0 = COPY %rdi
# AVX512F-NEXT:     %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 32)
# AVX512F-NEXT:     %zmm0 = COPY %1
# AVX512F-NEXT:     RET 0, implicit %zmm0
body:             |
  bb.1 (%ir-block.0):
    liveins: %rdi

    %0(p0) = COPY %rdi
    %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32)
    %zmm0 = COPY %1(<16 x s32>)
    RET 0, implicit %zmm0

...
---
name:            test_store_v16i32_noalign
# AVX512F-LABEL: name:  test_store_v16i32_noalign
alignment:       4
legalized:       true
regBankSelected: true
# AVX512F:      registers:
# AVX512F-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
# AVX512F-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: gpr }
# AVX512F:          %0 = COPY %zmm0
# AVX512F-NEXT:     %1 = COPY %rdi
# AVX512F-NEXT:     VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 1)
# AVX512F-NEXT:     RET 0
body:             |
  bb.1 (%ir-block.0):
    liveins: %rdi, %zmm0

    %0(<16 x s32>) = COPY %zmm0
    %1(p0) = COPY %rdi
    G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
    RET 0

...
---
name:            test_store_v16i32_align
# AVX512F-LABEL: name:  test_store_v16i32_align
alignment:       4
legalized:       true
regBankSelected: true
# AVX512F:      registers:
# AVX512F-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
# AVX512F-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: gpr }
# AVX512F:          %0 = COPY %zmm0
# AVX512F-NEXT:     %1 = COPY %rdi
# AVX512F-NEXT:     VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 32)
# AVX512F-NEXT:     RET 0
body:             |
  bb.1 (%ir-block.0):
    liveins: %rdi, %zmm0

    %0(<16 x s32>) = COPY %zmm0
    %1(p0) = COPY %rdi
    G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 32)
    RET 0

...