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llvm-project/llvm/test/CodeGen/PowerPC/testComparesiltsc.ll

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[PowerPC] Reverting sequence of patches for elimination of comparison instructions In the past while, I've committed a number of patches in the PowerPC back end aimed at eliminating comparison instructions. However, this causes some failures in proprietary source and these issues are not observed in SPEC or any open source packages I've been able to run. As a result, I'm pulling the entire series and will refactor it to: - Have a single entry point for easy control - Have fine-grained control over which patterns we transform A side-effect of this is that test cases for these patches (and modified by them) are XFAIL-ed. This is a temporary measure as it is counter-productive to remove/modify these test cases and then have to modify them again when the refactored patch is recommitted. The failure will be investigated in parallel to the refactoring effort and the recommit will either have a fix for it or will leave this transformation off by default until the problem is resolved. llvm-svn: 314244
2017-09-27 04:42:47 +08:00
; XFAIL: *
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential revision. llvm-svn: 314055
2017-09-23 12:41:34 +08:00
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_iltsc_sext_z:
; CHECK: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_store:
; CHECK: # BB#0: # %entry
; CHECK: sub [[REG:r[0-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: sub [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_iltsc_sext_z_store:
; CHECK: srwi {{r[0-9]+}}, r3, 7
entry:
%cmp = icmp slt i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}