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llvm-project/llvm/test/CodeGen/PowerPC/branch_coalesce.ll

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Update branch coalescing to be a PowerPC specific pass Implementing this pass as a PowerPC specific pass. Branch coalescing utilizes the analyzeBranch method which currently does not include any implicit operands. This is not an issue on PPC but must be handled on other targets. Pass is currently off by default. Enabled via -enable-ppc-branch-coalesce. Differential Revision : https: // reviews.llvm.org/D32776 llvm-svn: 313061
2017-09-13 02:39:11 +08:00
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
Improve scheduling with branch coalescing This patch adds a MachineSSA pass that coalesces blocks that branch on the same condition. Committing on behalf of Lei Huang. Differential Revision: https://reviews.llvm.org/D28249 llvm-svn: 296670
2017-03-02 04:29:34 +08:00
; Function Attrs: nounwind
define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
Update branch coalescing to be a PowerPC specific pass Implementing this pass as a PowerPC specific pass. Branch coalescing utilizes the analyzeBranch method which currently does not include any implicit operands. This is not an issue on PPC but must be handled on other targets. Pass is currently off by default. Enabled via -enable-ppc-branch-coalesce. Differential Revision : https: // reviews.llvm.org/D32776 llvm-svn: 313061
2017-09-13 02:39:11 +08:00
; CHECK-LABEL: @testBranchCoal
Improve scheduling with branch coalescing This patch adds a MachineSSA pass that coalesces blocks that branch on the same condition. Committing on behalf of Lei Huang. Differential Revision: https://reviews.llvm.org/D28249 llvm-svn: 296670
2017-03-02 04:29:34 +08:00
; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]]
; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha
; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha
; CHECK-DAG: xxlxor 2, 2, 2
Update branch coalescing to be a PowerPC specific pass Implementing this pass as a PowerPC specific pass. Branch coalescing utilizes the analyzeBranch method which currently does not include any implicit operands. This is not an issue on PPC but must be handled on other targets. Pass is currently off by default. Enabled via -enable-ppc-branch-coalesce. Differential Revision : https: // reviews.llvm.org/D32776 llvm-svn: 313061
2017-09-13 02:39:11 +08:00
; CHECK-NOT: beq
; CHECK-DAG: addi [[LD1BASE:[0-9]+]], [[LD1REG]]
Improve scheduling with branch coalescing This patch adds a MachineSSA pass that coalesces blocks that branch on the same condition. Committing on behalf of Lei Huang. Differential Revision: https://reviews.llvm.org/D28249 llvm-svn: 296670
2017-03-02 04:29:34 +08:00
; CHECK-DAG: addi [[LD2BASE:[0-9]+]], [[LD2REG]]
; CHECK-DAG: lxsdx 1, 0, [[LD1BASE]]
; CHECK-DAG: lxsdx 3, 0, [[LD2BASE]]
; CHECK: .LBB[[LAB1]]
; CHECK: xsadddp 0, 1, 2
; CHECK: xsadddp 1, 0, 3
; CHECK: blr
Update branch coalescing to be a PowerPC specific pass Implementing this pass as a PowerPC specific pass. Branch coalescing utilizes the analyzeBranch method which currently does not include any implicit operands. This is not an issue on PPC but must be handled on other targets. Pass is currently off by default. Enabled via -enable-ppc-branch-coalesce. Differential Revision : https: // reviews.llvm.org/D32776 llvm-svn: 313061
2017-09-13 02:39:11 +08:00
; CHECK-NOCOALESCE-LABEL: testBranchCoal:
; CHECK-NOCOALESCE: # BB#0: # %entry
; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5
; CHECK-NOCOALESCE-NEXT: # BB#1: # %entry
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6
; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry
; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4
; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry
; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_1@toc@l
; CHECK-NOCOALESCE-NEXT: lxsdx 3, 0, 3
; CHECK-NOCOALESCE-NEXT: .LBB0_4: # %entry
; CHECK-NOCOALESCE-NEXT: xsadddp 0, 1, 2
; CHECK-NOCOALESCE-NEXT: xsadddp 1, 0, 3
; CHECK-NOCOALESCE-NEXT: blr
; CHECK-NOCOALESCE-NEXT: .LBB0_5: # %entry
; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK-NOCOALESCE-NEXT: lxsdx 1, 0, 3
; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_2
; CHECK-NOCOALESCE-NEXT: .LBB0_6: # %entry
; CHECK-NOCOALESCE-NEXT: xxlxor 2, 2, 2
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_3
; CHECK-NOCOALESCE-NEXT: b .LBB0_4
entry:
%test = icmp eq i32 %x, 0
%tmp1 = select i1 %test, double %a, double 2.000000e-03
%tmp2 = select i1 %test, double %b, double 0.000000e+00
%tmp3 = select i1 %test, double %c, double 5.000000e-03
%res1 = fadd double %tmp1, %tmp2
%result = fadd double %res1, %tmp3
ret double %result
Improve scheduling with branch coalescing This patch adds a MachineSSA pass that coalesces blocks that branch on the same condition. Committing on behalf of Lei Huang. Differential Revision: https://reviews.llvm.org/D28249 llvm-svn: 296670
2017-03-02 04:29:34 +08:00
}