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llvm-project/llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll

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It seems that OR operation does not affect status reg at all. Remove impdef of SRW. This fixes PR4779 llvm-svn: 83739
2009-10-11 06:17:47 +08:00
; RUN: llc -march=msp430 < %s
; PR4779
define void @foo() nounwind {
entry:
%r = alloca i8 ; <i8*> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
load volatile i8, i8* %r, align 1 ; <i8>:0 [#uses=1]
It seems that OR operation does not affect status reg at all. Remove impdef of SRW. This fixes PR4779 llvm-svn: 83739
2009-10-11 06:17:47 +08:00
or i8 %0, 1 ; <i8>:1 [#uses=1]
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. llvm-svn: 145171
2011-11-27 14:54:59 +08:00
store volatile i8 %1, i8* %r, align 1
It seems that OR operation does not affect status reg at all. Remove impdef of SRW. This fixes PR4779 llvm-svn: 83739
2009-10-11 06:17:47 +08:00
br label %return
return: ; preds = %entry
ret void
}