maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

30 lines
1.0 KiB
LLVM
Raw Normal View History

[AMDGPU] need to insert wait between the scalar load and vector store to the same address to avoid WAR conflict. Reviewers: rampitec, vpykhtin, nhaehnle Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D71934
2020-01-04 23:23:14 +08:00
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
Resubmit: [AMDGPU] Invert the handling of skip insertion. The current implementation of skip insertion (SIInsertSkip) makes it a mandatory pass required for correctness. Initially, the idea was to have an optional pass. This patch inserts the s_cbranch_execz upfront during SILowerControlFlow to skip over the sections of code when no lanes are active. Later, SIRemoveShortExecBranches removes the skips for short branches, unless there is a sideeffect and the skip branch is really necessary. This new pass will replace the handling of skip insertion in the existing SIInsertSkip Pass. Differential revision: https://reviews.llvm.org/D68092
2020-01-22 12:07:55 +08:00
; GCN-LABEL: ; %bb.0:
[AMDGPU] need to insert wait between the scalar load and vector store to the same address to avoid WAR conflict. Reviewers: rampitec, vpykhtin, nhaehnle Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D71934
2020-01-04 23:23:14 +08:00
; GCN: s_load_dword s{{[0-9]+}}, s{{\[}}[[ADDR_LO:[0-9]+]]{{\:}}[[ADDR_HI:[0-9]+]]{{\]}}, 0x0
; GCN: s_waitcnt lgkmcnt(0)
AMDGPU: Select global saddr mode from SGPR pointer Use the 64-bit SGPR base with a 0 offset, since it's 1 fewer instruction to materialize the 0 vs. the 64-bit copy.
2020-11-11 00:06:59 +08:00
; GCN: global_store_dword v
[AMDGPU] need to insert wait between the scalar load and vector store to the same address to avoid WAR conflict. Reviewers: rampitec, vpykhtin, nhaehnle Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D71934
2020-01-04 23:23:14 +08:00
define amdgpu_kernel void @zot(i32 addrspace(1)* nocapture %arg, i64 addrspace(1)* nocapture %arg1) {
bb:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = icmp eq i32 %tmp, 0
br i1 %tmp2, label %bb3, label %bb8
bb3: ; preds = %bb
%tmp4 = load i32, i32 addrspace(1)* %arg, align 4
store i32 0, i32 addrspace(1)* %arg, align 4
%tmp5 = zext i32 %tmp4 to i64
%tmp6 = load i64, i64 addrspace(1)* %arg1, align 8
%tmp7 = add i64 %tmp6, %tmp5
store i64 %tmp7, i64 addrspace(1)* %arg1, align 8
br label %bb8
bb8: ; preds = %bb3, %bb
ret void
}
; Function Attrs: nounwind readnone speculatable
declare i32 @llvm.amdgcn.workitem.id.x() #0
attributes #0 = { nounwind readnone speculatable }