2007-07-14 01:31:29 +08:00
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//===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
|
2007-07-14 01:13:54 +08:00
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//
|
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// The LLVM Compiler Infrastructure
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//
|
2007-12-30 04:36:04 +08:00
|
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// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-07-14 01:13:54 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a top-down list scheduler, using standard algorithms.
|
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// The basic approach uses a priority queue of available nodes to schedule.
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// One at a time, nodes are taken from the priority queue (thus in priority
|
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// order), checked for legality to schedule, and emitted if legal.
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//
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// Nodes may not be legal to schedule either due to structural hazards (e.g.
|
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|
|
// pipeline or resource constraints) or because an input to the instruction has
|
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|
|
// not completed execution.
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//
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|
//===----------------------------------------------------------------------===//
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|
|
2009-10-27 03:32:42 +08:00
|
|
|
#include "AggressiveAntiDepBreaker.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "AntiDepBreaker.h"
|
2009-10-27 00:59:04 +08:00
|
|
|
#include "CriticalAntiDepBreaker.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/ADT/Statistic.h"
|
|
|
|
#include "llvm/Analysis/AliasAnalysis.h"
|
2008-11-20 07:18:57 +08:00
|
|
|
#include "llvm/CodeGen/LatencyPriorityQueue.h"
|
2008-12-16 11:25:46 +08:00
|
|
|
#include "llvm/CodeGen/MachineDominators.h"
|
2009-10-02 03:45:32 +08:00
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
2007-07-14 01:13:54 +08:00
|
|
|
#include "llvm/CodeGen/MachineFunctionPass.h"
|
2008-12-16 11:25:46 +08:00
|
|
|
#include "llvm/CodeGen/MachineLoopInfo.h"
|
2008-11-25 08:52:40 +08:00
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
2016-04-18 17:17:29 +08:00
|
|
|
#include "llvm/CodeGen/Passes.h"
|
2012-06-07 04:29:31 +08:00
|
|
|
#include "llvm/CodeGen/RegisterClassInfo.h"
|
2012-03-08 07:01:06 +08:00
|
|
|
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
|
2009-01-16 09:33:36 +08:00
|
|
|
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/CodeGen/SchedulerRegistry.h"
|
2016-05-10 11:21:59 +08:00
|
|
|
#include "llvm/CodeGen/TargetPassConfig.h"
|
2009-10-27 06:31:16 +08:00
|
|
|
#include "llvm/Support/CommandLine.h"
|
2007-07-14 01:13:54 +08:00
|
|
|
#include "llvm/Support/Debug.h"
|
2009-07-12 04:10:48 +08:00
|
|
|
#include "llvm/Support/ErrorHandling.h"
|
2009-08-11 09:44:26 +08:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
|
|
#include "llvm/Target/TargetLowering.h"
|
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
|
|
|
#include "llvm/Target/TargetSubtargetInfo.h"
|
2007-07-14 01:13:54 +08:00
|
|
|
using namespace llvm;
|
|
|
|
|
2014-04-22 10:02:50 +08:00
|
|
|
#define DEBUG_TYPE "post-RA-sched"
|
|
|
|
|
2009-01-16 09:33:36 +08:00
|
|
|
STATISTIC(NumNoops, "Number of noops inserted");
|
2008-11-20 07:18:57 +08:00
|
|
|
STATISTIC(NumStalls, "Number of pipeline stalls");
|
2009-10-27 00:59:04 +08:00
|
|
|
STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
|
2008-11-20 07:18:57 +08:00
|
|
|
|
2009-10-02 05:46:35 +08:00
|
|
|
// Post-RA scheduling is enabled with
|
2011-07-02 05:01:15 +08:00
|
|
|
// TargetSubtargetInfo.enablePostRAScheduler(). This flag can be used to
|
2009-10-02 05:46:35 +08:00
|
|
|
// override the target.
|
|
|
|
static cl::opt<bool>
|
|
|
|
EnablePostRAScheduler("post-RA-scheduler",
|
|
|
|
cl::desc("Enable scheduling after register allocation"),
|
2009-10-02 06:19:57 +08:00
|
|
|
cl::init(false), cl::Hidden);
|
2009-10-27 00:59:04 +08:00
|
|
|
static cl::opt<std::string>
|
2008-11-25 08:52:40 +08:00
|
|
|
EnableAntiDepBreaking("break-anti-dependencies",
|
2009-10-27 00:59:04 +08:00
|
|
|
cl::desc("Break post-RA scheduling anti-dependencies: "
|
|
|
|
"\"critical\", \"all\", or \"none\""),
|
|
|
|
cl::init("none"), cl::Hidden);
|
2009-01-16 09:33:36 +08:00
|
|
|
|
2009-09-02 02:34:03 +08:00
|
|
|
// If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
|
|
|
|
static cl::opt<int>
|
|
|
|
DebugDiv("postra-sched-debugdiv",
|
|
|
|
cl::desc("Debug control MBBs that are scheduled"),
|
|
|
|
cl::init(0), cl::Hidden);
|
|
|
|
static cl::opt<int>
|
|
|
|
DebugMod("postra-sched-debugmod",
|
|
|
|
cl::desc("Debug control MBBs that are scheduled"),
|
|
|
|
cl::init(0), cl::Hidden);
|
|
|
|
|
2009-10-27 03:41:00 +08:00
|
|
|
AntiDepBreaker::~AntiDepBreaker() { }
|
|
|
|
|
2007-07-14 01:13:54 +08:00
|
|
|
namespace {
|
2009-10-25 14:33:48 +08:00
|
|
|
class PostRAScheduler : public MachineFunctionPass {
|
2010-06-19 07:09:54 +08:00
|
|
|
const TargetInstrInfo *TII;
|
2011-06-17 05:56:21 +08:00
|
|
|
RegisterClassInfo RegClassInfo;
|
2009-10-10 07:27:56 +08:00
|
|
|
|
2007-07-14 01:13:54 +08:00
|
|
|
public:
|
|
|
|
static char ID;
|
2012-02-09 05:22:53 +08:00
|
|
|
PostRAScheduler() : MachineFunctionPass(ID) {}
|
2008-11-25 08:52:40 +08:00
|
|
|
|
2014-03-07 17:26:03 +08:00
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
2009-08-01 07:37:33 +08:00
|
|
|
AU.setPreservesCFG();
|
[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
with the new pass manager, and no longer relying on analysis groups.
This builds essentially a ground-up new AA infrastructure stack for
LLVM. The core ideas are the same that are used throughout the new pass
manager: type erased polymorphism and direct composition. The design is
as follows:
- FunctionAAResults is a type-erasing alias analysis results aggregation
interface to walk a single query across a range of results from
different alias analyses. Currently this is function-specific as we
always assume that aliasing queries are *within* a function.
- AAResultBase is a CRTP utility providing stub implementations of
various parts of the alias analysis result concept, notably in several
cases in terms of other more general parts of the interface. This can
be used to implement only a narrow part of the interface rather than
the entire interface. This isn't really ideal, this logic should be
hoisted into FunctionAAResults as currently it will cause
a significant amount of redundant work, but it faithfully models the
behavior of the prior infrastructure.
- All the alias analysis passes are ported to be wrapper passes for the
legacy PM and new-style analysis passes for the new PM with a shared
result object. In some cases (most notably CFL), this is an extremely
naive approach that we should revisit when we can specialize for the
new pass manager.
- BasicAA has been restructured to reflect that it is much more
fundamentally a function analysis because it uses dominator trees and
loop info that need to be constructed for each function.
All of the references to getting alias analysis results have been
updated to use the new aggregation interface. All the preservation and
other pass management code has been updated accordingly.
The way the FunctionAAResultsWrapperPass works is to detect the
available alias analyses when run, and add them to the results object.
This means that we should be able to continue to respect when various
passes are added to the pipeline, for example adding CFL or adding TBAA
passes should just cause their results to be available and to get folded
into this. The exception to this rule is BasicAA which really needs to
be a function pass due to using dominator trees and loop info. As
a consequence, the FunctionAAResultsWrapperPass directly depends on
BasicAA and always includes it in the aggregation.
This has significant implications for preserving analyses. Generally,
most passes shouldn't bother preserving FunctionAAResultsWrapperPass
because rebuilding the results just updates the set of known AA passes.
The exception to this rule are LoopPass instances which need to preserve
all the function analyses that the loop pass manager will end up
needing. This means preserving both BasicAAWrapperPass and the
aggregating FunctionAAResultsWrapperPass.
Now, when preserving an alias analysis, you do so by directly preserving
that analysis. This is only necessary for non-immutable-pass-provided
alias analyses though, and there are only three of interest: BasicAA,
GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is
preserved when needed because it (like DominatorTree and LoopInfo) is
marked as a CFG-only pass. I've expanded GlobalsAA into the preserved
set everywhere we previously were preserving all of AliasAnalysis, and
I've added SCEVAA in the intersection of that with where we preserve
SCEV itself.
One significant challenge to all of this is that the CGSCC passes were
actually using the alias analysis implementations by taking advantage of
a pretty amazing set of loop holes in the old pass manager's analysis
management code which allowed analysis groups to slide through in many
cases. Moving away from analysis groups makes this problem much more
obvious. To fix it, I've leveraged the flexibility the design of the new
PM components provides to just directly construct the relevant alias
analyses for the relevant functions in the IPO passes that need them.
This is a bit hacky, but should go away with the new pass manager, and
is already in many ways cleaner than the prior state.
Another significant challenge is that various facilities of the old
alias analysis infrastructure just don't fit any more. The most
significant of these is the alias analysis 'counter' pass. That pass
relied on the ability to snoop on AA queries at different points in the
analysis group chain. Instead, I'm planning to build printing
functionality directly into the aggregation layer. I've not included
that in this patch merely to keep it smaller.
Note that all of this needs a nearly complete rewrite of the AA
documentation. I'm planning to do that, but I'd like to make sure the
new design settles, and to flesh out a bit more of what it looks like in
the new pass manager first.
Differential Revision: http://reviews.llvm.org/D12080
llvm-svn: 247167
2015-09-10 01:55:00 +08:00
|
|
|
AU.addRequired<AAResultsWrapperPass>();
|
2012-02-09 05:22:53 +08:00
|
|
|
AU.addRequired<TargetPassConfig>();
|
2008-12-16 11:25:46 +08:00
|
|
|
AU.addRequired<MachineDominatorTree>();
|
|
|
|
AU.addPreserved<MachineDominatorTree>();
|
|
|
|
AU.addRequired<MachineLoopInfo>();
|
|
|
|
AU.addPreserved<MachineLoopInfo>();
|
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
|
|
}
|
|
|
|
|
2016-03-29 01:05:30 +08:00
|
|
|
MachineFunctionProperties getRequiredProperties() const override {
|
|
|
|
return MachineFunctionProperties().set(
|
|
|
|
MachineFunctionProperties::Property::AllVRegsAllocated);
|
|
|
|
}
|
|
|
|
|
2014-03-07 17:26:03 +08:00
|
|
|
bool runOnMachineFunction(MachineFunction &Fn) override;
|
2014-10-29 23:23:11 +08:00
|
|
|
|
2016-05-20 00:40:49 +08:00
|
|
|
private:
|
2014-07-16 06:39:58 +08:00
|
|
|
bool enablePostRAScheduler(
|
|
|
|
const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
|
|
|
|
TargetSubtargetInfo::AntiDepBreakMode &Mode,
|
|
|
|
TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
|
2008-11-20 07:18:57 +08:00
|
|
|
};
|
|
|
|
char PostRAScheduler::ID = 0;
|
|
|
|
|
2009-10-25 14:33:48 +08:00
|
|
|
class SchedulePostRATDList : public ScheduleDAGInstrs {
|
2008-11-20 07:18:57 +08:00
|
|
|
/// AvailableQueue - The priority queue to use for the available SUnits.
|
2009-10-21 09:44:44 +08:00
|
|
|
///
|
2008-11-20 07:18:57 +08:00
|
|
|
LatencyPriorityQueue AvailableQueue;
|
2010-05-15 05:19:48 +08:00
|
|
|
|
2008-11-20 07:18:57 +08:00
|
|
|
/// PendingQueue - This contains all of the instructions whose operands have
|
|
|
|
/// been issued, but their results are not ready yet (due to the latency of
|
|
|
|
/// the operation). Once the operands becomes available, the instruction is
|
|
|
|
/// added to the AvailableQueue.
|
|
|
|
std::vector<SUnit*> PendingQueue;
|
|
|
|
|
2009-10-21 09:44:44 +08:00
|
|
|
/// HazardRec - The hazard recognizer to use.
|
|
|
|
ScheduleHazardRecognizer *HazardRec;
|
|
|
|
|
2009-10-27 00:59:04 +08:00
|
|
|
/// AntiDepBreak - Anti-dependence breaking object, or NULL if none
|
|
|
|
AntiDepBreaker *AntiDepBreak;
|
|
|
|
|
2009-10-21 09:44:44 +08:00
|
|
|
/// AA - AliasAnalysis for making memory reference queries.
|
|
|
|
AliasAnalysis *AA;
|
2009-10-21 03:54:44 +08:00
|
|
|
|
2012-03-07 13:21:52 +08:00
|
|
|
/// The schedule. Null SUnit*'s represent noop instructions.
|
|
|
|
std::vector<SUnit*> Sequence;
|
|
|
|
|
2016-03-05 23:45:23 +08:00
|
|
|
/// Ordered list of DAG postprocessing steps.
|
|
|
|
std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
|
|
|
|
|
2013-08-24 01:48:33 +08:00
|
|
|
/// The index in BB of RegionEnd.
|
|
|
|
///
|
|
|
|
/// This is the instruction number from the top of the current block, not
|
|
|
|
/// the SlotIndex. It is only used by the AntiDepBreaker.
|
|
|
|
unsigned EndIndex;
|
|
|
|
|
2008-11-25 08:52:40 +08:00
|
|
|
public:
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
SchedulePostRATDList(
|
2014-08-21 04:57:26 +08:00
|
|
|
MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA,
|
|
|
|
const RegisterClassInfo &,
|
|
|
|
TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
|
|
|
|
SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs);
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
|
2015-04-11 10:11:45 +08:00
|
|
|
~SchedulePostRATDList() override;
|
2008-11-20 07:18:57 +08:00
|
|
|
|
2012-03-08 07:00:49 +08:00
|
|
|
/// startBlock - Initialize register live-range state for scheduling in
|
2009-02-11 07:27:53 +08:00
|
|
|
/// this block.
|
|
|
|
///
|
2014-03-07 17:26:03 +08:00
|
|
|
void startBlock(MachineBasicBlock *BB) override;
|
2009-02-11 07:27:53 +08:00
|
|
|
|
2013-08-24 01:48:33 +08:00
|
|
|
// Set the index of RegionEnd within the current BB.
|
|
|
|
void setEndIndex(unsigned EndIdx) { EndIndex = EndIdx; }
|
|
|
|
|
2012-03-07 13:21:52 +08:00
|
|
|
/// Initialize the scheduler state for the next scheduling region.
|
2014-03-07 17:26:03 +08:00
|
|
|
void enterRegion(MachineBasicBlock *bb,
|
|
|
|
MachineBasicBlock::iterator begin,
|
|
|
|
MachineBasicBlock::iterator end,
|
|
|
|
unsigned regioninstrs) override;
|
2012-03-07 13:21:52 +08:00
|
|
|
|
|
|
|
/// Notify that the scheduler has finished scheduling the current region.
|
2014-03-07 17:26:03 +08:00
|
|
|
void exitRegion() override;
|
2012-03-07 13:21:52 +08:00
|
|
|
|
2009-10-21 03:54:44 +08:00
|
|
|
/// Schedule - Schedule the instruction range using list scheduling.
|
2009-02-11 07:27:53 +08:00
|
|
|
///
|
2014-03-07 17:26:03 +08:00
|
|
|
void schedule() override;
|
2010-05-15 05:19:48 +08:00
|
|
|
|
2012-03-07 13:21:44 +08:00
|
|
|
void EmitSchedule();
|
|
|
|
|
2009-10-21 09:44:44 +08:00
|
|
|
/// Observe - Update liveness information to account for the current
|
|
|
|
/// instruction, which will not be scheduled.
|
|
|
|
///
|
2016-02-28 03:33:37 +08:00
|
|
|
void Observe(MachineInstr &MI, unsigned Count);
|
2009-10-21 03:54:44 +08:00
|
|
|
|
2012-03-08 07:00:49 +08:00
|
|
|
/// finishBlock - Clean up register live-range state.
|
2009-10-21 09:44:44 +08:00
|
|
|
///
|
2014-03-07 17:26:03 +08:00
|
|
|
void finishBlock() override;
|
2009-10-21 03:54:44 +08:00
|
|
|
|
2009-10-21 09:44:44 +08:00
|
|
|
private:
|
2016-03-05 23:45:23 +08:00
|
|
|
/// Apply each ScheduleDAGMutation step in order.
|
|
|
|
void postprocessDAG();
|
|
|
|
|
2009-11-21 03:32:48 +08:00
|
|
|
void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
|
|
|
|
void ReleaseSuccessors(SUnit *SU);
|
|
|
|
void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
|
|
|
|
void ListScheduleTopDown();
|
2010-05-15 05:19:48 +08:00
|
|
|
|
2012-03-07 13:21:40 +08:00
|
|
|
void dumpSchedule() const;
|
Add two additional hazard recognizer functions
This adds two additional functions to the hazard recognizer interface. These
are optional (in the sense that the default implementations preserve the
current behavior), and used by the post-RA scheduler. Upcoming commits will use
this functionality in order to improve dispatch-group formation on the POWER7
and related cores. Dispatch groups are an odd construct: sometimes we need to
insert nops to force a new one to start (for performance reasons), and some
instructions need to appear in certain positions within a group, but the groups
are not fundamentally cycle based (they can contain instructions with data
dependencies with non-trivial latencies).
Motivation:
unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert
nops to force a new dispatch group to begin. We already have a NoopHazard, and
this is also still needed. However, NoopHazard only causes a nop to be inserted
if there are no other available instructions, and so is not always sufficient.
The number of nops to insert depends on state that only the hazard recognizer
has, so a general callback is necessary.
bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that
would start a new dispatch group when others are available that could be part
of the current dispatch group. In this case, we don't want to issue nops,
because the non-preferred instruction will implicitly start a new dispatch
group regardless.
Although the motivation for these functions is driven by the PowerPC backend,
they are completely general.
llvm-svn: 197084
2013-12-12 06:33:43 +08:00
|
|
|
void emitNoop(unsigned CurCycle);
|
2007-07-14 01:13:54 +08:00
|
|
|
};
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2007-07-14 01:13:54 +08:00
|
|
|
|
2012-02-09 05:23:13 +08:00
|
|
|
char &llvm::PostRASchedulerID = PostRAScheduler::ID;
|
|
|
|
|
|
|
|
INITIALIZE_PASS(PostRAScheduler, "post-RA-sched",
|
|
|
|
"Post RA top-down list latency scheduler", false, false)
|
|
|
|
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
SchedulePostRATDList::SchedulePostRATDList(
|
2014-08-21 04:57:26 +08:00
|
|
|
MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA,
|
|
|
|
const RegisterClassInfo &RCI,
|
|
|
|
TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
|
|
|
|
SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs)
|
2015-11-03 09:53:29 +08:00
|
|
|
: ScheduleDAGInstrs(MF, &MLI), AA(AA), EndIndex(0) {
|
2013-12-29 05:56:55 +08:00
|
|
|
|
2014-08-05 05:25:23 +08:00
|
|
|
const InstrItineraryData *InstrItins =
|
2014-10-14 15:17:23 +08:00
|
|
|
MF.getSubtarget().getInstrItineraryData();
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
HazardRec =
|
2014-10-14 15:17:23 +08:00
|
|
|
MF.getSubtarget().getInstrInfo()->CreateTargetPostRAHazardRecognizer(
|
2014-08-05 05:25:23 +08:00
|
|
|
InstrItins, this);
|
2016-03-05 23:45:23 +08:00
|
|
|
MF.getSubtarget().getPostRAMutations(Mutations);
|
2012-04-24 05:39:35 +08:00
|
|
|
|
|
|
|
assert((AntiDepMode == TargetSubtargetInfo::ANTIDEP_NONE ||
|
|
|
|
MRI.tracksLiveness()) &&
|
|
|
|
"Live-ins must be accurate for anti-dependency breaking");
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
AntiDepBreak =
|
2011-07-02 05:01:15 +08:00
|
|
|
((AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) ?
|
2011-06-17 05:56:21 +08:00
|
|
|
(AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
|
2011-07-02 05:01:15 +08:00
|
|
|
((AntiDepMode == TargetSubtargetInfo::ANTIDEP_CRITICAL) ?
|
2014-04-14 08:51:57 +08:00
|
|
|
(AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : nullptr));
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
SchedulePostRATDList::~SchedulePostRATDList() {
|
|
|
|
delete HazardRec;
|
|
|
|
delete AntiDepBreak;
|
|
|
|
}
|
|
|
|
|
2012-03-07 13:21:52 +08:00
|
|
|
/// Initialize state associated with the next scheduling region.
|
|
|
|
void SchedulePostRATDList::enterRegion(MachineBasicBlock *bb,
|
|
|
|
MachineBasicBlock::iterator begin,
|
|
|
|
MachineBasicBlock::iterator end,
|
2013-08-24 01:48:33 +08:00
|
|
|
unsigned regioninstrs) {
|
|
|
|
ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
|
2012-03-07 13:21:52 +08:00
|
|
|
Sequence.clear();
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Print the schedule before exiting the region.
|
|
|
|
void SchedulePostRATDList::exitRegion() {
|
|
|
|
DEBUG({
|
|
|
|
dbgs() << "*** Final schedule ***\n";
|
|
|
|
dumpSchedule();
|
|
|
|
dbgs() << '\n';
|
|
|
|
});
|
|
|
|
ScheduleDAGInstrs::exitRegion();
|
|
|
|
}
|
|
|
|
|
2012-09-12 06:23:19 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2012-03-07 13:21:40 +08:00
|
|
|
/// dumpSchedule - dump the scheduled Sequence.
|
|
|
|
void SchedulePostRATDList::dumpSchedule() const {
|
|
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
|
|
if (SUnit *SU = Sequence[i])
|
|
|
|
SU->dump(this);
|
|
|
|
else
|
|
|
|
dbgs() << "**** NOOP ****\n";
|
|
|
|
}
|
|
|
|
}
|
2012-09-07 03:06:06 +08:00
|
|
|
#endif
|
2012-03-07 13:21:40 +08:00
|
|
|
|
2014-07-16 06:39:58 +08:00
|
|
|
bool PostRAScheduler::enablePostRAScheduler(
|
|
|
|
const TargetSubtargetInfo &ST,
|
|
|
|
CodeGenOpt::Level OptLevel,
|
|
|
|
TargetSubtargetInfo::AntiDepBreakMode &Mode,
|
|
|
|
TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const {
|
|
|
|
Mode = ST.getAntiDepBreakMode();
|
|
|
|
ST.getCriticalPathRCs(CriticalPathRCs);
|
2016-05-20 00:40:49 +08:00
|
|
|
|
|
|
|
// Check for explicit enable/disable of post-ra scheduling.
|
|
|
|
if (EnablePostRAScheduler.getPosition() > 0)
|
|
|
|
return EnablePostRAScheduler;
|
|
|
|
|
2015-06-13 11:42:16 +08:00
|
|
|
return ST.enablePostRAScheduler() &&
|
2014-07-16 06:39:58 +08:00
|
|
|
OptLevel >= ST.getOptLevelToEnablePostRAScheduler();
|
|
|
|
}
|
|
|
|
|
2008-11-20 07:18:57 +08:00
|
|
|
bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
|
2016-04-23 06:06:11 +08:00
|
|
|
if (skipFunction(*Fn.getFunction()))
|
2014-04-01 01:43:35 +08:00
|
|
|
return false;
|
|
|
|
|
2014-08-05 10:39:49 +08:00
|
|
|
TII = Fn.getSubtarget().getInstrInfo();
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
|
[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
with the new pass manager, and no longer relying on analysis groups.
This builds essentially a ground-up new AA infrastructure stack for
LLVM. The core ideas are the same that are used throughout the new pass
manager: type erased polymorphism and direct composition. The design is
as follows:
- FunctionAAResults is a type-erasing alias analysis results aggregation
interface to walk a single query across a range of results from
different alias analyses. Currently this is function-specific as we
always assume that aliasing queries are *within* a function.
- AAResultBase is a CRTP utility providing stub implementations of
various parts of the alias analysis result concept, notably in several
cases in terms of other more general parts of the interface. This can
be used to implement only a narrow part of the interface rather than
the entire interface. This isn't really ideal, this logic should be
hoisted into FunctionAAResults as currently it will cause
a significant amount of redundant work, but it faithfully models the
behavior of the prior infrastructure.
- All the alias analysis passes are ported to be wrapper passes for the
legacy PM and new-style analysis passes for the new PM with a shared
result object. In some cases (most notably CFL), this is an extremely
naive approach that we should revisit when we can specialize for the
new pass manager.
- BasicAA has been restructured to reflect that it is much more
fundamentally a function analysis because it uses dominator trees and
loop info that need to be constructed for each function.
All of the references to getting alias analysis results have been
updated to use the new aggregation interface. All the preservation and
other pass management code has been updated accordingly.
The way the FunctionAAResultsWrapperPass works is to detect the
available alias analyses when run, and add them to the results object.
This means that we should be able to continue to respect when various
passes are added to the pipeline, for example adding CFL or adding TBAA
passes should just cause their results to be available and to get folded
into this. The exception to this rule is BasicAA which really needs to
be a function pass due to using dominator trees and loop info. As
a consequence, the FunctionAAResultsWrapperPass directly depends on
BasicAA and always includes it in the aggregation.
This has significant implications for preserving analyses. Generally,
most passes shouldn't bother preserving FunctionAAResultsWrapperPass
because rebuilding the results just updates the set of known AA passes.
The exception to this rule are LoopPass instances which need to preserve
all the function analyses that the loop pass manager will end up
needing. This means preserving both BasicAAWrapperPass and the
aggregating FunctionAAResultsWrapperPass.
Now, when preserving an alias analysis, you do so by directly preserving
that analysis. This is only necessary for non-immutable-pass-provided
alias analyses though, and there are only three of interest: BasicAA,
GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is
preserved when needed because it (like DominatorTree and LoopInfo) is
marked as a CFG-only pass. I've expanded GlobalsAA into the preserved
set everywhere we previously were preserving all of AliasAnalysis, and
I've added SCEVAA in the intersection of that with where we preserve
SCEV itself.
One significant challenge to all of this is that the CGSCC passes were
actually using the alias analysis implementations by taking advantage of
a pretty amazing set of loop holes in the old pass manager's analysis
management code which allowed analysis groups to slide through in many
cases. Moving away from analysis groups makes this problem much more
obvious. To fix it, I've leveraged the flexibility the design of the new
PM components provides to just directly construct the relevant alias
analyses for the relevant functions in the IPO passes that need them.
This is a bit hacky, but should go away with the new pass manager, and
is already in many ways cleaner than the prior state.
Another significant challenge is that various facilities of the old
alias analysis infrastructure just don't fit any more. The most
significant of these is the alias analysis 'counter' pass. That pass
relied on the ability to snoop on AA queries at different points in the
analysis group chain. Instead, I'm planning to build printing
functionality directly into the aggregation layer. I've not included
that in this patch merely to keep it smaller.
Note that all of this needs a nearly complete rewrite of the AA
documentation. I'm planning to do that, but I'd like to make sure the
new design settles, and to flesh out a bit more of what it looks like in
the new pass manager first.
Differential Revision: http://reviews.llvm.org/D12080
llvm-svn: 247167
2015-09-10 01:55:00 +08:00
|
|
|
AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
|
2012-02-09 05:22:53 +08:00
|
|
|
TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
|
|
|
|
|
2011-06-17 05:56:21 +08:00
|
|
|
RegClassInfo.runOnMachineFunction(Fn);
|
2009-10-10 08:15:38 +08:00
|
|
|
|
2011-12-14 10:11:42 +08:00
|
|
|
TargetSubtargetInfo::AntiDepBreakMode AntiDepMode =
|
|
|
|
TargetSubtargetInfo::ANTIDEP_NONE;
|
2012-02-22 13:59:10 +08:00
|
|
|
SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs;
|
2016-05-20 00:40:49 +08:00
|
|
|
|
|
|
|
// Check that post-RA scheduling is enabled for this target.
|
|
|
|
// This may upgrade the AntiDepMode.
|
|
|
|
if (!enablePostRAScheduler(Fn.getSubtarget(), PassConfig->getOptLevel(),
|
|
|
|
AntiDepMode, CriticalPathRCs))
|
|
|
|
return false;
|
2009-09-30 08:10:16 +08:00
|
|
|
|
2009-10-23 07:19:17 +08:00
|
|
|
// Check for antidep breaking override...
|
|
|
|
if (EnableAntiDepBreaking.getPosition() > 0) {
|
2011-07-02 05:01:15 +08:00
|
|
|
AntiDepMode = (EnableAntiDepBreaking == "all")
|
|
|
|
? TargetSubtargetInfo::ANTIDEP_ALL
|
|
|
|
: ((EnableAntiDepBreaking == "critical")
|
|
|
|
? TargetSubtargetInfo::ANTIDEP_CRITICAL
|
|
|
|
: TargetSubtargetInfo::ANTIDEP_NONE);
|
2009-10-23 07:19:17 +08:00
|
|
|
}
|
|
|
|
|
2010-01-05 09:26:01 +08:00
|
|
|
DEBUG(dbgs() << "PostRAScheduler\n");
|
2007-07-14 01:13:54 +08:00
|
|
|
|
2014-08-21 04:57:26 +08:00
|
|
|
SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
CriticalPathRCs);
|
2009-01-16 03:20:50 +08:00
|
|
|
|
2007-07-14 01:13:54 +08:00
|
|
|
// Loop over all of the basic blocks
|
2015-10-10 05:05:00 +08:00
|
|
|
for (auto &MBB : Fn) {
|
2009-09-02 02:34:03 +08:00
|
|
|
#ifndef NDEBUG
|
|
|
|
// If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
|
|
|
|
if (DebugDiv > 0) {
|
|
|
|
static int bbcnt = 0;
|
|
|
|
if (bbcnt++ % DebugDiv != DebugMod)
|
|
|
|
continue;
|
2012-08-22 14:07:19 +08:00
|
|
|
dbgs() << "*** DEBUG scheduling " << Fn.getName()
|
2015-10-10 05:05:00 +08:00
|
|
|
<< ":BB#" << MBB.getNumber() << " ***\n";
|
2009-09-02 02:34:03 +08:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2009-02-11 07:27:53 +08:00
|
|
|
// Initialize register live-range state for scheduling in this block.
|
2015-10-10 05:05:00 +08:00
|
|
|
Scheduler.startBlock(&MBB);
|
2009-02-11 07:27:53 +08:00
|
|
|
|
2009-01-17 06:10:20 +08:00
|
|
|
// Schedule each sequence of instructions not interrupted by a label
|
|
|
|
// or anything else that effectively needs to shut down scheduling.
|
2015-10-10 05:05:00 +08:00
|
|
|
MachineBasicBlock::iterator Current = MBB.end();
|
|
|
|
unsigned Count = MBB.size(), CurrentCount = Count;
|
|
|
|
for (MachineBasicBlock::iterator I = Current; I != MBB.begin();) {
|
2014-03-02 20:27:27 +08:00
|
|
|
MachineInstr *MI = std::prev(I);
|
2013-08-24 01:48:33 +08:00
|
|
|
--Count;
|
Make calls scheduling boundaries post-ra.
Before register allocation, instructions can be moved across calls in
order to reduce register pressure. After register allocation, we don't
gain a lot by moving callee-saved defs across calls. In fact, since the
scheduler doesn't have a good idea how registers are used in the callee,
it can't really make good scheduling decisions.
This changes the schedule in two ways: 1. Latencies to call uses and
defs are no longer accounted for, causing some random shuffling around
calls. This isn't really a problem since those uses and defs are
inaccurate proxies for what happens inside the callee. They don't
represent registers used by the call instruction itself.
2. Instructions are no longer moved across calls. This didn't happen
very often, and the scheduling decision was made on dubious information
anyway.
As with any scheduling change, benchmark numbers shift around a bit,
but there is no positive or negative trend from this change.
This makes the post-ra scheduler 5% faster for ARM targets.
The secret motivation for this patch is the introduction of register
mask operands representing call clobbers. The most efficient way of
handling regmasks in ScheduleDAGInstrs is to model them as barriers for
physreg live ranges, but not for virtreg live ranges. That's fine
pre-ra, but post-ra it would have the same effect as this patch.
llvm-svn: 151265
2012-02-24 01:54:21 +08:00
|
|
|
// Calls are not scheduling boundaries before register allocation, but
|
|
|
|
// post-ra we don't gain anything by scheduling across calls since we
|
|
|
|
// don't need to worry about register pressure.
|
2015-10-10 05:05:00 +08:00
|
|
|
if (MI->isCall() || TII->isSchedulingBoundary(MI, &MBB, Fn)) {
|
|
|
|
Scheduler.enterRegion(&MBB, I, Current, CurrentCount - Count);
|
2013-08-24 01:48:33 +08:00
|
|
|
Scheduler.setEndIndex(CurrentCount);
|
2012-03-08 07:00:49 +08:00
|
|
|
Scheduler.schedule();
|
2012-03-07 13:21:52 +08:00
|
|
|
Scheduler.exitRegion();
|
2010-05-01 08:01:06 +08:00
|
|
|
Scheduler.EmitSchedule();
|
2009-02-11 07:27:53 +08:00
|
|
|
Current = MI;
|
2013-08-24 01:48:33 +08:00
|
|
|
CurrentCount = Count;
|
2016-02-28 03:33:37 +08:00
|
|
|
Scheduler.Observe(*MI, CurrentCount);
|
2009-01-17 06:10:20 +08:00
|
|
|
}
|
2009-02-11 07:27:53 +08:00
|
|
|
I = MI;
|
2011-12-14 10:11:42 +08:00
|
|
|
if (MI->isBundle())
|
|
|
|
Count -= MI->getBundleSize();
|
2009-02-11 12:27:20 +08:00
|
|
|
}
|
|
|
|
assert(Count == 0 && "Instruction count mismatch!");
|
2015-10-10 05:05:00 +08:00
|
|
|
assert((MBB.begin() == Current || CurrentCount != 0) &&
|
2009-03-11 02:10:43 +08:00
|
|
|
"Instruction count mismatch!");
|
2015-10-10 05:05:00 +08:00
|
|
|
Scheduler.enterRegion(&MBB, MBB.begin(), Current, CurrentCount);
|
2013-08-24 01:48:33 +08:00
|
|
|
Scheduler.setEndIndex(CurrentCount);
|
2012-03-08 07:00:49 +08:00
|
|
|
Scheduler.schedule();
|
2012-03-07 13:21:52 +08:00
|
|
|
Scheduler.exitRegion();
|
2010-05-01 08:01:06 +08:00
|
|
|
Scheduler.EmitSchedule();
|
2009-02-11 07:27:53 +08:00
|
|
|
|
|
|
|
// Clean up register live-range state.
|
2012-03-08 07:00:49 +08:00
|
|
|
Scheduler.finishBlock();
|
2009-08-26 01:03:05 +08:00
|
|
|
|
2009-09-04 06:15:25 +08:00
|
|
|
// Update register kills
|
2015-10-10 05:05:00 +08:00
|
|
|
Scheduler.fixupKills(&MBB);
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
2007-07-14 01:13:54 +08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2010-05-15 05:19:48 +08:00
|
|
|
|
2009-02-11 07:27:53 +08:00
|
|
|
/// StartBlock - Initialize register live-range state for scheduling in
|
|
|
|
/// this block.
|
|
|
|
///
|
2012-03-08 07:00:49 +08:00
|
|
|
void SchedulePostRATDList::startBlock(MachineBasicBlock *BB) {
|
2009-02-11 07:27:53 +08:00
|
|
|
// Call the superclass.
|
2012-03-08 07:00:49 +08:00
|
|
|
ScheduleDAGInstrs::startBlock(BB);
|
2009-02-11 07:27:53 +08:00
|
|
|
|
2009-10-27 00:59:04 +08:00
|
|
|
// Reset the hazard recognizer and anti-dep breaker.
|
2009-08-10 23:55:25 +08:00
|
|
|
HazardRec->Reset();
|
2014-04-14 08:51:57 +08:00
|
|
|
if (AntiDepBreak)
|
2009-10-27 00:59:04 +08:00
|
|
|
AntiDepBreak->StartBlock(BB);
|
2009-02-11 07:27:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Schedule - Schedule the instruction range using list scheduling.
|
|
|
|
///
|
2012-03-08 07:00:49 +08:00
|
|
|
void SchedulePostRATDList::schedule() {
|
2008-12-24 02:36:58 +08:00
|
|
|
// Build the scheduling graph.
|
2012-03-08 07:00:49 +08:00
|
|
|
buildSchedGraph(AA);
|
2008-11-20 07:18:57 +08:00
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
if (AntiDepBreak) {
|
2010-05-15 05:19:48 +08:00
|
|
|
unsigned Broken =
|
2012-03-09 12:29:02 +08:00
|
|
|
AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd,
|
|
|
|
EndIndex, DbgValues);
|
2010-05-15 05:19:48 +08:00
|
|
|
|
2009-11-21 03:32:48 +08:00
|
|
|
if (Broken != 0) {
|
2008-11-25 08:52:40 +08:00
|
|
|
// We made changes. Update the dependency graph.
|
|
|
|
// Theoretically we could update the graph in place:
|
|
|
|
// When a live range is changed to use a different register, remove
|
|
|
|
// the def's anti-dependence *and* output-dependence edges due to
|
|
|
|
// that register, and add new anti-dependence and output-dependence
|
|
|
|
// edges based on the next live range of the register.
|
2012-03-07 13:21:52 +08:00
|
|
|
ScheduleDAG::clearDAG();
|
2012-03-08 07:00:49 +08:00
|
|
|
buildSchedGraph(AA);
|
2010-05-15 05:19:48 +08:00
|
|
|
|
2009-10-27 00:59:04 +08:00
|
|
|
NumFixedAnti += Broken;
|
2008-11-25 08:52:40 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-03-09 00:54:20 +08:00
|
|
|
postprocessDAG();
|
|
|
|
|
2010-01-05 09:26:01 +08:00
|
|
|
DEBUG(dbgs() << "********** List Scheduling **********\n");
|
2015-11-07 04:59:02 +08:00
|
|
|
DEBUG(
|
|
|
|
for (const SUnit &SU : SUnits) {
|
|
|
|
SU.dumpAll(this);
|
|
|
|
dbgs() << '\n';
|
|
|
|
}
|
|
|
|
);
|
2009-08-10 23:55:25 +08:00
|
|
|
|
2008-11-20 07:18:57 +08:00
|
|
|
AvailableQueue.initNodes(SUnits);
|
2009-11-21 03:32:48 +08:00
|
|
|
ListScheduleTopDown();
|
2008-11-20 07:18:57 +08:00
|
|
|
AvailableQueue.releaseState();
|
|
|
|
}
|
|
|
|
|
2009-02-11 07:27:53 +08:00
|
|
|
/// Observe - Update liveness information to account for the current
|
|
|
|
/// instruction, which will not be scheduled.
|
|
|
|
///
|
2016-02-28 03:33:37 +08:00
|
|
|
void SchedulePostRATDList::Observe(MachineInstr &MI, unsigned Count) {
|
2014-04-14 08:51:57 +08:00
|
|
|
if (AntiDepBreak)
|
2012-03-08 07:00:52 +08:00
|
|
|
AntiDepBreak->Observe(MI, Count, EndIndex);
|
2009-02-11 07:27:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// FinishBlock - Clean up register live-range state.
|
|
|
|
///
|
2012-03-08 07:00:49 +08:00
|
|
|
void SchedulePostRATDList::finishBlock() {
|
2014-04-14 08:51:57 +08:00
|
|
|
if (AntiDepBreak)
|
2009-10-27 00:59:04 +08:00
|
|
|
AntiDepBreak->FinishBlock();
|
2009-02-11 07:27:53 +08:00
|
|
|
|
|
|
|
// Call the superclass.
|
2012-03-08 07:00:49 +08:00
|
|
|
ScheduleDAGInstrs::finishBlock();
|
2009-02-11 07:27:53 +08:00
|
|
|
}
|
|
|
|
|
2016-03-05 23:45:23 +08:00
|
|
|
/// Apply each ScheduleDAGMutation step in order.
|
|
|
|
void SchedulePostRATDList::postprocessDAG() {
|
|
|
|
for (auto &M : Mutations)
|
|
|
|
M->apply(this);
|
|
|
|
}
|
|
|
|
|
2008-11-20 07:18:57 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Top-Down Scheduling
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
|
2012-11-13 03:28:57 +08:00
|
|
|
/// the PendingQueue if the count reaches zero.
|
2009-11-21 03:32:48 +08:00
|
|
|
void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
|
2008-12-10 06:54:47 +08:00
|
|
|
SUnit *SuccSU = SuccEdge->getSUnit();
|
2009-10-01 04:15:38 +08:00
|
|
|
|
2012-11-13 10:35:06 +08:00
|
|
|
if (SuccEdge->isWeak()) {
|
2012-11-13 03:28:57 +08:00
|
|
|
--SuccSU->WeakPredsLeft;
|
|
|
|
return;
|
|
|
|
}
|
2008-11-20 07:18:57 +08:00
|
|
|
#ifndef NDEBUG
|
2009-10-01 04:15:38 +08:00
|
|
|
if (SuccSU->NumPredsLeft == 0) {
|
2010-01-05 09:26:01 +08:00
|
|
|
dbgs() << "*** Scheduling failed! ***\n";
|
2008-11-20 07:18:57 +08:00
|
|
|
SuccSU->dump(this);
|
2010-01-05 09:26:01 +08:00
|
|
|
dbgs() << " has been released too many times!\n";
|
2014-04-14 08:51:57 +08:00
|
|
|
llvm_unreachable(nullptr);
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
|
|
|
#endif
|
2009-10-01 04:15:38 +08:00
|
|
|
--SuccSU->NumPredsLeft;
|
|
|
|
|
2011-05-07 02:14:32 +08:00
|
|
|
// Standard scheduler algorithms will recompute the depth of the successor
|
2011-05-07 01:09:08 +08:00
|
|
|
// here as such:
|
|
|
|
// SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
|
|
|
|
//
|
|
|
|
// However, we lazily compute node depth instead. Note that
|
|
|
|
// ScheduleNodeTopDown has already updated the depth of this node which causes
|
|
|
|
// all descendents to be marked dirty. Setting the successor depth explicitly
|
|
|
|
// here would cause depth to be recomputed for all its ancestors. If the
|
|
|
|
// successor is not yet ready (because of a transitively redundant edge) then
|
|
|
|
// this causes depth computation to be quadratic in the size of the DAG.
|
2010-05-15 05:19:48 +08:00
|
|
|
|
2009-02-11 07:27:53 +08:00
|
|
|
// If all the node's predecessors are scheduled, this node is ready
|
|
|
|
// to be scheduled. Ignore the special ExitSU node.
|
|
|
|
if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
|
2008-11-20 07:18:57 +08:00
|
|
|
PendingQueue.push_back(SuccSU);
|
2009-02-11 07:27:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
|
2009-11-21 03:32:48 +08:00
|
|
|
void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
|
2009-02-11 07:27:53 +08:00
|
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
2009-11-04 04:57:50 +08:00
|
|
|
I != E; ++I) {
|
2009-11-21 03:32:48 +08:00
|
|
|
ReleaseSucc(SU, &*I);
|
2009-11-04 04:57:50 +08:00
|
|
|
}
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
|
|
|
|
/// count of its successors. If a successor pending count is zero, add it to
|
|
|
|
/// the Available queue.
|
2009-11-21 03:32:48 +08:00
|
|
|
void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
|
2010-01-05 09:26:01 +08:00
|
|
|
DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
|
2008-11-20 07:18:57 +08:00
|
|
|
DEBUG(SU->dump(this));
|
2010-05-15 05:19:48 +08:00
|
|
|
|
2008-11-20 07:18:57 +08:00
|
|
|
Sequence.push_back(SU);
|
2010-05-15 05:19:48 +08:00
|
|
|
assert(CurCycle >= SU->getDepth() &&
|
2009-11-04 04:57:50 +08:00
|
|
|
"Node scheduled above its depth!");
|
2009-11-21 03:32:48 +08:00
|
|
|
SU->setDepthToAtLeast(CurCycle);
|
2008-11-20 07:18:57 +08:00
|
|
|
|
2009-11-21 03:32:48 +08:00
|
|
|
ReleaseSuccessors(SU);
|
2008-11-20 07:18:57 +08:00
|
|
|
SU->isScheduled = true;
|
2012-03-08 07:00:49 +08:00
|
|
|
AvailableQueue.scheduledNode(SU);
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
|
|
|
|
Add two additional hazard recognizer functions
This adds two additional functions to the hazard recognizer interface. These
are optional (in the sense that the default implementations preserve the
current behavior), and used by the post-RA scheduler. Upcoming commits will use
this functionality in order to improve dispatch-group formation on the POWER7
and related cores. Dispatch groups are an odd construct: sometimes we need to
insert nops to force a new one to start (for performance reasons), and some
instructions need to appear in certain positions within a group, but the groups
are not fundamentally cycle based (they can contain instructions with data
dependencies with non-trivial latencies).
Motivation:
unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert
nops to force a new dispatch group to begin. We already have a NoopHazard, and
this is also still needed. However, NoopHazard only causes a nop to be inserted
if there are no other available instructions, and so is not always sufficient.
The number of nops to insert depends on state that only the hazard recognizer
has, so a general callback is necessary.
bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that
would start a new dispatch group when others are available that could be part
of the current dispatch group. In this case, we don't want to issue nops,
because the non-preferred instruction will implicitly start a new dispatch
group regardless.
Although the motivation for these functions is driven by the PowerPC backend,
they are completely general.
llvm-svn: 197084
2013-12-12 06:33:43 +08:00
|
|
|
/// emitNoop - Add a noop to the current instruction sequence.
|
|
|
|
void SchedulePostRATDList::emitNoop(unsigned CurCycle) {
|
|
|
|
DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
|
|
|
|
HazardRec->EmitNoop();
|
2014-04-14 08:51:57 +08:00
|
|
|
Sequence.push_back(nullptr); // NULL here means noop
|
Add two additional hazard recognizer functions
This adds two additional functions to the hazard recognizer interface. These
are optional (in the sense that the default implementations preserve the
current behavior), and used by the post-RA scheduler. Upcoming commits will use
this functionality in order to improve dispatch-group formation on the POWER7
and related cores. Dispatch groups are an odd construct: sometimes we need to
insert nops to force a new one to start (for performance reasons), and some
instructions need to appear in certain positions within a group, but the groups
are not fundamentally cycle based (they can contain instructions with data
dependencies with non-trivial latencies).
Motivation:
unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert
nops to force a new dispatch group to begin. We already have a NoopHazard, and
this is also still needed. However, NoopHazard only causes a nop to be inserted
if there are no other available instructions, and so is not always sufficient.
The number of nops to insert depends on state that only the hazard recognizer
has, so a general callback is necessary.
bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that
would start a new dispatch group when others are available that could be part
of the current dispatch group. In this case, we don't want to issue nops,
because the non-preferred instruction will implicitly start a new dispatch
group regardless.
Although the motivation for these functions is driven by the PowerPC backend,
they are completely general.
llvm-svn: 197084
2013-12-12 06:33:43 +08:00
|
|
|
++NumNoops;
|
|
|
|
}
|
|
|
|
|
2008-11-20 07:18:57 +08:00
|
|
|
/// ListScheduleTopDown - The main loop of list scheduling for top-down
|
|
|
|
/// schedulers.
|
2009-11-21 03:32:48 +08:00
|
|
|
void SchedulePostRATDList::ListScheduleTopDown() {
|
2008-11-20 07:18:57 +08:00
|
|
|
unsigned CurCycle = 0;
|
2010-05-15 05:19:48 +08:00
|
|
|
|
2009-11-04 04:57:50 +08:00
|
|
|
// We're scheduling top-down but we're visiting the regions in
|
|
|
|
// bottom-up order, so we don't know the hazards at the start of a
|
|
|
|
// region. So assume no hazards (this should usually be ok as most
|
|
|
|
// blocks are a single region).
|
|
|
|
HazardRec->Reset();
|
|
|
|
|
2009-02-11 07:27:53 +08:00
|
|
|
// Release any successors of the special Entry node.
|
2009-11-21 03:32:48 +08:00
|
|
|
ReleaseSuccessors(&EntrySU);
|
2009-02-11 07:27:53 +08:00
|
|
|
|
2009-11-21 03:32:48 +08:00
|
|
|
// Add all leaves to Available queue.
|
2008-11-20 07:18:57 +08:00
|
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
|
|
// It is available if it has no predecessors.
|
2012-11-13 03:28:57 +08:00
|
|
|
if (!SUnits[i].NumPredsLeft && !SUnits[i].isAvailable) {
|
2008-11-20 07:18:57 +08:00
|
|
|
AvailableQueue.push(&SUnits[i]);
|
|
|
|
SUnits[i].isAvailable = true;
|
|
|
|
}
|
|
|
|
}
|
2009-02-11 07:27:53 +08:00
|
|
|
|
2009-08-13 05:47:46 +08:00
|
|
|
// In any cycle where we can't schedule any instructions, we must
|
|
|
|
// stall or emit a noop, depending on the target.
|
2009-09-06 20:10:17 +08:00
|
|
|
bool CycleHasInsts = false;
|
2009-08-13 05:47:46 +08:00
|
|
|
|
2008-11-20 07:18:57 +08:00
|
|
|
// While Available queue is not empty, grab the node with the highest
|
|
|
|
// priority. If it is not ready put it back. Schedule the node.
|
2009-01-16 09:33:36 +08:00
|
|
|
std::vector<SUnit*> NotReady;
|
2008-11-20 07:18:57 +08:00
|
|
|
Sequence.reserve(SUnits.size());
|
|
|
|
while (!AvailableQueue.empty() || !PendingQueue.empty()) {
|
|
|
|
// Check to see if any of the pending instructions are ready to issue. If
|
|
|
|
// so, add them to the available queue.
|
2008-12-16 11:25:46 +08:00
|
|
|
unsigned MinDepth = ~0u;
|
2008-11-20 07:18:57 +08:00
|
|
|
for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
|
2009-11-21 03:32:48 +08:00
|
|
|
if (PendingQueue[i]->getDepth() <= CurCycle) {
|
2008-11-20 07:18:57 +08:00
|
|
|
AvailableQueue.push(PendingQueue[i]);
|
|
|
|
PendingQueue[i]->isAvailable = true;
|
|
|
|
PendingQueue[i] = PendingQueue.back();
|
|
|
|
PendingQueue.pop_back();
|
|
|
|
--i; --e;
|
2009-11-21 03:32:48 +08:00
|
|
|
} else if (PendingQueue[i]->getDepth() < MinDepth)
|
|
|
|
MinDepth = PendingQueue[i]->getDepth();
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
2009-08-12 01:35:23 +08:00
|
|
|
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
|
2009-08-12 01:35:23 +08:00
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
SUnit *FoundSUnit = nullptr, *NotPreferredSUnit = nullptr;
|
2009-01-16 09:33:36 +08:00
|
|
|
bool HasNoopHazards = false;
|
|
|
|
while (!AvailableQueue.empty()) {
|
|
|
|
SUnit *CurSUnit = AvailableQueue.pop();
|
|
|
|
|
|
|
|
ScheduleHazardRecognizer::HazardType HT =
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
|
2009-01-16 09:33:36 +08:00
|
|
|
if (HT == ScheduleHazardRecognizer::NoHazard) {
|
Add two additional hazard recognizer functions
This adds two additional functions to the hazard recognizer interface. These
are optional (in the sense that the default implementations preserve the
current behavior), and used by the post-RA scheduler. Upcoming commits will use
this functionality in order to improve dispatch-group formation on the POWER7
and related cores. Dispatch groups are an odd construct: sometimes we need to
insert nops to force a new one to start (for performance reasons), and some
instructions need to appear in certain positions within a group, but the groups
are not fundamentally cycle based (they can contain instructions with data
dependencies with non-trivial latencies).
Motivation:
unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert
nops to force a new dispatch group to begin. We already have a NoopHazard, and
this is also still needed. However, NoopHazard only causes a nop to be inserted
if there are no other available instructions, and so is not always sufficient.
The number of nops to insert depends on state that only the hazard recognizer
has, so a general callback is necessary.
bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that
would start a new dispatch group when others are available that could be part
of the current dispatch group. In this case, we don't want to issue nops,
because the non-preferred instruction will implicitly start a new dispatch
group regardless.
Although the motivation for these functions is driven by the PowerPC backend,
they are completely general.
llvm-svn: 197084
2013-12-12 06:33:43 +08:00
|
|
|
if (HazardRec->ShouldPreferAnother(CurSUnit)) {
|
|
|
|
if (!NotPreferredSUnit) {
|
2014-10-29 23:23:11 +08:00
|
|
|
// If this is the first non-preferred node for this cycle, then
|
|
|
|
// record it and continue searching for a preferred node. If this
|
|
|
|
// is not the first non-preferred node, then treat it as though
|
|
|
|
// there had been a hazard.
|
Add two additional hazard recognizer functions
This adds two additional functions to the hazard recognizer interface. These
are optional (in the sense that the default implementations preserve the
current behavior), and used by the post-RA scheduler. Upcoming commits will use
this functionality in order to improve dispatch-group formation on the POWER7
and related cores. Dispatch groups are an odd construct: sometimes we need to
insert nops to force a new one to start (for performance reasons), and some
instructions need to appear in certain positions within a group, but the groups
are not fundamentally cycle based (they can contain instructions with data
dependencies with non-trivial latencies).
Motivation:
unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert
nops to force a new dispatch group to begin. We already have a NoopHazard, and
this is also still needed. However, NoopHazard only causes a nop to be inserted
if there are no other available instructions, and so is not always sufficient.
The number of nops to insert depends on state that only the hazard recognizer
has, so a general callback is necessary.
bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that
would start a new dispatch group when others are available that could be part
of the current dispatch group. In this case, we don't want to issue nops,
because the non-preferred instruction will implicitly start a new dispatch
group regardless.
Although the motivation for these functions is driven by the PowerPC backend,
they are completely general.
llvm-svn: 197084
2013-12-12 06:33:43 +08:00
|
|
|
NotPreferredSUnit = CurSUnit;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
FoundSUnit = CurSUnit;
|
|
|
|
break;
|
|
|
|
}
|
2009-01-16 09:33:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Remember if this is a noop hazard.
|
|
|
|
HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
|
|
|
|
|
|
|
|
NotReady.push_back(CurSUnit);
|
|
|
|
}
|
|
|
|
|
Add two additional hazard recognizer functions
This adds two additional functions to the hazard recognizer interface. These
are optional (in the sense that the default implementations preserve the
current behavior), and used by the post-RA scheduler. Upcoming commits will use
this functionality in order to improve dispatch-group formation on the POWER7
and related cores. Dispatch groups are an odd construct: sometimes we need to
insert nops to force a new one to start (for performance reasons), and some
instructions need to appear in certain positions within a group, but the groups
are not fundamentally cycle based (they can contain instructions with data
dependencies with non-trivial latencies).
Motivation:
unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert
nops to force a new dispatch group to begin. We already have a NoopHazard, and
this is also still needed. However, NoopHazard only causes a nop to be inserted
if there are no other available instructions, and so is not always sufficient.
The number of nops to insert depends on state that only the hazard recognizer
has, so a general callback is necessary.
bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that
would start a new dispatch group when others are available that could be part
of the current dispatch group. In this case, we don't want to issue nops,
because the non-preferred instruction will implicitly start a new dispatch
group regardless.
Although the motivation for these functions is driven by the PowerPC backend,
they are completely general.
llvm-svn: 197084
2013-12-12 06:33:43 +08:00
|
|
|
// If we have a non-preferred node, push it back onto the available list.
|
|
|
|
// If we did not find a preferred node, then schedule this first
|
|
|
|
// non-preferred node.
|
|
|
|
if (NotPreferredSUnit) {
|
|
|
|
if (!FoundSUnit) {
|
|
|
|
DEBUG(dbgs() << "*** Will schedule a non-preferred instruction...\n");
|
|
|
|
FoundSUnit = NotPreferredSUnit;
|
|
|
|
} else {
|
|
|
|
AvailableQueue.push(NotPreferredSUnit);
|
|
|
|
}
|
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
NotPreferredSUnit = nullptr;
|
Add two additional hazard recognizer functions
This adds two additional functions to the hazard recognizer interface. These
are optional (in the sense that the default implementations preserve the
current behavior), and used by the post-RA scheduler. Upcoming commits will use
this functionality in order to improve dispatch-group formation on the POWER7
and related cores. Dispatch groups are an odd construct: sometimes we need to
insert nops to force a new one to start (for performance reasons), and some
instructions need to appear in certain positions within a group, but the groups
are not fundamentally cycle based (they can contain instructions with data
dependencies with non-trivial latencies).
Motivation:
unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert
nops to force a new dispatch group to begin. We already have a NoopHazard, and
this is also still needed. However, NoopHazard only causes a nop to be inserted
if there are no other available instructions, and so is not always sufficient.
The number of nops to insert depends on state that only the hazard recognizer
has, so a general callback is necessary.
bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that
would start a new dispatch group when others are available that could be part
of the current dispatch group. In this case, we don't want to issue nops,
because the non-preferred instruction will implicitly start a new dispatch
group regardless.
Although the motivation for these functions is driven by the PowerPC backend,
they are completely general.
llvm-svn: 197084
2013-12-12 06:33:43 +08:00
|
|
|
}
|
|
|
|
|
2009-01-16 09:33:36 +08:00
|
|
|
// Add the nodes that aren't ready back onto the available list.
|
|
|
|
if (!NotReady.empty()) {
|
|
|
|
AvailableQueue.push_all(NotReady);
|
|
|
|
NotReady.clear();
|
|
|
|
}
|
|
|
|
|
2009-11-04 04:57:50 +08:00
|
|
|
// If we found a node to schedule...
|
2008-11-20 07:18:57 +08:00
|
|
|
if (FoundSUnit) {
|
Add two additional hazard recognizer functions
This adds two additional functions to the hazard recognizer interface. These
are optional (in the sense that the default implementations preserve the
current behavior), and used by the post-RA scheduler. Upcoming commits will use
this functionality in order to improve dispatch-group formation on the POWER7
and related cores. Dispatch groups are an odd construct: sometimes we need to
insert nops to force a new one to start (for performance reasons), and some
instructions need to appear in certain positions within a group, but the groups
are not fundamentally cycle based (they can contain instructions with data
dependencies with non-trivial latencies).
Motivation:
unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert
nops to force a new dispatch group to begin. We already have a NoopHazard, and
this is also still needed. However, NoopHazard only causes a nop to be inserted
if there are no other available instructions, and so is not always sufficient.
The number of nops to insert depends on state that only the hazard recognizer
has, so a general callback is necessary.
bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that
would start a new dispatch group when others are available that could be part
of the current dispatch group. In this case, we don't want to issue nops,
because the non-preferred instruction will implicitly start a new dispatch
group regardless.
Although the motivation for these functions is driven by the PowerPC backend,
they are completely general.
llvm-svn: 197084
2013-12-12 06:33:43 +08:00
|
|
|
// If we need to emit noops prior to this instruction, then do so.
|
|
|
|
unsigned NumPreNoops = HazardRec->PreEmitNoops(FoundSUnit);
|
|
|
|
for (unsigned i = 0; i != NumPreNoops; ++i)
|
|
|
|
emitNoop(CurCycle);
|
|
|
|
|
2009-11-04 04:57:50 +08:00
|
|
|
// ... schedule the node...
|
2009-11-21 03:32:48 +08:00
|
|
|
ScheduleNodeTopDown(FoundSUnit, CurCycle);
|
2009-01-16 09:33:36 +08:00
|
|
|
HazardRec->EmitInstruction(FoundSUnit);
|
2009-09-06 20:10:17 +08:00
|
|
|
CycleHasInsts = true;
|
2011-06-01 11:27:56 +08:00
|
|
|
if (HazardRec->atIssueLimit()) {
|
|
|
|
DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
|
|
|
|
HazardRec->AdvanceCycle();
|
|
|
|
++CurCycle;
|
|
|
|
CycleHasInsts = false;
|
|
|
|
}
|
2009-01-16 09:33:36 +08:00
|
|
|
} else {
|
2009-09-06 20:10:17 +08:00
|
|
|
if (CycleHasInsts) {
|
2010-01-05 09:26:01 +08:00
|
|
|
DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
|
2009-08-13 05:47:46 +08:00
|
|
|
HazardRec->AdvanceCycle();
|
|
|
|
} else if (!HasNoopHazards) {
|
|
|
|
// Otherwise, we have a pipeline stall, but no other problem,
|
|
|
|
// just advance the current cycle and try again.
|
2010-01-05 09:26:01 +08:00
|
|
|
DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
|
2009-08-13 05:47:46 +08:00
|
|
|
HazardRec->AdvanceCycle();
|
2009-11-21 03:32:48 +08:00
|
|
|
++NumStalls;
|
2009-08-13 05:47:46 +08:00
|
|
|
} else {
|
|
|
|
// Otherwise, we have no instructions to issue and we have instructions
|
|
|
|
// that will fault if we don't do this right. This is the case for
|
|
|
|
// processors without pipeline interlocks and other cases.
|
Add two additional hazard recognizer functions
This adds two additional functions to the hazard recognizer interface. These
are optional (in the sense that the default implementations preserve the
current behavior), and used by the post-RA scheduler. Upcoming commits will use
this functionality in order to improve dispatch-group formation on the POWER7
and related cores. Dispatch groups are an odd construct: sometimes we need to
insert nops to force a new one to start (for performance reasons), and some
instructions need to appear in certain positions within a group, but the groups
are not fundamentally cycle based (they can contain instructions with data
dependencies with non-trivial latencies).
Motivation:
unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert
nops to force a new dispatch group to begin. We already have a NoopHazard, and
this is also still needed. However, NoopHazard only causes a nop to be inserted
if there are no other available instructions, and so is not always sufficient.
The number of nops to insert depends on state that only the hazard recognizer
has, so a general callback is necessary.
bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that
would start a new dispatch group when others are available that could be part
of the current dispatch group. In this case, we don't want to issue nops,
because the non-preferred instruction will implicitly start a new dispatch
group regardless.
Although the motivation for these functions is driven by the PowerPC backend,
they are completely general.
llvm-svn: 197084
2013-12-12 06:33:43 +08:00
|
|
|
emitNoop(CurCycle);
|
2009-08-13 05:47:46 +08:00
|
|
|
}
|
|
|
|
|
2009-01-16 09:33:36 +08:00
|
|
|
++CurCycle;
|
2009-09-06 20:10:17 +08:00
|
|
|
CycleHasInsts = false;
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
2012-03-07 13:21:36 +08:00
|
|
|
unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false);
|
|
|
|
unsigned Noops = 0;
|
|
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
|
|
|
|
if (!Sequence[i])
|
|
|
|
++Noops;
|
|
|
|
assert(Sequence.size() - Noops == ScheduledNodes &&
|
|
|
|
"The number of nodes scheduled doesn't match the expected number!");
|
|
|
|
#endif // NDEBUG
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
2012-03-07 13:21:44 +08:00
|
|
|
|
|
|
|
// EmitSchedule - Emit the machine code in scheduled order.
|
|
|
|
void SchedulePostRATDList::EmitSchedule() {
|
2012-03-09 12:29:02 +08:00
|
|
|
RegionBegin = RegionEnd;
|
2012-03-07 13:21:44 +08:00
|
|
|
|
|
|
|
// If first instruction was a DBG_VALUE then put it back.
|
|
|
|
if (FirstDbgValue)
|
2012-03-09 12:29:02 +08:00
|
|
|
BB->splice(RegionEnd, BB, FirstDbgValue);
|
2012-03-07 13:21:44 +08:00
|
|
|
|
|
|
|
// Then re-insert them according to the given schedule.
|
|
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
|
|
if (SUnit *SU = Sequence[i])
|
2012-03-09 12:29:02 +08:00
|
|
|
BB->splice(RegionEnd, BB, SU->getInstr());
|
2012-03-07 13:21:44 +08:00
|
|
|
else
|
|
|
|
// Null SUnit* is a noop.
|
2012-03-09 12:29:02 +08:00
|
|
|
TII->insertNoop(*BB, RegionEnd);
|
2012-03-07 13:21:44 +08:00
|
|
|
|
|
|
|
// Update the Begin iterator, as the first instruction in the block
|
|
|
|
// may have been scheduled later.
|
|
|
|
if (i == 0)
|
2014-03-02 20:27:27 +08:00
|
|
|
RegionBegin = std::prev(RegionEnd);
|
2012-03-07 13:21:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Reinsert any remaining debug_values.
|
|
|
|
for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
|
|
|
|
DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
|
2014-03-02 20:27:27 +08:00
|
|
|
std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
|
2012-03-07 13:21:44 +08:00
|
|
|
MachineInstr *DbgValue = P.first;
|
|
|
|
MachineBasicBlock::iterator OrigPrivMI = P.second;
|
|
|
|
BB->splice(++OrigPrivMI, BB, DbgValue);
|
|
|
|
}
|
|
|
|
DbgValues.clear();
|
2014-04-14 08:51:57 +08:00
|
|
|
FirstDbgValue = nullptr;
|
2012-03-07 13:21:44 +08:00
|
|
|
}
|