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llvm-project/llvm/test/MC/Mips/set-mips-directives-bad.s

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[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips1 2>%t1
# RUN: FileCheck %s < %t1
# FIXME: At the moment we emit the wrong error message if we try to assemble the
# ll instruction using an unsupported architecture so we just check for "error"
# and ignore the rest of the message.
.text
.set noreorder
.set mips1
ll $2,-2($2) # CHECK: error:
.set mips2
dadd $2,$2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled
.set mips3
ldxc1 $f8,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled
.set mips4
luxc1 $f19,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled
.set mips5
clo $2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled
.set mips32
rotr $2,15 # CHECK: error: instruction requires a CPU feature not currently enabled
.set mips32r2
mod $2, $4, $6 # CHECK: error:instruction requires a CPU feature not currently enabled
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
.set mips64r3
.set mips32r3
daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
.set mips64r3
.set mips32r5
daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
.set mips32r6
daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
.set mips64
drotr32 $1,$14,15 # CHECK: error: instruction requires a CPU feature not currently enabled
.set mips64r2
mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
.set mips64r6
.set mips64r3
mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
.set mips64r6
.set mips64r5
mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00