2020-01-19 15:12:22 +08:00
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# RUN: llc -o - %s -start-after=livedebugvalues -O0 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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|
# RUN: llc -o - %s -start-after=livedebugvalues -O0 -mtriple=x86_64-unknown-linux-gnu -filetype=obj \
|
2018-11-02 09:31:52 +08:00
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# RUN: | llvm-dwarfdump -debug-info - | FileCheck %s --check-prefix=DWARF
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#
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# Verify that we have correct debug info for local variables in code
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# instrumented with AddressSanitizer.
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#
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# Generated from the source file test.cc:
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# int bar(int y) {
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# return y + 2;
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|
# }
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# with "clang++ -S -emit-llvm -mllvm -asan-skip-promotable-allocas=0 -fsanitize=address -O0 -g test.cc"
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#
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# The address of the (potentially now malloc'ed) alloca ends up
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# in rdi, after which it is spilled to the stack. We record the
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# spill OFFSET on the stack for checking the debug info below.
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# CHECK: #DEBUG_VALUE: bar:y <- [DW_OP_deref] [$rcx+0]
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# CHECK: movq %rcx, [[OFFSET:[0-9]+]](%rsp)
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# CHECK-NEXT: [[START_LABEL:.Ltmp[0-9]+]]
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# CHECK-NEXT: #DEBUG_VALUE: bar:y <- [DW_OP_plus_uconst [[OFFSET]], DW_OP_deref, DW_OP_deref]
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# This location should be valid until the end of the function.
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#
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# CHECK: movq %rbp, %rsp
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# CHECK-NEXT: [[END_LABEL:.Ltmp[0-9]+]]:
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#
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# CHECK: .Ldebug_loc{{[0-9]+}}:
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# We expect two location ranges for the variable.
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#
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# First, its address is stored in %rcx:
|
[DebugInfo] Stop changing labels for register-described parameter DBG_VALUEs
Summary:
This is a follow-up to D57510. This patch stops DebugHandlerBase from
changing the starting label for the first non-overlapping,
register-described parameter DBG_VALUEs to the beginning of the
function. That code did not consider what defined the registers, which
could result in the ranges for the debug values starting before their
defining instructions. We currently do not emit debug values for
constant values directly at the start of the function, so this code is
still useful for such values, but my intention is to remove the code
from DebugHandlerBase completely when we get there. One reason for
removing it is that the code violates the history map's ranges, which I
think can make it quite confusing when troubleshooting.
In D57510, PrologEpilogInserter was amended so that parameter DBG_VALUEs
now are kept at the start of the entry block, even after emission of
prologue code. That was done to reduce the degradation of debug
completeness from this patch. PR40638 is another example, where the
lexical-scope trimming that LDV does, in combination with scheduling,
results in instructions after the prologue being left without locations.
There might be other cases where the DBG_VALUEs are pushed further down,
for which the DebugHandlerBase code may be helpful, but as it now quite
often result in incorrect locations, even after the prologue, it seems
better to remove that code, and try to work our way up with accurate
locations.
In the long run we should maybe not aim to provide accurate locations
inside the prologue. Some single location descriptions, at least those
referring to stack values, generate inaccurate values inside the
epilogue, so we maybe should not aim to achieve accuracy for location
lists. However, it seems that we now emit line number programs that can
result in GDB and LLDB stopping inside the prologue when doing line
number stepping into functions. See PR40188 for more information.
A summary of some of the changed test cases is available in PR40188#c2.
Reviewers: aprantl, dblaikie, rnk, jmorse
Reviewed By: aprantl
Subscribers: jdoerfert, jholewinski, jvesely, javed.absar, llvm-commits
Tags: #debug-info, #llvm
Differential Revision: https://reviews.llvm.org/D57511
llvm-svn: 353928
2019-02-13 17:34:07 +08:00
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|
|
# CHECK: .quad .Ltmp0-.Lfunc_begin0
|
2018-11-02 09:31:52 +08:00
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|
# CHECK-NEXT: .quad [[START_LABEL]]-.Lfunc_begin0
|
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# CHECK: DW_OP_breg2
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# DWARF: DW_TAG_formal_parameter
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|
# DWARF: DW_AT_location
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|
# DWARF-NEXT: [{{.*}}, {{.*}}): DW_OP_breg2 RCX+0, DW_OP_deref
|
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|
|
#
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|
|
# Then it's addressed via %rsp:
|
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|
|
# CHECK: .quad [[START_LABEL]]-.Lfunc_begin0
|
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|
# CHECK-NEXT: .quad [[END_LABEL]]-.Lfunc_begin0
|
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|
# CHECK: DW_OP_breg7
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|
# CHECK-NEXT: [[OFFSET]]
|
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|
# CHECK: DW_OP_deref
|
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|
|
# DWARF-NEXT: [{{.*}}, {{.*}}): DW_OP_breg7 RSP+{{[0-9]+}}, DW_OP_deref, DW_OP_deref)
|
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|
|
--- |
|
|
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|
|
@__asan_option_detect_stack_use_after_return = external global i32
|
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|
@___asan_gen_ = private unnamed_addr constant [16 x i8] c"1 32 4 6 y.addr\00", align 1
|
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|
|
|
; Function Attrs: nounwind sanitize_address uwtable
|
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|
|
define i32 @_Z3bari(i32 %y) #0 !dbg !6 {
|
|
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|
|
entry:
|
|
|
|
|
%MyAlloca = alloca [64 x i8], align 32
|
|
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|
%0 = ptrtoint [64 x i8]* %MyAlloca to i64
|
|
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|
|
%1 = load i32, i32* @__asan_option_detect_stack_use_after_return
|
|
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|
|
%2 = icmp ne i32 %1, 0
|
|
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|
|
br i1 %2, label %3, label %5
|
|
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|
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|
|
; <label>:3: ; preds = %entry
|
|
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|
%4 = call i64 @__asan_stack_malloc_0(i64 64, i64 %0)
|
|
|
|
|
br label %5
|
|
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|
|
|
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|
|
; <label>:5: ; preds = %3, %entry
|
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|
%6 = phi i64 [ %0, %entry ], [ %4, %3 ]
|
|
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|
|
%7 = add i64 %6, 32
|
|
|
|
|
%8 = inttoptr i64 %7 to i32*
|
|
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|
|
%9 = inttoptr i64 %6 to i64*
|
|
|
|
|
store i64 1102416563, i64* %9
|
|
|
|
|
%10 = add i64 %6, 8
|
|
|
|
|
%11 = inttoptr i64 %10 to i64*
|
|
|
|
|
store i64 ptrtoint ([16 x i8]* @___asan_gen_ to i64), i64* %11
|
|
|
|
|
%12 = add i64 %6, 16
|
|
|
|
|
%13 = inttoptr i64 %12 to i64*
|
|
|
|
|
store i64 ptrtoint (i32 (i32)* @_Z3bari to i64), i64* %13
|
|
|
|
|
%14 = lshr i64 %6, 3
|
|
|
|
|
%15 = add i64 %14, 2147450880
|
|
|
|
|
%16 = add i64 %15, 0
|
|
|
|
|
%17 = inttoptr i64 %16 to i64*
|
|
|
|
|
store i64 -868083100587789839, i64* %17
|
|
|
|
|
%18 = ptrtoint i32* %8 to i64
|
|
|
|
|
%19 = lshr i64 %18, 3
|
|
|
|
|
%20 = add i64 %19, 2147450880
|
|
|
|
|
%21 = inttoptr i64 %20 to i8*
|
|
|
|
|
%22 = load i8, i8* %21
|
|
|
|
|
%23 = icmp ne i8 %22, 0
|
|
|
|
|
call void @llvm.dbg.declare(metadata i32* %8, metadata !10, metadata !DIExpression(DW_OP_deref)), !dbg !11
|
|
|
|
|
br i1 %23, label %24, label %30
|
|
|
|
|
|
|
|
|
|
; <label>:24: ; preds = %5
|
|
|
|
|
%25 = and i64 %18, 7
|
|
|
|
|
%26 = add i64 %25, 3
|
|
|
|
|
%27 = trunc i64 %26 to i8
|
|
|
|
|
%28 = icmp sge i8 %27, %22
|
|
|
|
|
br i1 %28, label %29, label %30
|
|
|
|
|
|
|
|
|
|
; <label>:29: ; preds = %24
|
|
|
|
|
call void @__asan_report_store4(i64 %18)
|
|
|
|
|
call void asm sideeffect "", ""()
|
|
|
|
|
unreachable
|
|
|
|
|
|
|
|
|
|
; <label>:30: ; preds = %24, %5
|
|
|
|
|
store i32 %y, i32* %8, align 4
|
|
|
|
|
%31 = ptrtoint i32* %8 to i64, !dbg !12
|
|
|
|
|
%32 = lshr i64 %31, 3, !dbg !12
|
|
|
|
|
%33 = add i64 %32, 2147450880, !dbg !12
|
|
|
|
|
%34 = inttoptr i64 %33 to i8*, !dbg !12
|
|
|
|
|
%35 = load i8, i8* %34, !dbg !12
|
|
|
|
|
%36 = icmp ne i8 %35, 0, !dbg !12
|
|
|
|
|
br i1 %36, label %37, label %43, !dbg !12
|
|
|
|
|
|
|
|
|
|
; <label>:37: ; preds = %30
|
|
|
|
|
%38 = and i64 %31, 7, !dbg !12
|
|
|
|
|
%39 = add i64 %38, 3, !dbg !12
|
|
|
|
|
%40 = trunc i64 %39 to i8, !dbg !12
|
|
|
|
|
%41 = icmp sge i8 %40, %35, !dbg !12
|
|
|
|
|
br i1 %41, label %42, label %43
|
|
|
|
|
|
|
|
|
|
; <label>:42: ; preds = %37
|
|
|
|
|
call void @__asan_report_load4(i64 %31), !dbg !12
|
|
|
|
|
call void asm sideeffect "", ""()
|
|
|
|
|
unreachable
|
|
|
|
|
|
|
|
|
|
; <label>:43: ; preds = %37, %30
|
|
|
|
|
%44 = load i32, i32* %8, align 4, !dbg !12
|
|
|
|
|
%add = add nsw i32 %44, 2, !dbg !12
|
|
|
|
|
store i64 1172321806, i64* %9, !dbg !12
|
|
|
|
|
%45 = icmp ne i64 %6, %0, !dbg !12
|
|
|
|
|
br i1 %45, label %46, label %53, !dbg !12
|
|
|
|
|
|
|
|
|
|
; <label>:46: ; preds = %43
|
|
|
|
|
%47 = add i64 %15, 0, !dbg !12
|
|
|
|
|
%48 = inttoptr i64 %47 to i64*, !dbg !12
|
|
|
|
|
store i64 -723401728380766731, i64* %48, !dbg !12
|
|
|
|
|
%49 = add i64 %6, 56, !dbg !12
|
|
|
|
|
%50 = inttoptr i64 %49 to i64*, !dbg !12
|
|
|
|
|
%51 = load i64, i64* %50, !dbg !12
|
|
|
|
|
%52 = inttoptr i64 %51 to i8*, !dbg !12
|
|
|
|
|
store i8 0, i8* %52, !dbg !12
|
|
|
|
|
br label %56, !dbg !12
|
|
|
|
|
|
|
|
|
|
; <label>:53: ; preds = %43
|
|
|
|
|
%54 = add i64 %15, 0, !dbg !12
|
|
|
|
|
%55 = inttoptr i64 %54 to i64*, !dbg !12
|
|
|
|
|
store i64 0, i64* %55, !dbg !12
|
|
|
|
|
br label %56, !dbg !12
|
|
|
|
|
|
|
|
|
|
; <label>:56: ; preds = %53, %46
|
|
|
|
|
ret i32 %add, !dbg !12
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Function Attrs: nounwind readnone speculatable
|
|
|
|
|
declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
|
|
|
|
|
|
|
|
|
|
declare void @__asan_init_v3()
|
|
|
|
|
|
|
|
|
|
declare void @__asan_report_load4(i64)
|
|
|
|
|
|
|
|
|
|
declare void @__asan_report_store4(i64)
|
|
|
|
|
|
|
|
|
|
declare i64 @__asan_stack_malloc_0(i64, i64)
|
|
|
|
|
|
|
|
|
|
; Function Attrs: nounwind
|
|
|
|
|
declare void @llvm.stackprotector(i8*, i8**) #2
|
|
|
|
|
|
2019-12-25 07:52:21 +08:00
|
|
|
attributes #0 = { nounwind sanitize_address uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
2018-11-02 09:31:52 +08:00
|
|
|
attributes #1 = { nounwind readnone speculatable }
|
|
|
|
|
attributes #2 = { nounwind }
|
|
|
|
|
|
|
|
|
|
!llvm.dbg.cu = !{!0}
|
|
|
|
|
!llvm.module.flags = !{!3, !4}
|
|
|
|
|
!llvm.ident = !{!5}
|
|
|
|
|
|
|
|
|
|
!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 3.5.0 (209308)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2)
|
|
|
|
|
!1 = !DIFile(filename: "test.cc", directory: "/llvm_cmake_gcc")
|
|
|
|
|
!2 = !{}
|
|
|
|
|
!3 = !{i32 2, !"Dwarf Version", i32 4}
|
|
|
|
|
!4 = !{i32 2, !"Debug Info Version", i32 3}
|
|
|
|
|
!5 = !{!"clang version 3.5.0 (209308)"}
|
|
|
|
|
!6 = distinct !DISubprogram(name: "bar", linkageName: "_Z3bari", scope: !1, file: !1, line: 1, type: !7, isLocal: false, isDefinition: true, scopeLine: 1, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2)
|
|
|
|
|
!7 = !DISubroutineType(types: !8)
|
|
|
|
|
!8 = !{!9, !9}
|
|
|
|
|
!9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
|
|
|
|
|
!10 = !DILocalVariable(name: "y", arg: 1, scope: !6, file: !1, line: 1, type: !9)
|
|
|
|
|
!11 = !DILocation(line: 0, scope: !6)
|
|
|
|
|
!12 = !DILocation(line: 2, scope: !6)
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
name: _Z3bari
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 16
|
2018-11-02 09:31:52 +08:00
|
|
|
tracksRegLiveness: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$edi' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
stackSize: 152
|
|
|
|
|
offsetAdjustment: -160
|
|
|
|
|
maxAlignment: 32
|
|
|
|
|
adjustsStack: true
|
|
|
|
|
hasCalls: true
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
fixedStack:
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default }
|
2018-11-02 09:31:52 +08:00
|
|
|
stack:
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 0, name: MyAlloca, offset: -96, size: 64, alignment: 32, stack-id: default }
|
|
|
|
|
- { id: 1, type: spill-slot, offset: -100, size: 4, alignment: 4, stack-id: default }
|
|
|
|
|
- { id: 2, type: spill-slot, offset: -112, size: 8, alignment: 8, stack-id: default }
|
|
|
|
|
- { id: 3, type: spill-slot, offset: -120, size: 8, alignment: 8, stack-id: default }
|
|
|
|
|
- { id: 4, type: spill-slot, offset: -128, size: 8, alignment: 8, stack-id: default }
|
|
|
|
|
- { id: 5, type: spill-slot, offset: -136, size: 8, alignment: 8, stack-id: default }
|
|
|
|
|
- { id: 6, type: spill-slot, offset: -144, size: 8, alignment: 8, stack-id: default }
|
|
|
|
|
- { id: 7, type: spill-slot, offset: -145, size: 1, alignment: 1, stack-id: default }
|
|
|
|
|
- { id: 8, type: spill-slot, offset: -146, size: 1, alignment: 1, stack-id: default }
|
|
|
|
|
- { id: 9, type: spill-slot, offset: -152, size: 4, alignment: 4, stack-id: default }
|
2018-11-02 09:31:52 +08:00
|
|
|
body: |
|
|
|
|
|
bb.0.entry:
|
|
|
|
|
liveins: $edi
|
|
|
|
|
|
|
|
|
|
frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
|
|
|
|
|
CFI_INSTRUCTION def_cfa_offset 16
|
|
|
|
|
CFI_INSTRUCTION offset $rbp, -16
|
|
|
|
|
$rbp = frame-setup MOV64rr $rsp
|
|
|
|
|
CFI_INSTRUCTION def_cfa_register $rbp
|
|
|
|
|
$rsp = frame-setup AND64ri8 $rsp, -32, implicit-def dead $eflags
|
|
|
|
|
$rsp = frame-setup SUB64ri32 $rsp, 160, implicit-def dead $eflags
|
|
|
|
|
renamable $rax = LEA64r $rsp, 1, $noreg, 64, $noreg
|
|
|
|
|
CMP32mi8 $noreg, 1, $noreg, @__asan_option_detect_stack_use_after_return, $noreg, 0, implicit-def $eflags :: (load 4 from @__asan_option_detect_stack_use_after_return)
|
|
|
|
|
$rcx = MOV64rr $rax
|
|
|
|
|
MOV32mr $rsp, 1, $noreg, 60, $noreg, killed $edi :: (store 4 into %stack.1)
|
|
|
|
|
MOV64mr $rsp, 1, $noreg, 48, $noreg, killed $rax :: (store 8 into %stack.2)
|
|
|
|
|
MOV64mr $rsp, 1, $noreg, 40, $noreg, killed $rcx :: (store 8 into %stack.3)
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.2, 4, implicit $eflags
|
2018-11-02 09:31:52 +08:00
|
|
|
|
|
|
|
|
bb.1 (%ir-block.3):
|
|
|
|
|
$edi = MOV32ri 64, implicit-def $rdi
|
|
|
|
|
$rsi = MOV64rm $rsp, 1, $noreg, 48, $noreg :: (load 8 from %stack.2)
|
|
|
|
|
CALL64pcrel32 @__asan_stack_malloc_0, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit killed $rsi, implicit-def $rax
|
|
|
|
|
MOV64mr $rsp, 1, $noreg, 40, $noreg, killed $rax :: (store 8 into %stack.3)
|
|
|
|
|
|
|
|
|
|
bb.2 (%ir-block.5):
|
|
|
|
|
$rax = MOV64rm $rsp, 1, $noreg, 40, $noreg :: (load 8 from %stack.3)
|
|
|
|
|
$rcx = MOV64rr $rax
|
|
|
|
|
renamable $rcx = ADD64ri8 renamable $rcx, 32, implicit-def $eflags
|
|
|
|
|
MOV64mi32 renamable $rax, 1, $noreg, 0, $noreg, 1102416563 :: (store 8 into %ir.9)
|
|
|
|
|
renamable $rdx = MOV64ri @___asan_gen_
|
|
|
|
|
MOV64mr renamable $rax, 1, $noreg, 8, $noreg, killed renamable $rdx :: (store 8 into %ir.11)
|
|
|
|
|
renamable $rdx = MOV64ri @_Z3bari
|
|
|
|
|
MOV64mr renamable $rax, 1, $noreg, 16, $noreg, killed renamable $rdx :: (store 8 into %ir.13)
|
|
|
|
|
$rdx = MOV64rr $rax
|
|
|
|
|
renamable $rdx = SHR64ri renamable $rdx, 3, implicit-def $eflags
|
|
|
|
|
$rsi = MOV64rr $rdx
|
|
|
|
|
renamable $rsi = ADD64ri32 renamable $rsi, 2147450880, implicit-def $eflags
|
|
|
|
|
renamable $rdi = MOV64ri -868083100587789839
|
|
|
|
|
MOV64mr killed renamable $rdx, 1, $noreg, 2147450880, $noreg, killed renamable $rdi :: (store 8 into %ir.17)
|
|
|
|
|
$rdx = MOV64rr $rcx
|
|
|
|
|
renamable $rdx = SHR64ri renamable $rdx, 3, implicit-def $eflags
|
|
|
|
|
renamable $r8b = MOV8rm killed renamable $rdx, 1, $noreg, 2147450880, $noreg :: (load 1 from %ir.21)
|
|
|
|
|
DBG_VALUE renamable $rcx, 0, !10, !DIExpression(DW_OP_deref), debug-location !11
|
|
|
|
|
CMP8ri renamable $r8b, 0, implicit-def $eflags
|
|
|
|
|
MOV64mr $rsp, 1, $noreg, 32, $noreg, killed $rax :: (store 8 into %stack.4)
|
|
|
|
|
MOV64mr $rsp, 1, $noreg, 24, $noreg, killed $rcx :: (store 8 into %stack.5)
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
MOV64mr $rsp, 1, $noreg, 16, $noreg, killed $rsi :: (store 8 into %stack.6)
|
|
|
|
|
MOV8mr $rsp, 1, $noreg, 15, $noreg, killed $r8b :: (store 1 into %stack.7)
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.5, 4, implicit $eflags
|
2018-11-02 09:31:52 +08:00
|
|
|
|
|
|
|
|
bb.3 (%ir-block.24):
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
$rax = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
|
|
|
|
|
renamable $rax = AND64ri8 renamable $rax, 7, implicit-def $eflags
|
|
|
|
|
renamable $rax = ADD64ri8 renamable $rax, 3, implicit-def $eflags
|
|
|
|
|
$cl = MOV8rr $al, implicit killed $rax
|
|
|
|
|
$dl = MOV8rm $rsp, 1, $noreg, 15, $noreg :: (load 1 from %stack.7)
|
|
|
|
|
CMP8rr killed renamable $cl, killed renamable $dl, implicit-def $eflags
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.5, 12, implicit $eflags
|
2018-11-02 09:31:52 +08:00
|
|
|
|
|
|
|
|
bb.4 (%ir-block.29):
|
|
|
|
|
successors:
|
|
|
|
|
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
$rdi = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
|
|
|
|
|
CALL64pcrel32 @__asan_report_store4, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi
|
|
|
|
|
INLINEASM &"", 1
|
|
|
|
|
|
|
|
|
|
bb.5 (%ir-block.30):
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
$rax = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
|
|
|
|
|
$ecx = MOV32rm $rsp, 1, $noreg, 60, $noreg :: (load 4 from %stack.1)
|
|
|
|
|
MOV32mr renamable $rax, 1, $noreg, 0, $noreg, killed renamable $ecx :: (store 4 into %ir.8)
|
|
|
|
|
renamable $rax = SHR64ri renamable $rax, 3, implicit-def $eflags, debug-location !12
|
|
|
|
|
renamable $dl = MOV8rm killed renamable $rax, 1, $noreg, 2147450880, $noreg, debug-location !12 :: (load 1 from %ir.34)
|
|
|
|
|
CMP8ri renamable $dl, 0, implicit-def $eflags, debug-location !12
|
|
|
|
|
MOV8mr $rsp, 1, $noreg, 14, $noreg, killed $dl :: (store 1 into %stack.8)
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.8, 4, implicit $eflags, debug-location !12
|
2018-11-02 09:31:52 +08:00
|
|
|
|
|
|
|
|
bb.6 (%ir-block.37):
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
$rax = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
|
|
|
|
|
renamable $rax = AND64ri8 renamable $rax, 7, implicit-def $eflags, debug-location !12
|
|
|
|
|
renamable $rax = ADD64ri8 renamable $rax, 3, implicit-def $eflags, debug-location !12
|
|
|
|
|
$cl = MOV8rr $al, implicit killed $rax, debug-location !12
|
|
|
|
|
$dl = MOV8rm $rsp, 1, $noreg, 14, $noreg :: (load 1 from %stack.8)
|
|
|
|
|
CMP8rr killed renamable $cl, killed renamable $dl, implicit-def $eflags, debug-location !12
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.8, 12, implicit $eflags
|
2018-11-02 09:31:52 +08:00
|
|
|
|
|
|
|
|
bb.7 (%ir-block.42):
|
|
|
|
|
successors:
|
|
|
|
|
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
$rdi = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
|
|
|
|
|
CALL64pcrel32 @__asan_report_load4, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, debug-location !12
|
|
|
|
|
INLINEASM &"", 1
|
|
|
|
|
|
|
|
|
|
bb.8 (%ir-block.43):
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
$rax = MOV64rm $rsp, 1, $noreg, 24, $noreg :: (load 8 from %stack.5)
|
|
|
|
|
renamable $ecx = MOV32rm killed renamable $rax, 1, $noreg, 0, $noreg, debug-location !12 :: (load 4 from %ir.8)
|
|
|
|
|
renamable $ecx = ADD32ri8 renamable $ecx, 2, implicit-def $eflags, debug-location !12
|
|
|
|
|
$rdx = MOV64rm $rsp, 1, $noreg, 32, $noreg :: (load 8 from %stack.4)
|
|
|
|
|
MOV64mi32 renamable $rdx, 1, $noreg, 0, $noreg, 1172321806, debug-location !12 :: (store 8 into %ir.9)
|
|
|
|
|
$rsi = MOV64rm $rsp, 1, $noreg, 48, $noreg :: (load 8 from %stack.2)
|
|
|
|
|
CMP64rr killed renamable $rdx, killed renamable $rsi, implicit-def $eflags, debug-location !12
|
|
|
|
|
MOV32mr $rsp, 1, $noreg, 8, $noreg, killed $ecx :: (store 4 into %stack.9)
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.10, 4, implicit $eflags, debug-location !12
|
2018-11-02 09:31:52 +08:00
|
|
|
|
|
|
|
|
bb.9 (%ir-block.46):
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
renamable $rax = MOV64ri -723401728380766731, debug-location !12
|
|
|
|
|
$rcx = MOV64rm $rsp, 1, $noreg, 16, $noreg :: (load 8 from %stack.6)
|
|
|
|
|
MOV64mr killed renamable $rcx, 1, $noreg, 0, $noreg, killed renamable $rax, debug-location !12 :: (store 8 into %ir.48)
|
|
|
|
|
$rax = MOV64rm $rsp, 1, $noreg, 32, $noreg :: (load 8 from %stack.4)
|
|
|
|
|
renamable $rdx = MOV64rm killed renamable $rax, 1, $noreg, 56, $noreg, debug-location !12 :: (load 8 from %ir.50)
|
|
|
|
|
MOV8mi killed renamable $rdx, 1, $noreg, 0, $noreg, 0, debug-location !12 :: (store 1 into %ir.52)
|
|
|
|
|
JMP_1 %bb.11, debug-location !12
|
|
|
|
|
|
|
|
|
|
bb.10 (%ir-block.53):
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
$rax = MOV64rm $rsp, 1, $noreg, 16, $noreg :: (load 8 from %stack.6)
|
|
|
|
|
MOV64mi32 killed renamable $rax, 1, $noreg, 0, $noreg, 0, debug-location !12 :: (store 8 into %ir.55)
|
|
|
|
|
|
|
|
|
|
bb.11 (%ir-block.56):
|
|
|
|
|
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
|
|
|
|
|
$eax = MOV32rm $rsp, 1, $noreg, 8, $noreg :: (load 4 from %stack.9)
|
|
|
|
|
$rsp = MOV64rr $rbp, debug-location !12
|
|
|
|
|
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !12
|
|
|
|
|
CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !12
|
|
|
|
|
RETQ implicit killed $eax, debug-location !12
|
|
|
|
|
|
|
|
|
|
...
|