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llvm-project/llvm/test/CodeGen/X86/2011-12-8-bitcastintprom.ll

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[X86][SSE] Regenerate extraction from promotion test Added tests for SSE2 as well as SSE41 llvm-svn: 275878
2016-07-19 02:53:15 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
Fix a bug in the integer-promotion of bitcast operations on vector types. We must not issue a bitcast operation for integer-promotion of vector types, because the location of the values in the vector may be different. llvm-svn: 146150
2011-12-08 21:10:01 +08:00
; Make sure that the conversion between v4i8 to v2i16 is not a simple bitcast.
define void @prom_bug(<4 x i8> %t, i16* %p) {
[X86][SSE] Regenerate extraction from promotion test Added tests for SSE2 as well as SSE41 llvm-svn: 275878
2016-07-19 02:53:15 +08:00
; SSE2-LABEL: prom_bug:
; SSE2: ## BB#0:
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,6,7]
; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: movw %ax, (%rdi)
; SSE2-NEXT: retq
;
; SSE41-LABEL: prom_bug:
; SSE41: ## BB#0:
; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
2016-07-21 22:54:17 +08:00
; SSE41-NEXT: pextrw $0, %xmm0, (%rdi)
[X86][SSE] Regenerate extraction from promotion test Added tests for SSE2 as well as SSE41 llvm-svn: 275878
2016-07-19 02:53:15 +08:00
; SSE41-NEXT: retq
Fix a bug in the integer-promotion of bitcast operations on vector types. We must not issue a bitcast operation for integer-promotion of vector types, because the location of the values in the vector may be different. llvm-svn: 146150
2011-12-08 21:10:01 +08:00
%r = bitcast <4 x i8> %t to <2 x i16>
%o = extractelement <2 x i16> %r, i32 0
store i16 %o, i16* %p
ret void
}