2017-08-04 06:12:30 +08:00
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//===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
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2007-06-06 15:42:06 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2007-06-06 15:42:06 +08:00
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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2014-08-14 00:26:38 +08:00
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
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#define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
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2007-06-06 15:42:06 +08:00
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2015-01-30 07:27:36 +08:00
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#include "MCTargetDesc/MipsABIInfo.h"
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2014-01-07 19:48:04 +08:00
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#include "MCTargetDesc/MipsBaseInfo.h"
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2017-08-04 06:12:30 +08:00
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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2007-06-06 15:42:06 +08:00
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#include "Mips.h"
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2018-04-11 23:12:32 +08:00
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#include "llvm/CodeGen/CallingConvLower.h"
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2017-08-04 06:12:30 +08:00
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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2012-03-18 02:46:09 +08:00
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#include "llvm/CodeGen/SelectionDAG.h"
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2017-08-04 06:12:30 +08:00
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetLowering.h"
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2018-03-30 01:21:10 +08:00
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#include "llvm/CodeGen/ValueTypes.h"
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2017-08-04 06:12:30 +08:00
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Type.h"
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2018-03-24 07:58:25 +08:00
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#include "llvm/Support/MachineValueType.h"
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2017-08-04 06:12:30 +08:00
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#include "llvm/Target/TargetMachine.h"
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#include <algorithm>
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#include <cassert>
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2013-01-23 04:05:56 +08:00
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#include <deque>
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2013-01-24 12:24:02 +08:00
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#include <string>
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2017-08-04 06:12:30 +08:00
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#include <utility>
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#include <vector>
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2007-06-06 15:42:06 +08:00
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namespace llvm {
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2017-08-04 06:12:30 +08:00
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class Argument;
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class CCState;
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class CCValAssign;
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class FastISel;
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class FunctionLoweringInfo;
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class MachineBasicBlock;
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class MachineFrameInfo;
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class MachineInstr;
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class MipsCCState;
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class MipsFunctionInfo;
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class MipsSubtarget;
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class MipsTargetMachine;
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class TargetLibraryInfo;
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class TargetRegisterClass;
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2007-06-06 15:42:06 +08:00
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namespace MipsISD {
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2017-08-04 06:12:30 +08:00
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2015-05-08 05:33:59 +08:00
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enum NodeType : unsigned {
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2007-06-06 15:42:06 +08:00
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// Start the numbering from where ISD NodeType finishes.
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2008-09-24 02:42:32 +08:00
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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2007-06-06 15:42:06 +08:00
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// Jump and link (call)
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JmpLink,
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2012-10-20 04:59:39 +08:00
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// Tail call
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TailCall,
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2017-01-27 19:36:52 +08:00
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// Get the Highest (63-48) 16 bits from a 64-bit immediate
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Highest,
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// Get the Higher (47-32) 16 bits from a 64-bit immediate
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Higher,
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// Get the High 16 bits from a 32/64-bit immediate
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2007-06-06 15:42:06 +08:00
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// No relation with Mips Hi register
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2011-03-05 01:51:39 +08:00
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Hi,
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2007-06-06 15:42:06 +08:00
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2017-01-27 19:36:52 +08:00
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// Get the Lower 16 bits from a 32/64-bit immediate
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2007-06-06 15:42:06 +08:00
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// No relation with Mips Lo register
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2011-03-05 01:51:39 +08:00
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Lo,
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2007-06-06 15:42:06 +08:00
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2017-01-27 19:36:52 +08:00
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// Get the High 16 bits from a 32 bit immediate for accessing the GOT.
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GotHi,
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2018-07-24 21:47:52 +08:00
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// Get the High 16 bits from a 32-bit immediate for accessing TLS.
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TlsHi,
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2008-07-22 02:52:34 +08:00
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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2011-05-31 10:53:58 +08:00
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// Thread Pointer
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ThreadPointer,
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2018-04-27 21:30:27 +08:00
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// Vector Floating Point Multiply and Subtract
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FMS,
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2008-07-09 12:45:36 +08:00
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// Floating Point Branch Conditional
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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FPBrcond,
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2008-07-09 12:45:36 +08:00
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// Floating Point Compare
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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FPCmp,
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2017-07-20 21:08:18 +08:00
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// Floating point select
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FSELECT,
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// Node used to generate an MTC1 i32 to f64 instruction
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MTC1_D64,
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2011-04-01 02:26:17 +08:00
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// Floating Point Conditional Moves
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CMovFP_T,
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CMovFP_F,
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2013-05-17 05:17:15 +08:00
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// FP-to-int truncation node.
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TruncIntFP,
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2011-03-05 01:51:39 +08:00
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// Return
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2011-01-19 03:29:17 +08:00
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Ret,
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2015-10-26 20:38:43 +08:00
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// Interrupt, exception, error trap Return
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ERet,
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// Software Exception Return.
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2013-01-30 08:26:49 +08:00
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EH_RETURN,
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2013-03-30 09:14:04 +08:00
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// Node used to extract integer from accumulator.
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2013-10-15 09:12:50 +08:00
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MFHI,
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MFLO,
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2013-03-30 09:14:04 +08:00
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// Node used to insert integers to accumulator.
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2013-10-15 09:12:50 +08:00
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MTLOHI,
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2013-03-30 09:14:04 +08:00
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// Mult nodes.
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Mult,
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Multu,
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2011-01-19 03:29:17 +08:00
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// MAdd/Sub nodes
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MAdd,
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MAddu,
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MSub,
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2011-03-05 05:03:24 +08:00
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MSubu,
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// DivRem(u)
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DivRem,
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2011-04-16 03:52:08 +08:00
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DivRemU,
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2013-03-30 09:14:04 +08:00
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DivRem16,
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DivRemU16,
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2011-04-16 03:52:08 +08:00
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BuildPairF64,
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2011-05-28 09:07:07 +08:00
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ExtractElementF64,
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2011-12-09 09:53:17 +08:00
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Wrapper,
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2011-06-21 08:40:49 +08:00
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2011-07-20 07:30:50 +08:00
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DynAlloc,
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2011-08-17 10:05:42 +08:00
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Sync,
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Ext,
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2012-06-02 08:03:12 +08:00
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Ins,
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[Mips] Add support to match more patterns for DEXT and CINS
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
2017-03-15 21:10:08 +08:00
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CIns,
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2012-06-02 08:03:12 +08:00
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2012-09-22 07:52:47 +08:00
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// EXTR.W instrinsic nodes.
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EXTP,
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EXTPDP,
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EXTR_S_H,
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EXTR_W,
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EXTR_R_W,
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EXTR_RS_W,
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SHILO,
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MTHLIP,
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// DPA.W intrinsic nodes.
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MULSAQ_S_W_PH,
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MAQ_S_W_PHL,
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MAQ_S_W_PHR,
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MAQ_SA_W_PHL,
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MAQ_SA_W_PHR,
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DPAU_H_QBL,
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DPAU_H_QBR,
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DPSU_H_QBL,
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DPSU_H_QBR,
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DPAQ_S_W_PH,
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DPSQ_S_W_PH,
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DPAQ_SA_L_W,
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DPSQ_SA_L_W,
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DPA_W_PH,
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DPS_W_PH,
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DPAQX_S_W_PH,
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DPAQX_SA_W_PH,
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DPAX_W_PH,
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DPSX_W_PH,
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DPSQX_S_W_PH,
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DPSQX_SA_W_PH,
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MULSA_W_PH,
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MULT,
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MULTU,
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MADD_DSP,
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MADDU_DSP,
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MSUB_DSP,
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MSUBU_DSP,
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2013-04-20 07:21:32 +08:00
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// DSP shift nodes.
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SHLL_DSP,
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SHRA_DSP,
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SHRL_DSP,
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2013-05-01 06:37:26 +08:00
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// DSP setcc and select_cc nodes.
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SETCC_DSP,
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SELECT_CC_DSP,
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2013-09-23 20:02:46 +08:00
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// Vector comparisons.
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2013-09-24 18:46:19 +08:00
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// These take a vector and return a boolean.
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2013-08-28 20:14:50 +08:00
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VALL_ZERO,
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VANY_ZERO,
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VALL_NONZERO,
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VANY_NONZERO,
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2013-09-24 18:46:19 +08:00
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// These take a vector and return a vector bitmask.
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VCEQ,
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VCLE_S,
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VCLE_U,
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VCLT_S,
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VCLT_U,
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2013-09-24 22:02:15 +08:00
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// Vector Shuffle with mask as an operand
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VSHF, // Generic shuffle
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2013-09-24 22:20:00 +08:00
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SHF, // 4-element set shuffle.
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2013-09-24 22:36:12 +08:00
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ILVEV, // Interleave even elements
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ILVOD, // Interleave odd elements
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ILVL, // Interleave left elements
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ILVR, // Interleave right elements
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2013-09-24 22:53:25 +08:00
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PCKEV, // Pack even elements
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PCKOD, // Pack odd elements
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2013-09-24 22:02:15 +08:00
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[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 18:35:28 +08:00
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// Vector Lane Copy
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INSVE, // Copy element from one vector to another
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2013-09-23 21:22:24 +08:00
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// Combined (XOR (OR $a, $b), -1)
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VNOR,
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2013-09-23 22:03:12 +08:00
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// Extended vector element extraction
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VEXTRACT_SEXT_ELT,
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VEXTRACT_ZEXT_ELT,
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2012-06-02 08:03:12 +08:00
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// Load/Store Left/Right nodes.
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|
|
LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
|
|
|
|
LWR,
|
|
|
|
SWL,
|
|
|
|
SWR,
|
|
|
|
LDL,
|
|
|
|
LDR,
|
|
|
|
SDL,
|
|
|
|
SDR
|
2007-06-06 15:42:06 +08:00
|
|
|
};
|
2017-08-04 06:12:30 +08:00
|
|
|
|
|
|
|
} // ene namespace MipsISD
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2011-04-16 05:51:11 +08:00
|
|
|
//===--------------------------------------------------------------------===//
|
2007-06-06 15:42:06 +08:00
|
|
|
// TargetLowering Implementation
|
2011-04-16 05:51:11 +08:00
|
|
|
//===--------------------------------------------------------------------===//
|
2011-03-05 01:51:39 +08:00
|
|
|
|
2009-08-13 13:41:27 +08:00
|
|
|
class MipsTargetLowering : public TargetLowering {
|
2013-12-20 00:12:56 +08:00
|
|
|
bool isMicroMips;
|
2017-08-04 06:12:30 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
public:
|
2014-09-20 07:30:42 +08:00
|
|
|
explicit MipsTargetLowering(const MipsTargetMachine &TM,
|
2014-07-19 07:25:04 +08:00
|
|
|
const MipsSubtarget &STI);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2014-09-20 07:30:42 +08:00
|
|
|
static const MipsTargetLowering *create(const MipsTargetMachine &TM,
|
2014-07-19 07:25:04 +08:00
|
|
|
const MipsSubtarget &STI);
|
2011-11-08 02:59:49 +08:00
|
|
|
|
2014-04-18 06:15:34 +08:00
|
|
|
/// createFastISel - This method returns a target specific FastISel object,
|
|
|
|
/// or null if the target does not support "fast" ISel.
|
|
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
|
|
const TargetLibraryInfo *libInfo) const override;
|
|
|
|
|
2015-07-09 23:12:23 +08:00
|
|
|
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
|
2015-07-09 10:09:20 +08:00
|
|
|
return MVT::i32;
|
|
|
|
}
|
2011-08-13 05:30:06 +08:00
|
|
|
|
2018-07-26 18:59:35 +08:00
|
|
|
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
|
|
|
|
ISD::NodeType) const override;
|
|
|
|
|
[MIPS] add overrides for isCheapToSpeculateCttz() and isCheapToSpeculateCtlz()
MIPS32 has instructions for efficient count-leading/trailing-zeros, so this should be
considered a cheap operation (and therefore fair game for speculation) for any MIPS32
implementation.
The net result of allowing this speculation for the regression tests in this patch is
that we get this code:
ctlz:
jr $ra
clz $2, $4
cttz:
addiu $1, $4, -1
not $2, $4
and $1, $2, $1
clz $1, $1
addiu $2, $zero, 32
jr $ra
subu $2, $2, $1
Instead of:
ctlz:
beqz $4, $BB0_2
addiu $2, $zero, 32
clz $2, $4
$BB0_2:
jr $ra
nop
cttz:
beqz $4, $BB1_2
addiu $2, $zero, 32
addiu $1, $4, -1
not $2, $4
and $1, $2, $1
clz $1, $1
addiu $2, $zero, 32
subu $2, $2, $1
$BB1_2:
jr $ra
nop
See D14469 for the larger motivation.
Differential Revision: http://reviews.llvm.org/D14500
llvm-svn: 252755
2015-11-12 01:24:56 +08:00
|
|
|
bool isCheapToSpeculateCttz() const override;
|
|
|
|
bool isCheapToSpeculateCtlz() const override;
|
2019-04-17 04:57:28 +08:00
|
|
|
bool shouldFoldConstantShiftPairToMask(const SDNode *N,
|
|
|
|
CombineLevel Level) const override;
|
[MIPS] add overrides for isCheapToSpeculateCttz() and isCheapToSpeculateCtlz()
MIPS32 has instructions for efficient count-leading/trailing-zeros, so this should be
considered a cheap operation (and therefore fair game for speculation) for any MIPS32
implementation.
The net result of allowing this speculation for the regression tests in this patch is
that we get this code:
ctlz:
jr $ra
clz $2, $4
cttz:
addiu $1, $4, -1
not $2, $4
and $1, $2, $1
clz $1, $1
addiu $2, $zero, 32
jr $ra
subu $2, $2, $1
Instead of:
ctlz:
beqz $4, $BB0_2
addiu $2, $zero, 32
clz $2, $4
$BB0_2:
jr $ra
nop
cttz:
beqz $4, $BB1_2
addiu $2, $zero, 32
addiu $1, $4, -1
not $2, $4
and $1, $2, $1
clz $1, $1
addiu $2, $zero, 32
subu $2, $2, $1
$BB1_2:
jr $ra
nop
See D14469 for the larger motivation.
Differential Revision: http://reviews.llvm.org/D14500
llvm-svn: 252755
2015-11-12 01:24:56 +08:00
|
|
|
|
Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 22:37:08 +08:00
|
|
|
/// Return the register type for a given MVT, ensuring vectors are treated
|
|
|
|
/// as a series of gpr sized integers.
|
2018-07-28 21:25:19 +08:00
|
|
|
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
|
2017-08-04 06:12:30 +08:00
|
|
|
EVT VT) const override;
|
Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 22:37:08 +08:00
|
|
|
|
|
|
|
/// Return the number of registers for a given MVT, ensuring vectors are
|
|
|
|
/// treated as a series of gpr sized integers.
|
2017-08-04 06:12:30 +08:00
|
|
|
unsigned getNumRegistersForCallingConv(LLVMContext &Context,
|
2018-07-28 21:25:19 +08:00
|
|
|
CallingConv::ID CC,
|
2017-08-04 06:12:30 +08:00
|
|
|
EVT VT) const override;
|
Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 22:37:08 +08:00
|
|
|
|
|
|
|
/// Break down vectors to the correct number of gpr sized integers.
|
2017-08-04 06:12:30 +08:00
|
|
|
unsigned getVectorTypeBreakdownForCallingConv(
|
2018-07-28 21:25:19 +08:00
|
|
|
LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
|
Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 22:37:08 +08:00
|
|
|
unsigned &NumIntermediates, MVT &RegisterVT) const override;
|
|
|
|
|
|
|
|
/// Return the correct alignment for the current calling convention.
|
2017-08-04 06:12:30 +08:00
|
|
|
unsigned getABIAlignmentForCallingConv(Type *ArgTy,
|
|
|
|
DataLayout DL) const override {
|
Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 22:37:08 +08:00
|
|
|
if (ArgTy->isVectorTy())
|
|
|
|
return std::min(DL.getABITypeAlignment(ArgTy), 8U);
|
|
|
|
return DL.getABITypeAlignment(ArgTy);
|
|
|
|
}
|
|
|
|
|
2016-05-11 00:49:04 +08:00
|
|
|
ISD::NodeType getExtendForAtomicOps() const override {
|
|
|
|
return ISD::SIGN_EXTEND;
|
2016-03-24 23:38:38 +08:00
|
|
|
}
|
|
|
|
|
2014-04-29 15:58:02 +08:00
|
|
|
void LowerOperationWrapper(SDNode *N,
|
|
|
|
SmallVectorImpl<SDValue> &Results,
|
|
|
|
SelectionDAG &DAG) const override;
|
2012-09-22 07:58:31 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
2014-04-29 15:58:02 +08:00
|
|
|
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2012-09-22 07:58:31 +08:00
|
|
|
/// ReplaceNodeResults - Replace the results of node with an illegal result
|
|
|
|
/// type with new values built out of custom code.
|
|
|
|
///
|
2014-04-29 15:58:02 +08:00
|
|
|
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
|
|
|
|
SelectionDAG &DAG) const override;
|
2012-09-22 07:58:31 +08:00
|
|
|
|
2011-03-05 01:51:39 +08:00
|
|
|
/// getTargetNodeName - This method returns the name of a target specific
|
2007-06-06 15:42:06 +08:00
|
|
|
// DAG node.
|
2014-04-29 15:58:02 +08:00
|
|
|
const char *getTargetNodeName(unsigned Opcode) const override;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2008-03-10 23:42:14 +08:00
|
|
|
/// getSetCCResultType - get the ISD::SETCC result ValueType
|
2015-07-09 10:09:04 +08:00
|
|
|
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
|
|
|
|
EVT VT) const override;
|
2008-03-10 23:42:14 +08:00
|
|
|
|
2014-04-29 15:58:02 +08:00
|
|
|
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
|
2012-10-27 07:56:38 +08:00
|
|
|
|
2014-04-29 15:58:02 +08:00
|
|
|
MachineBasicBlock *
|
2016-07-01 06:52:52 +08:00
|
|
|
EmitInstrWithCustomInserter(MachineInstr &MI,
|
2014-04-29 15:58:02 +08:00
|
|
|
MachineBasicBlock *MBB) const override;
|
2013-03-13 08:54:29 +08:00
|
|
|
|
2019-01-18 05:50:37 +08:00
|
|
|
void AdjustInstrPostInstrSelection(MachineInstr &MI,
|
|
|
|
SDNode *Node) const override;
|
|
|
|
|
2014-11-03 00:09:29 +08:00
|
|
|
void HandleByVal(CCState *, unsigned &, unsigned) const override;
|
|
|
|
|
2015-07-10 01:40:29 +08:00
|
|
|
unsigned getRegisterByName(const char* RegName, EVT VT,
|
|
|
|
SelectionDAG &DAG) const override;
|
2015-01-10 01:21:30 +08:00
|
|
|
|
2015-11-07 09:11:31 +08:00
|
|
|
/// If a physical register, this returns the register that receives the
|
|
|
|
/// exception address on entry to an EH pad.
|
|
|
|
unsigned
|
|
|
|
getExceptionPointerRegister(const Constant *PersonalityFn) const override {
|
|
|
|
return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// If a physical register, this returns the register that receives the
|
|
|
|
/// exception typeid on entry to a landing pad.
|
|
|
|
unsigned
|
|
|
|
getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
|
|
|
|
return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
|
|
|
|
}
|
|
|
|
|
2015-09-08 17:07:03 +08:00
|
|
|
/// Returns true if a cast between SrcAS and DestAS is a noop.
|
|
|
|
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
|
|
|
|
// Mips doesn't have any special address spaces so we just reserve
|
|
|
|
// the first 256 for software use (e.g. OpenCL) and treat casts
|
|
|
|
// between them as noops.
|
|
|
|
return SrcAS < 256 && DestAS < 256;
|
|
|
|
}
|
|
|
|
|
2016-11-15 20:39:46 +08:00
|
|
|
bool isJumpTableRelative() const override {
|
2017-01-27 19:36:52 +08:00
|
|
|
return getTargetMachine().isPositionIndependent();
|
2016-11-15 20:39:46 +08:00
|
|
|
}
|
|
|
|
|
2018-04-11 23:12:32 +08:00
|
|
|
CCAssignFn *CCAssignFnForCall() const;
|
|
|
|
|
|
|
|
CCAssignFn *CCAssignFnForReturn() const;
|
|
|
|
|
2013-03-13 08:54:29 +08:00
|
|
|
protected:
|
|
|
|
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
|
2013-01-28 10:46:49 +08:00
|
|
|
|
2013-09-28 03:51:35 +08:00
|
|
|
// This method creates the following nodes, which are necessary for
|
|
|
|
// computing a local symbol's address:
|
|
|
|
//
|
|
|
|
// (add (load (wrapper $gp, %got(sym)), %lo(sym))
|
2014-03-26 21:59:42 +08:00
|
|
|
template <class NodeTy>
|
2016-06-12 23:39:02 +08:00
|
|
|
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
|
2014-03-26 21:59:42 +08:00
|
|
|
bool IsN32OrN64) const {
|
|
|
|
unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
|
2013-09-28 03:51:35 +08:00
|
|
|
SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
|
|
|
|
getTargetNode(N, Ty, DAG, GOTFlag));
|
2015-08-12 07:09:45 +08:00
|
|
|
SDValue Load =
|
|
|
|
DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
|
[SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends.
Summary:
Instead, we take a single flags arg (a bitset).
Also add a default 0 alignment, and change the order of arguments so the
alignment comes before the flags.
This greatly simplifies many callsites, and fixes a bug in
AMDGPUISelLowering, wherein the order of the args to getLoad was
inverted. It also greatly simplifies the process of adding another flag
to getLoad.
Reviewers: chandlerc, tstellarAMD
Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits
Differential Revision: http://reviews.llvm.org/D22249
llvm-svn: 275592
2016-07-16 02:27:10 +08:00
|
|
|
MachinePointerInfo::getGOT(DAG.getMachineFunction()));
|
2014-03-26 21:59:42 +08:00
|
|
|
unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
|
2013-09-28 03:51:35 +08:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
|
|
|
|
getTargetNode(N, Ty, DAG, LoFlag));
|
|
|
|
return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
|
|
|
|
}
|
|
|
|
|
|
|
|
// This method creates the following nodes, which are necessary for
|
|
|
|
// computing a global symbol's address:
|
|
|
|
//
|
|
|
|
// (load (wrapper $gp, %got(sym)))
|
2015-01-24 22:35:11 +08:00
|
|
|
template <class NodeTy>
|
2016-06-12 23:39:02 +08:00
|
|
|
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
|
2013-09-28 08:12:32 +08:00
|
|
|
unsigned Flag, SDValue Chain,
|
|
|
|
const MachinePointerInfo &PtrInfo) const {
|
2013-09-28 03:51:35 +08:00
|
|
|
SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
|
|
|
|
getTargetNode(N, Ty, DAG, Flag));
|
[SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends.
Summary:
Instead, we take a single flags arg (a bitset).
Also add a default 0 alignment, and change the order of arguments so the
alignment comes before the flags.
This greatly simplifies many callsites, and fixes a bug in
AMDGPUISelLowering, wherein the order of the args to getLoad was
inverted. It also greatly simplifies the process of adding another flag
to getLoad.
Reviewers: chandlerc, tstellarAMD
Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits
Differential Revision: http://reviews.llvm.org/D22249
llvm-svn: 275592
2016-07-16 02:27:10 +08:00
|
|
|
return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
|
2013-09-28 03:51:35 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// This method creates the following nodes, which are necessary for
|
|
|
|
// computing a global symbol's address in large-GOT mode:
|
|
|
|
//
|
|
|
|
// (load (wrapper (add %hi(sym), $gp), %lo(sym)))
|
2015-01-24 22:35:11 +08:00
|
|
|
template <class NodeTy>
|
2016-06-12 23:39:02 +08:00
|
|
|
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
|
2015-01-24 22:35:11 +08:00
|
|
|
SelectionDAG &DAG, unsigned HiFlag,
|
|
|
|
unsigned LoFlag, SDValue Chain,
|
2013-09-28 08:12:32 +08:00
|
|
|
const MachinePointerInfo &PtrInfo) const {
|
2017-01-27 19:36:52 +08:00
|
|
|
SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
|
|
|
|
getTargetNode(N, Ty, DAG, HiFlag));
|
2013-09-28 03:51:35 +08:00
|
|
|
Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
|
|
|
|
SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
|
|
|
|
getTargetNode(N, Ty, DAG, LoFlag));
|
[SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends.
Summary:
Instead, we take a single flags arg (a bitset).
Also add a default 0 alignment, and change the order of arguments so the
alignment comes before the flags.
This greatly simplifies many callsites, and fixes a bug in
AMDGPUISelLowering, wherein the order of the args to getLoad was
inverted. It also greatly simplifies the process of adding another flag
to getLoad.
Reviewers: chandlerc, tstellarAMD
Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits
Differential Revision: http://reviews.llvm.org/D22249
llvm-svn: 275592
2016-07-16 02:27:10 +08:00
|
|
|
return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
|
2013-09-28 03:51:35 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// This method creates the following nodes, which are necessary for
|
|
|
|
// computing a symbol's address in non-PIC mode:
|
|
|
|
//
|
|
|
|
// (add %hi(sym), %lo(sym))
|
2017-01-27 19:36:52 +08:00
|
|
|
//
|
|
|
|
// This method covers O32, N32 and N64 in sym32 mode.
|
2015-01-24 22:35:11 +08:00
|
|
|
template <class NodeTy>
|
2016-06-12 23:39:02 +08:00
|
|
|
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
|
2015-01-24 22:35:11 +08:00
|
|
|
SelectionDAG &DAG) const {
|
2013-09-28 03:51:35 +08:00
|
|
|
SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
|
|
|
|
SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
|
|
|
|
return DAG.getNode(ISD::ADD, DL, Ty,
|
|
|
|
DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
|
|
|
|
DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
|
2017-01-27 19:36:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// This method creates the following nodes, which are necessary for
|
|
|
|
// computing a symbol's address in non-PIC mode for N64.
|
|
|
|
//
|
|
|
|
// (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
|
|
|
|
// 16), %lo(%sym))
|
|
|
|
//
|
|
|
|
// FIXME: This method is not efficent for (micro)MIPS64R6.
|
|
|
|
template <class NodeTy>
|
|
|
|
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
|
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
|
|
|
|
SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
|
|
|
|
|
|
|
|
SDValue Highest =
|
|
|
|
DAG.getNode(MipsISD::Highest, DL, Ty,
|
|
|
|
getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
|
|
|
|
SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
|
|
|
|
SDValue HigherPart =
|
|
|
|
DAG.getNode(ISD::ADD, DL, Ty, Highest,
|
|
|
|
DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
|
|
|
|
SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
|
|
|
|
SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
|
|
|
|
SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
|
|
|
|
DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
|
|
|
|
SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
|
|
|
|
DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
|
|
|
|
}
|
2013-03-13 08:54:29 +08:00
|
|
|
|
2014-11-06 21:20:12 +08:00
|
|
|
// This method creates the following nodes, which are necessary for
|
|
|
|
// computing a symbol's address using gp-relative addressing:
|
|
|
|
//
|
|
|
|
// (add $gp, %gp_rel(sym))
|
2015-01-24 22:35:11 +08:00
|
|
|
template <class NodeTy>
|
2016-06-12 23:39:02 +08:00
|
|
|
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
|
2017-08-11 22:36:05 +08:00
|
|
|
SelectionDAG &DAG, bool IsN64) const {
|
2014-11-06 21:20:12 +08:00
|
|
|
SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
|
2017-08-11 22:36:05 +08:00
|
|
|
return DAG.getNode(
|
|
|
|
ISD::ADD, DL, Ty,
|
|
|
|
DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
|
|
|
|
DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
|
2014-11-06 21:20:12 +08:00
|
|
|
}
|
|
|
|
|
2013-03-13 08:54:29 +08:00
|
|
|
/// This function fills Ops, which is the list of operands that will later
|
|
|
|
/// be used when a function call node is created. It also generates
|
|
|
|
/// copyToReg nodes to set up argument registers.
|
|
|
|
virtual void
|
|
|
|
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
2017-08-04 06:12:30 +08:00
|
|
|
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
|
2013-03-13 08:54:29 +08:00
|
|
|
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
2014-10-01 16:22:21 +08:00
|
|
|
bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
|
|
|
|
SDValue Chain) const;
|
2013-01-24 12:24:02 +08:00
|
|
|
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-11 06:25:39 +08:00
|
|
|
protected:
|
2013-09-07 08:52:30 +08:00
|
|
|
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// Subtarget Info
|
2014-07-19 06:55:25 +08:00
|
|
|
const MipsSubtarget &Subtarget;
|
2015-01-30 07:27:36 +08:00
|
|
|
// Cache the ABI from the TargetMachine, we use it everywhere.
|
|
|
|
const MipsABIInfo &ABI;
|
2012-02-28 15:46:26 +08:00
|
|
|
|
2013-03-13 08:54:29 +08:00
|
|
|
private:
|
2013-09-28 03:51:35 +08:00
|
|
|
// Create a TargetGlobalAddress node.
|
|
|
|
SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
|
|
|
|
unsigned Flag) const;
|
|
|
|
|
|
|
|
// Create a TargetExternalSymbol node.
|
|
|
|
SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
|
|
|
|
unsigned Flag) const;
|
|
|
|
|
|
|
|
// Create a TargetBlockAddress node.
|
|
|
|
SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
|
|
|
|
unsigned Flag) const;
|
|
|
|
|
|
|
|
// Create a TargetJumpTable node.
|
|
|
|
SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
|
|
|
|
unsigned Flag) const;
|
|
|
|
|
|
|
|
// Create a TargetConstantPool node.
|
|
|
|
SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
|
|
|
|
unsigned Flag) const;
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-11 06:25:39 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Lower Operand helpers
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
2016-06-12 23:39:02 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
|
|
SmallVectorImpl<SDValue> &InVals,
|
2014-09-26 18:06:12 +08:00
|
|
|
TargetLowering::CallLoweringInfo &CLI) const;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Lower Operand specifics
|
2013-03-12 08:16:36 +08:00
|
|
|
SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
2014-08-01 17:17:39 +08:00
|
|
|
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
|
2013-03-12 08:16:36 +08:00
|
|
|
SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
|
|
|
|
SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
|
|
|
|
SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
|
2012-06-15 05:10:56 +08:00
|
|
|
bool IsSRA) const;
|
Add ISD::EH_DWARF_CFA, simplify @llvm.eh.dwarf.cfa on Mips, fix on PowerPC
LLVM has an @llvm.eh.dwarf.cfa intrinsic, used to lower the GCC-compatible
__builtin_dwarf_cfa() builtin. As pointed out in PR26761, this is currently
broken on PowerPC (and likely on ARM as well). Currently, @llvm.eh.dwarf.cfa is
lowered using:
ADD(FRAMEADDR, FRAME_TO_ARGS_OFFSET)
where FRAME_TO_ARGS_OFFSET defaults to the constant zero. On x86,
FRAME_TO_ARGS_OFFSET is lowered to 2*SlotSize. This setup, however, does not
work for PowerPC. Because of the way that the stack layout works, the canonical
frame address is not exactly (FRAMEADDR + FRAME_TO_ARGS_OFFSET) on PowerPC
(there is a lower save-area offset as well), so it is not just a matter of
implementing FRAME_TO_ARGS_OFFSET for PowerPC (unless we redefine its
semantics -- We can do that, since it is currently used only for
@llvm.eh.dwarf.cfa lowering, but the better to directly lower the CFA construct
itself (since it can be easily represented as a fixed-offset FrameIndex)). Mips
currently does this, but by using a custom lowering for ADD that specifically
recognizes the (FRAMEADDR, FRAME_TO_ARGS_OFFSET) pattern.
This change introduces a ISD::EH_DWARF_CFA node, which by default expands using
the existing logic, but can be directly lowered by the target. Mips is updated
to use this method (which simplifies its implementation, and I suspect makes it
more robust), and updates PowerPC to do the same.
Fixes PR26761.
Differential Revision: https://reviews.llvm.org/D24038
llvm-svn: 280350
2016-09-01 18:28:47 +08:00
|
|
|
SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
|
2013-05-17 05:17:15 +08:00
|
|
|
SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2013-03-12 08:16:36 +08:00
|
|
|
/// isEligibleForTailCallOptimization - Check whether the call is eligible
|
2012-10-20 05:47:33 +08:00
|
|
|
/// for tail call optimization.
|
2013-03-13 08:54:29 +08:00
|
|
|
virtual bool
|
2014-11-03 00:09:29 +08:00
|
|
|
isEligibleForTailCallOptimization(const CCState &CCInfo,
|
2013-03-13 08:54:29 +08:00
|
|
|
unsigned NextStackOffset,
|
2014-11-03 00:09:29 +08:00
|
|
|
const MipsFunctionInfo &FI) const = 0;
|
2012-10-20 05:47:33 +08:00
|
|
|
|
2012-10-27 08:10:18 +08:00
|
|
|
/// copyByValArg - Copy argument registers which were used to pass a byval
|
|
|
|
/// argument to the stack. Create a stack frame object for the byval
|
|
|
|
/// argument.
|
2016-06-12 23:39:02 +08:00
|
|
|
void copyByValRegs(SDValue Chain, const SDLoc &DL,
|
|
|
|
std::vector<SDValue> &OutChains, SelectionDAG &DAG,
|
|
|
|
const ISD::ArgFlagsTy &Flags,
|
2012-10-27 08:10:18 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals,
|
2014-11-07 23:33:08 +08:00
|
|
|
const Argument *FuncArg, unsigned FirstReg,
|
|
|
|
unsigned LastReg, const CCValAssign &VA,
|
|
|
|
MipsCCState &State) const;
|
2012-10-27 08:10:18 +08:00
|
|
|
|
2012-10-27 08:16:36 +08:00
|
|
|
/// passByValArg - Pass a byval argument in registers or on stack.
|
2017-10-20 22:35:41 +08:00
|
|
|
void passByValArg(SDValue Chain, const SDLoc &DL,
|
|
|
|
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
|
|
|
|
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
|
|
|
|
MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
|
|
|
|
unsigned FirstReg, unsigned LastReg,
|
|
|
|
const ISD::ArgFlagsTy &Flags, bool isLittle,
|
|
|
|
const CCValAssign &VA) const;
|
2012-10-27 08:16:36 +08:00
|
|
|
|
2012-10-27 08:21:13 +08:00
|
|
|
/// writeVarArgRegs - Write variable function arguments passed in registers
|
|
|
|
/// to the stack. Also create a stack frame object for the first variable
|
|
|
|
/// argument.
|
2014-11-07 23:33:08 +08:00
|
|
|
void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
|
2016-06-12 23:39:02 +08:00
|
|
|
const SDLoc &DL, SelectionDAG &DAG,
|
|
|
|
CCState &State) const;
|
2012-10-27 08:21:13 +08:00
|
|
|
|
2014-04-29 15:58:02 +08:00
|
|
|
SDValue
|
2016-06-12 23:39:02 +08:00
|
|
|
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
2012-10-31 03:23:25 +08:00
|
|
|
SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
|
2016-06-12 23:39:02 +08:00
|
|
|
SDValue Arg, const SDLoc &DL, bool IsTailCall,
|
2012-10-31 03:23:25 +08:00
|
|
|
SelectionDAG &DAG) const;
|
|
|
|
|
2014-04-29 15:58:02 +08:00
|
|
|
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
2014-04-29 15:58:02 +08:00
|
|
|
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
|
|
|
|
bool isVarArg,
|
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
|
|
LLVMContext &Context) const override;
|
|
|
|
|
2016-06-12 23:39:02 +08:00
|
|
|
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
2014-04-29 15:58:02 +08:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
2016-06-12 23:39:02 +08:00
|
|
|
const SDLoc &dl, SelectionDAG &DAG) const override;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
2016-06-12 23:39:02 +08:00
|
|
|
SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
|
|
|
|
const SDLoc &DL, SelectionDAG &DAG) const;
|
2015-10-26 20:38:43 +08:00
|
|
|
|
2015-03-23 20:28:13 +08:00
|
|
|
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
|
|
|
|
|
2007-08-22 00:09:25 +08:00
|
|
|
// Inline asm support
|
2015-07-06 03:29:18 +08:00
|
|
|
ConstraintType getConstraintType(StringRef Constraint) const override;
|
2007-08-22 00:09:25 +08:00
|
|
|
|
2011-04-16 05:51:11 +08:00
|
|
|
/// Examine constraint string and operand type and determine a weight value.
|
|
|
|
/// The operand object must already have been set up with the operand type.
|
2010-10-30 01:29:13 +08:00
|
|
|
ConstraintWeight getSingleConstraintMatchWeight(
|
2014-04-29 15:58:02 +08:00
|
|
|
AsmOperandInfo &info, const char *constraint) const override;
|
2010-10-30 01:29:13 +08:00
|
|
|
|
2013-08-14 08:21:25 +08:00
|
|
|
/// This function parses registers that appear in inline-asm constraints.
|
|
|
|
/// It returns pair (0, 0) on failure.
|
|
|
|
std::pair<unsigned, const TargetRegisterClass *>
|
2014-08-31 00:48:02 +08:00
|
|
|
parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
|
2013-08-14 08:21:25 +08:00
|
|
|
|
2015-02-27 06:38:43 +08:00
|
|
|
std::pair<unsigned, const TargetRegisterClass *>
|
|
|
|
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
2015-07-06 03:29:18 +08:00
|
|
|
StringRef Constraint, MVT VT) const override;
|
2007-08-22 00:09:25 +08:00
|
|
|
|
2012-05-07 11:13:32 +08:00
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
|
|
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
|
|
|
|
/// true it means one of the asm constraint of the inline asm instruction
|
|
|
|
/// being processed is 'm'.
|
2014-04-29 15:58:02 +08:00
|
|
|
void LowerAsmOperandForConstraint(SDValue Op,
|
|
|
|
std::string &Constraint,
|
|
|
|
std::vector<SDValue> &Ops,
|
|
|
|
SelectionDAG &DAG) const override;
|
2012-05-07 11:13:32 +08:00
|
|
|
|
2015-07-06 03:29:18 +08:00
|
|
|
unsigned
|
|
|
|
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
|
2015-03-24 19:26:34 +08:00
|
|
|
if (ConstraintCode == "R")
|
|
|
|
return InlineAsm::Constraint_R;
|
|
|
|
else if (ConstraintCode == "ZC")
|
|
|
|
return InlineAsm::Constraint_ZC;
|
|
|
|
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
|
2015-03-16 21:13:41 +08:00
|
|
|
}
|
|
|
|
|
2015-07-09 10:09:40 +08:00
|
|
|
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
|
2017-07-21 19:59:37 +08:00
|
|
|
Type *Ty, unsigned AS,
|
|
|
|
Instruction *I = nullptr) const override;
|
2012-11-17 08:25:41 +08:00
|
|
|
|
2014-04-29 15:58:02 +08:00
|
|
|
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
|
2009-10-28 03:56:55 +08:00
|
|
|
|
2014-04-29 15:58:02 +08:00
|
|
|
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
|
|
|
|
unsigned SrcAlign,
|
|
|
|
bool IsMemset, bool ZeroMemset,
|
|
|
|
bool MemcpyStrSrc,
|
2019-04-30 16:38:12 +08:00
|
|
|
const AttributeList &FuncAttributes) const override;
|
2012-06-14 03:33:32 +08:00
|
|
|
|
2009-10-28 03:56:55 +08:00
|
|
|
/// isFPImmLegal - Returns true if the target can instruction select the
|
|
|
|
/// specified FP immediate natively. If false, the legalizer will
|
|
|
|
/// materialize the FP immediate as a load from a constant pool.
|
2019-03-19 02:40:07 +08:00
|
|
|
bool isFPImmLegal(const APFloat &Imm, EVT VT,
|
|
|
|
bool ForCodeSize) const override;
|
2011-05-31 10:54:07 +08:00
|
|
|
|
2014-04-29 15:58:02 +08:00
|
|
|
unsigned getJumpTableEncoding() const override;
|
2015-05-12 09:26:05 +08:00
|
|
|
bool useSoftFloat() const override;
|
2012-02-03 12:33:00 +08:00
|
|
|
|
2016-03-17 06:12:04 +08:00
|
|
|
bool shouldInsertFencesForAtomic(const Instruction *I) const override {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-06-16 21:13:03 +08:00
|
|
|
/// Emit a sign-extension using sll/sra, seb, or seh appropriately.
|
2016-07-01 06:52:52 +08:00
|
|
|
MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
|
2014-06-16 21:13:03 +08:00
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned Size, unsigned DstReg,
|
|
|
|
unsigned SrcRec) const;
|
|
|
|
|
2018-07-05 17:27:05 +08:00
|
|
|
MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
|
|
|
|
MachineBasicBlock *BB) const;
|
2016-07-01 06:52:52 +08:00
|
|
|
MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
|
|
|
|
MachineBasicBlock *BB,
|
2018-07-05 17:27:05 +08:00
|
|
|
unsigned Size) const;
|
2016-07-01 06:52:52 +08:00
|
|
|
MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
|
2018-07-05 17:27:05 +08:00
|
|
|
MachineBasicBlock *BB) const;
|
2016-07-01 06:52:52 +08:00
|
|
|
MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
|
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned Size) const;
|
|
|
|
MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
|
|
|
|
bool isFPCmp, unsigned Opc) const;
|
2019-01-14 20:28:51 +08:00
|
|
|
MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
|
|
|
|
MachineBasicBlock *BB) const;
|
2007-06-06 15:42:06 +08:00
|
|
|
};
|
2013-03-13 08:54:29 +08:00
|
|
|
|
|
|
|
/// Create MipsTargetLowering objects.
|
2014-07-19 07:25:04 +08:00
|
|
|
const MipsTargetLowering *
|
2014-09-20 07:30:42 +08:00
|
|
|
createMips16TargetLowering(const MipsTargetMachine &TM,
|
|
|
|
const MipsSubtarget &STI);
|
2014-07-19 07:25:04 +08:00
|
|
|
const MipsTargetLowering *
|
2014-09-20 07:30:42 +08:00
|
|
|
createMipsSETargetLowering(const MipsTargetMachine &TM,
|
|
|
|
const MipsSubtarget &STI);
|
2014-04-18 06:15:34 +08:00
|
|
|
|
2017-08-04 06:12:30 +08:00
|
|
|
namespace Mips {
|
|
|
|
|
|
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
|
|
const TargetLibraryInfo *libInfo);
|
|
|
|
|
|
|
|
} // end namespace Mips
|
|
|
|
|
|
|
|
} // end namespace llvm
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2017-08-04 06:12:30 +08:00
|
|
|
#endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
|